1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * A V4L2 driver for Sony IMX219 cameras.
4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
5 *
6 * Based on Sony imx258 camera driver
7 * Copyright (C) 2018 Intel Corporation
8 *
9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10 * Copyright 2018 Qtechnology A/S
11 *
12 * Flip handling taken from the Sony IMX319 driver.
13 * Copyright (C) 2018 Intel Corporation
14 *
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25
26 #include <media/v4l2-cci.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-mediabus.h>
32
33 /* Chip ID */
34 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
35 #define IMX219_CHIP_ID 0x0219
36
37 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
38 #define IMX219_MODE_STANDBY 0x00
39 #define IMX219_MODE_STREAMING 0x01
40
41 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
42 #define IMX219_CSI_2_LANE_MODE 0x01
43 #define IMX219_CSI_4_LANE_MODE 0x03
44
45 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
46 #define IMX219_DPHY_CTRL_TIMING_AUTO 0
47 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1
48
49 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
50 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
51
52 /* Analog gain control */
53 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
54 #define IMX219_ANA_GAIN_MIN 0
55 #define IMX219_ANA_GAIN_MAX 232
56 #define IMX219_ANA_GAIN_STEP 1
57 #define IMX219_ANA_GAIN_DEFAULT 0x0
58
59 /* Digital gain control */
60 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
61 #define IMX219_DGTL_GAIN_MIN 0x0100
62 #define IMX219_DGTL_GAIN_MAX 0x0fff
63 #define IMX219_DGTL_GAIN_DEFAULT 0x0100
64 #define IMX219_DGTL_GAIN_STEP 1
65
66 /* Exposure control */
67 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
68 #define IMX219_EXPOSURE_MIN 4
69 #define IMX219_EXPOSURE_STEP 1
70 #define IMX219_EXPOSURE_DEFAULT 0x640
71 #define IMX219_EXPOSURE_MAX 65535
72
73 /* V_TIMING internal */
74 #define IMX219_REG_VTS CCI_REG16(0x0160)
75 #define IMX219_VTS_MAX 0xffff
76
77 #define IMX219_VBLANK_MIN 32
78
79 /* HBLANK control - read only */
80 #define IMX219_PPL_DEFAULT 3448
81
82 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162)
83 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
84 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
85 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
86 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
87 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c)
88 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e)
89 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
90 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
91 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
92
93 /* Binning Mode */
94 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
95 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
96 #define IMX219_BINNING_NONE 0x00
97 #define IMX219_BINNING_X2 0x01
98 #define IMX219_BINNING_X2_ANALOG 0x03
99
100 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c)
101
102 /* PLL Settings */
103 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
104 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
105 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
106 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
107 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
108 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
109 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
110 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
111
112 /* Test Pattern Control */
113 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600)
114 #define IMX219_TEST_PATTERN_DISABLE 0
115 #define IMX219_TEST_PATTERN_SOLID_COLOR 1
116 #define IMX219_TEST_PATTERN_COLOR_BARS 2
117 #define IMX219_TEST_PATTERN_GREY_COLOR 3
118 #define IMX219_TEST_PATTERN_PN9 4
119
120 /* Test pattern colour components */
121 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602)
122 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604)
123 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606)
124 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608)
125 #define IMX219_TESTP_COLOUR_MIN 0
126 #define IMX219_TESTP_COLOUR_MAX 0x03ff
127 #define IMX219_TESTP_COLOUR_STEP 1
128
129 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624)
130 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626)
131
132 /* External clock frequency is 24.0M */
133 #define IMX219_XCLK_FREQ 24000000
134
135 /* Pixel rate is fixed for all the modes */
136 #define IMX219_PIXEL_RATE 182400000
137 #define IMX219_PIXEL_RATE_4LANE 281600000
138
139 #define IMX219_DEFAULT_LINK_FREQ 456000000
140 #define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000
141 #define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000
142
143 /* IMX219 native and active pixel array size. */
144 #define IMX219_NATIVE_WIDTH 3296U
145 #define IMX219_NATIVE_HEIGHT 2480U
146 #define IMX219_PIXEL_ARRAY_LEFT 8U
147 #define IMX219_PIXEL_ARRAY_TOP 8U
148 #define IMX219_PIXEL_ARRAY_WIDTH 3280U
149 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U
150
151 /* Mode : resolution and related config&values */
152 struct imx219_mode {
153 /* Frame width */
154 unsigned int width;
155 /* Frame height */
156 unsigned int height;
157
158 /* V-timing */
159 unsigned int vts_def;
160 };
161
162 static const struct cci_reg_sequence imx219_common_regs[] = {
163 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */
164
165 /* To Access Addresses 3000-5fff, send the following commands */
166 { CCI_REG8(0x30eb), 0x05 },
167 { CCI_REG8(0x30eb), 0x0c },
168 { CCI_REG8(0x300a), 0xff },
169 { CCI_REG8(0x300b), 0xff },
170 { CCI_REG8(0x30eb), 0x05 },
171 { CCI_REG8(0x30eb), 0x09 },
172
173 /* Undocumented registers */
174 { CCI_REG8(0x455e), 0x00 },
175 { CCI_REG8(0x471e), 0x4b },
176 { CCI_REG8(0x4767), 0x0f },
177 { CCI_REG8(0x4750), 0x14 },
178 { CCI_REG8(0x4540), 0x00 },
179 { CCI_REG8(0x47b4), 0x14 },
180 { CCI_REG8(0x4713), 0x30 },
181 { CCI_REG8(0x478b), 0x10 },
182 { CCI_REG8(0x478f), 0x10 },
183 { CCI_REG8(0x4793), 0x10 },
184 { CCI_REG8(0x4797), 0x0e },
185 { CCI_REG8(0x479b), 0x0e },
186
187 /* Frame Bank Register Group "A" */
188 { IMX219_REG_LINE_LENGTH_A, 3448 },
189 { IMX219_REG_X_ODD_INC_A, 1 },
190 { IMX219_REG_Y_ODD_INC_A, 1 },
191
192 /* Output setup registers */
193 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO },
194 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
195 };
196
197 static const struct cci_reg_sequence imx219_2lane_regs[] = {
198 /* PLL Clock Table */
199 { IMX219_REG_VTPXCK_DIV, 5 },
200 { IMX219_REG_VTSYCK_DIV, 1 },
201 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
202 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
203 { IMX219_REG_PLL_VT_MPY, 57 },
204 { IMX219_REG_OPSYCK_DIV, 1 },
205 { IMX219_REG_PLL_OP_MPY, 114 },
206
207 /* 2-Lane CSI Mode */
208 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE },
209 };
210
211 static const struct cci_reg_sequence imx219_4lane_regs[] = {
212 /* PLL Clock Table */
213 { IMX219_REG_VTPXCK_DIV, 5 },
214 { IMX219_REG_VTSYCK_DIV, 1 },
215 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
216 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
217 { IMX219_REG_PLL_VT_MPY, 88 },
218 { IMX219_REG_OPSYCK_DIV, 1 },
219 { IMX219_REG_PLL_OP_MPY, 91 },
220
221 /* 4-Lane CSI Mode */
222 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE },
223 };
224
225 static const s64 imx219_link_freq_menu[] = {
226 IMX219_DEFAULT_LINK_FREQ,
227 };
228
229 static const s64 imx219_link_freq_4lane_menu[] = {
230 IMX219_DEFAULT_LINK_FREQ_4LANE,
231 /*
232 * This will never be advertised to userspace, but will be used for
233 * v4l2_link_freq_to_bitmap
234 */
235 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED,
236 };
237
238 static const char * const imx219_test_pattern_menu[] = {
239 "Disabled",
240 "Color Bars",
241 "Solid Color",
242 "Grey Color Bars",
243 "PN9"
244 };
245
246 static const int imx219_test_pattern_val[] = {
247 IMX219_TEST_PATTERN_DISABLE,
248 IMX219_TEST_PATTERN_COLOR_BARS,
249 IMX219_TEST_PATTERN_SOLID_COLOR,
250 IMX219_TEST_PATTERN_GREY_COLOR,
251 IMX219_TEST_PATTERN_PN9,
252 };
253
254 /* regulator supplies */
255 static const char * const imx219_supply_name[] = {
256 /* Supplies can be enabled in any order */
257 "VANA", /* Analog (2.8V) supply */
258 "VDIG", /* Digital Core (1.8V) supply */
259 "VDDL", /* IF (1.2V) supply */
260 };
261
262 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
263
264 /*
265 * The supported formats.
266 * This table MUST contain 4 entries per format, to cover the various flip
267 * combinations in the order
268 * - no flip
269 * - h flip
270 * - v flip
271 * - h&v flips
272 */
273 static const u32 imx219_mbus_formats[] = {
274 MEDIA_BUS_FMT_SRGGB10_1X10,
275 MEDIA_BUS_FMT_SGRBG10_1X10,
276 MEDIA_BUS_FMT_SGBRG10_1X10,
277 MEDIA_BUS_FMT_SBGGR10_1X10,
278
279 MEDIA_BUS_FMT_SRGGB8_1X8,
280 MEDIA_BUS_FMT_SGRBG8_1X8,
281 MEDIA_BUS_FMT_SGBRG8_1X8,
282 MEDIA_BUS_FMT_SBGGR8_1X8,
283 };
284
285 /*
286 * Initialisation delay between XCLR low->high and the moment when the sensor
287 * can start capture (i.e. can leave software stanby) must be not less than:
288 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
289 * where
290 * t4 is fixed, and is max 200uS,
291 * t5 is fixed, and is 6000uS,
292 * t6 depends on the sensor external clock, and is max 32000 clock periods.
293 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
294 * So for any acceptable external clock t6 is always within the range of
295 * 1185 to 5333 uS, and is always less than t5.
296 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
297 * initialize the sensor over I2C, and then exit the software standby.
298 *
299 * This start-up time can be optimized a bit more, if we start the writes
300 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
301 * initialization over I2C may complete before (t4+t5) expires, and we must
302 * ensure that capture is not started before (t4+t5).
303 *
304 * This delay doesn't account for the power supply startup time. If needed,
305 * this should be taken care of via the regulator framework. E.g. in the
306 * case of DT for regulator-fixed one should define the startup-delay-us
307 * property.
308 */
309 #define IMX219_XCLR_MIN_DELAY_US 6200
310 #define IMX219_XCLR_DELAY_RANGE_US 1000
311
312 /* Mode configs */
313 static const struct imx219_mode supported_modes[] = {
314 {
315 /* 8MPix 15fps mode */
316 .width = 3280,
317 .height = 2464,
318 .vts_def = 3526,
319 },
320 {
321 /* 1080P 30fps cropped */
322 .width = 1920,
323 .height = 1080,
324 .vts_def = 1763,
325 },
326 {
327 /* 2x2 binned 30fps mode */
328 .width = 1640,
329 .height = 1232,
330 .vts_def = 1763,
331 },
332 {
333 /* 640x480 30fps mode */
334 .width = 640,
335 .height = 480,
336 .vts_def = 1763,
337 },
338 };
339
340 struct imx219 {
341 struct v4l2_subdev sd;
342 struct media_pad pad;
343
344 struct regmap *regmap;
345 struct clk *xclk; /* system clock to IMX219 */
346 u32 xclk_freq;
347
348 struct gpio_desc *reset_gpio;
349 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
350
351 struct v4l2_ctrl_handler ctrl_handler;
352 /* V4L2 Controls */
353 struct v4l2_ctrl *pixel_rate;
354 struct v4l2_ctrl *link_freq;
355 struct v4l2_ctrl *exposure;
356 struct v4l2_ctrl *vflip;
357 struct v4l2_ctrl *hflip;
358 struct v4l2_ctrl *vblank;
359 struct v4l2_ctrl *hblank;
360
361 /* Two or Four lanes */
362 u8 lanes;
363 };
364
to_imx219(struct v4l2_subdev * _sd)365 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
366 {
367 return container_of(_sd, struct imx219, sd);
368 }
369
370 /* Get bayer order based on flip setting. */
imx219_get_format_code(struct imx219 * imx219,u32 code)371 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
372 {
373 unsigned int i;
374
375 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
376 if (imx219_mbus_formats[i] == code)
377 break;
378
379 if (i >= ARRAY_SIZE(imx219_mbus_formats))
380 i = 0;
381
382 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
383 (imx219->hflip->val ? 1 : 0);
384
385 return imx219_mbus_formats[i];
386 }
387
388 /* -----------------------------------------------------------------------------
389 * Controls
390 */
391
imx219_set_ctrl(struct v4l2_ctrl * ctrl)392 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
393 {
394 struct imx219 *imx219 =
395 container_of(ctrl->handler, struct imx219, ctrl_handler);
396 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
397 const struct v4l2_mbus_framefmt *format;
398 struct v4l2_subdev_state *state;
399 int ret = 0;
400
401 state = v4l2_subdev_get_locked_active_state(&imx219->sd);
402 format = v4l2_subdev_state_get_format(state, 0);
403
404 if (ctrl->id == V4L2_CID_VBLANK) {
405 int exposure_max, exposure_def;
406
407 /* Update max exposure while meeting expected vblanking */
408 exposure_max = format->height + ctrl->val - 4;
409 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
410 exposure_max : IMX219_EXPOSURE_DEFAULT;
411 __v4l2_ctrl_modify_range(imx219->exposure,
412 imx219->exposure->minimum,
413 exposure_max, imx219->exposure->step,
414 exposure_def);
415 }
416
417 /*
418 * Applying V4L2 control value only happens
419 * when power is up for streaming
420 */
421 if (pm_runtime_get_if_in_use(&client->dev) == 0)
422 return 0;
423
424 switch (ctrl->id) {
425 case V4L2_CID_ANALOGUE_GAIN:
426 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN,
427 ctrl->val, &ret);
428 break;
429 case V4L2_CID_EXPOSURE:
430 cci_write(imx219->regmap, IMX219_REG_EXPOSURE,
431 ctrl->val, &ret);
432 break;
433 case V4L2_CID_DIGITAL_GAIN:
434 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN,
435 ctrl->val, &ret);
436 break;
437 case V4L2_CID_TEST_PATTERN:
438 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN,
439 imx219_test_pattern_val[ctrl->val], &ret);
440 break;
441 case V4L2_CID_HFLIP:
442 case V4L2_CID_VFLIP:
443 cci_write(imx219->regmap, IMX219_REG_ORIENTATION,
444 imx219->hflip->val | imx219->vflip->val << 1, &ret);
445 break;
446 case V4L2_CID_VBLANK:
447 cci_write(imx219->regmap, IMX219_REG_VTS,
448 format->height + ctrl->val, &ret);
449 break;
450 case V4L2_CID_TEST_PATTERN_RED:
451 cci_write(imx219->regmap, IMX219_REG_TESTP_RED,
452 ctrl->val, &ret);
453 break;
454 case V4L2_CID_TEST_PATTERN_GREENR:
455 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR,
456 ctrl->val, &ret);
457 break;
458 case V4L2_CID_TEST_PATTERN_BLUE:
459 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE,
460 ctrl->val, &ret);
461 break;
462 case V4L2_CID_TEST_PATTERN_GREENB:
463 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB,
464 ctrl->val, &ret);
465 break;
466 default:
467 dev_info(&client->dev,
468 "ctrl(id:0x%x,val:0x%x) is not handled\n",
469 ctrl->id, ctrl->val);
470 ret = -EINVAL;
471 break;
472 }
473
474 pm_runtime_put(&client->dev);
475
476 return ret;
477 }
478
479 static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
480 .s_ctrl = imx219_set_ctrl,
481 };
482
imx219_get_pixel_rate(struct imx219 * imx219)483 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219)
484 {
485 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
486 }
487
488 /* Initialize control handlers */
imx219_init_controls(struct imx219 * imx219)489 static int imx219_init_controls(struct imx219 *imx219)
490 {
491 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
492 const struct imx219_mode *mode = &supported_modes[0];
493 struct v4l2_ctrl_handler *ctrl_hdlr;
494 struct v4l2_fwnode_device_properties props;
495 int exposure_max, exposure_def, hblank;
496 int i, ret;
497
498 ctrl_hdlr = &imx219->ctrl_handler;
499 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
500 if (ret)
501 return ret;
502
503 /* By default, PIXEL_RATE is read only */
504 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
505 V4L2_CID_PIXEL_RATE,
506 imx219_get_pixel_rate(imx219),
507 imx219_get_pixel_rate(imx219), 1,
508 imx219_get_pixel_rate(imx219));
509
510 imx219->link_freq =
511 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops,
512 V4L2_CID_LINK_FREQ,
513 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0,
514 (imx219->lanes == 2) ? imx219_link_freq_menu :
515 imx219_link_freq_4lane_menu);
516 if (imx219->link_freq)
517 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
518
519 /* Initial vblank/hblank/exposure parameters based on current mode */
520 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
521 V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
522 IMX219_VTS_MAX - mode->height, 1,
523 mode->vts_def - mode->height);
524 hblank = IMX219_PPL_DEFAULT - mode->width;
525 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
526 V4L2_CID_HBLANK, hblank, hblank,
527 1, hblank);
528 if (imx219->hblank)
529 imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
530 exposure_max = mode->vts_def - 4;
531 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
532 exposure_max : IMX219_EXPOSURE_DEFAULT;
533 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
534 V4L2_CID_EXPOSURE,
535 IMX219_EXPOSURE_MIN, exposure_max,
536 IMX219_EXPOSURE_STEP,
537 exposure_def);
538
539 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
540 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
541 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
542
543 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
544 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
545 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
546
547 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
548 V4L2_CID_HFLIP, 0, 1, 1, 0);
549 if (imx219->hflip)
550 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
551
552 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
553 V4L2_CID_VFLIP, 0, 1, 1, 0);
554 if (imx219->vflip)
555 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
556
557 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops,
558 V4L2_CID_TEST_PATTERN,
559 ARRAY_SIZE(imx219_test_pattern_menu) - 1,
560 0, 0, imx219_test_pattern_menu);
561 for (i = 0; i < 4; i++) {
562 /*
563 * The assumption is that
564 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
565 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
566 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
567 */
568 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
569 V4L2_CID_TEST_PATTERN_RED + i,
570 IMX219_TESTP_COLOUR_MIN,
571 IMX219_TESTP_COLOUR_MAX,
572 IMX219_TESTP_COLOUR_STEP,
573 IMX219_TESTP_COLOUR_MAX);
574 /* The "Solid color" pattern is white by default */
575 }
576
577 if (ctrl_hdlr->error) {
578 ret = ctrl_hdlr->error;
579 dev_err_probe(&client->dev, ret, "Control init failed\n");
580 goto error;
581 }
582
583 ret = v4l2_fwnode_device_parse(&client->dev, &props);
584 if (ret)
585 goto error;
586
587 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops,
588 &props);
589 if (ret)
590 goto error;
591
592 imx219->sd.ctrl_handler = ctrl_hdlr;
593
594 return 0;
595
596 error:
597 v4l2_ctrl_handler_free(ctrl_hdlr);
598
599 return ret;
600 }
601
imx219_free_controls(struct imx219 * imx219)602 static void imx219_free_controls(struct imx219 *imx219)
603 {
604 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler);
605 }
606
607 /* -----------------------------------------------------------------------------
608 * Subdev operations
609 */
610
imx219_set_framefmt(struct imx219 * imx219,struct v4l2_subdev_state * state)611 static int imx219_set_framefmt(struct imx219 *imx219,
612 struct v4l2_subdev_state *state)
613 {
614 const struct v4l2_mbus_framefmt *format;
615 const struct v4l2_rect *crop;
616 unsigned int bpp;
617 u64 bin_h, bin_v;
618 int ret = 0;
619
620 format = v4l2_subdev_state_get_format(state, 0);
621 crop = v4l2_subdev_state_get_crop(state, 0);
622
623 switch (format->code) {
624 case MEDIA_BUS_FMT_SRGGB8_1X8:
625 case MEDIA_BUS_FMT_SGRBG8_1X8:
626 case MEDIA_BUS_FMT_SGBRG8_1X8:
627 case MEDIA_BUS_FMT_SBGGR8_1X8:
628 bpp = 8;
629 break;
630
631 case MEDIA_BUS_FMT_SRGGB10_1X10:
632 case MEDIA_BUS_FMT_SGRBG10_1X10:
633 case MEDIA_BUS_FMT_SGBRG10_1X10:
634 case MEDIA_BUS_FMT_SBGGR10_1X10:
635 default:
636 bpp = 10;
637 break;
638 }
639
640 cci_write(imx219->regmap, IMX219_REG_X_ADD_STA_A,
641 crop->left - IMX219_PIXEL_ARRAY_LEFT, &ret);
642 cci_write(imx219->regmap, IMX219_REG_X_ADD_END_A,
643 crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, &ret);
644 cci_write(imx219->regmap, IMX219_REG_Y_ADD_STA_A,
645 crop->top - IMX219_PIXEL_ARRAY_TOP, &ret);
646 cci_write(imx219->regmap, IMX219_REG_Y_ADD_END_A,
647 crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, &ret);
648
649 switch (crop->width / format->width) {
650 case 1:
651 default:
652 bin_h = IMX219_BINNING_NONE;
653 break;
654 case 2:
655 bin_h = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
656 break;
657 }
658
659 switch (crop->height / format->height) {
660 case 1:
661 default:
662 bin_v = IMX219_BINNING_NONE;
663 break;
664 case 2:
665 bin_v = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
666 break;
667 }
668
669 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_H, bin_h, &ret);
670 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_V, bin_v, &ret);
671
672 cci_write(imx219->regmap, IMX219_REG_X_OUTPUT_SIZE,
673 format->width, &ret);
674 cci_write(imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE,
675 format->height, &ret);
676
677 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH,
678 format->width, &ret);
679 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT,
680 format->height, &ret);
681
682 cci_write(imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A,
683 (bpp << 8) | bpp, &ret);
684 cci_write(imx219->regmap, IMX219_REG_OPPXCK_DIV, bpp, &ret);
685
686 return ret;
687 }
688
imx219_configure_lanes(struct imx219 * imx219)689 static int imx219_configure_lanes(struct imx219 *imx219)
690 {
691 /* Write the appropriate PLL settings for the number of MIPI lanes */
692 return cci_multi_reg_write(imx219->regmap,
693 imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs,
694 imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) :
695 ARRAY_SIZE(imx219_4lane_regs), NULL);
696 };
697
imx219_start_streaming(struct imx219 * imx219,struct v4l2_subdev_state * state)698 static int imx219_start_streaming(struct imx219 *imx219,
699 struct v4l2_subdev_state *state)
700 {
701 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
702 int ret;
703
704 ret = pm_runtime_resume_and_get(&client->dev);
705 if (ret < 0)
706 return ret;
707
708 /* Send all registers that are common to all modes */
709 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs,
710 ARRAY_SIZE(imx219_common_regs), NULL);
711 if (ret) {
712 dev_err(&client->dev, "%s failed to send mfg header\n", __func__);
713 goto err_rpm_put;
714 }
715
716 /* Configure two or four Lane mode */
717 ret = imx219_configure_lanes(imx219);
718 if (ret) {
719 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
720 goto err_rpm_put;
721 }
722
723 /* Apply format and crop settings. */
724 ret = imx219_set_framefmt(imx219, state);
725 if (ret) {
726 dev_err(&client->dev, "%s failed to set frame format: %d\n",
727 __func__, ret);
728 goto err_rpm_put;
729 }
730
731 /* Apply customized values from user */
732 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
733 if (ret)
734 goto err_rpm_put;
735
736 /* set stream on register */
737 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
738 IMX219_MODE_STREAMING, NULL);
739 if (ret)
740 goto err_rpm_put;
741
742 /* vflip and hflip cannot change during streaming */
743 __v4l2_ctrl_grab(imx219->vflip, true);
744 __v4l2_ctrl_grab(imx219->hflip, true);
745
746 return 0;
747
748 err_rpm_put:
749 pm_runtime_put(&client->dev);
750 return ret;
751 }
752
imx219_stop_streaming(struct imx219 * imx219)753 static void imx219_stop_streaming(struct imx219 *imx219)
754 {
755 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
756 int ret;
757
758 /* set stream off register */
759 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
760 IMX219_MODE_STANDBY, NULL);
761 if (ret)
762 dev_err(&client->dev, "%s failed to set stream\n", __func__);
763
764 __v4l2_ctrl_grab(imx219->vflip, false);
765 __v4l2_ctrl_grab(imx219->hflip, false);
766
767 pm_runtime_put(&client->dev);
768 }
769
imx219_set_stream(struct v4l2_subdev * sd,int enable)770 static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
771 {
772 struct imx219 *imx219 = to_imx219(sd);
773 struct v4l2_subdev_state *state;
774 int ret = 0;
775
776 state = v4l2_subdev_lock_and_get_active_state(sd);
777
778 if (enable)
779 ret = imx219_start_streaming(imx219, state);
780 else
781 imx219_stop_streaming(imx219);
782
783 v4l2_subdev_unlock_state(state);
784 return ret;
785 }
786
imx219_update_pad_format(struct imx219 * imx219,const struct imx219_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code)787 static void imx219_update_pad_format(struct imx219 *imx219,
788 const struct imx219_mode *mode,
789 struct v4l2_mbus_framefmt *fmt, u32 code)
790 {
791 /* Bayer order varies with flips */
792 fmt->code = imx219_get_format_code(imx219, code);
793 fmt->width = mode->width;
794 fmt->height = mode->height;
795 fmt->field = V4L2_FIELD_NONE;
796 fmt->colorspace = V4L2_COLORSPACE_RAW;
797 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
798 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
799 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
800 }
801
imx219_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_mbus_code_enum * code)802 static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
803 struct v4l2_subdev_state *state,
804 struct v4l2_subdev_mbus_code_enum *code)
805 {
806 struct imx219 *imx219 = to_imx219(sd);
807
808 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4))
809 return -EINVAL;
810
811 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]);
812
813 return 0;
814 }
815
imx219_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_frame_size_enum * fse)816 static int imx219_enum_frame_size(struct v4l2_subdev *sd,
817 struct v4l2_subdev_state *state,
818 struct v4l2_subdev_frame_size_enum *fse)
819 {
820 struct imx219 *imx219 = to_imx219(sd);
821 u32 code;
822
823 if (fse->index >= ARRAY_SIZE(supported_modes))
824 return -EINVAL;
825
826 code = imx219_get_format_code(imx219, fse->code);
827 if (fse->code != code)
828 return -EINVAL;
829
830 fse->min_width = supported_modes[fse->index].width;
831 fse->max_width = fse->min_width;
832 fse->min_height = supported_modes[fse->index].height;
833 fse->max_height = fse->min_height;
834
835 return 0;
836 }
837
imx219_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * fmt)838 static int imx219_set_pad_format(struct v4l2_subdev *sd,
839 struct v4l2_subdev_state *state,
840 struct v4l2_subdev_format *fmt)
841 {
842 struct imx219 *imx219 = to_imx219(sd);
843 const struct imx219_mode *mode;
844 struct v4l2_mbus_framefmt *format;
845 struct v4l2_rect *crop;
846 unsigned int bin_h, bin_v;
847
848 mode = v4l2_find_nearest_size(supported_modes,
849 ARRAY_SIZE(supported_modes),
850 width, height,
851 fmt->format.width, fmt->format.height);
852
853 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code);
854
855 format = v4l2_subdev_state_get_format(state, 0);
856 *format = fmt->format;
857
858 /*
859 * Use binning to maximize the crop rectangle size, and centre it in the
860 * sensor.
861 */
862 bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U);
863 bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U);
864
865 crop = v4l2_subdev_state_get_crop(state, 0);
866 crop->width = format->width * bin_h;
867 crop->height = format->height * bin_v;
868 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2;
869 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2;
870
871 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
872 int exposure_max;
873 int exposure_def;
874 int hblank;
875
876 /* Update limits and set FPS to default */
877 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
878 IMX219_VTS_MAX - mode->height, 1,
879 mode->vts_def - mode->height);
880 __v4l2_ctrl_s_ctrl(imx219->vblank,
881 mode->vts_def - mode->height);
882 /* Update max exposure while meeting expected vblanking */
883 exposure_max = mode->vts_def - 4;
884 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
885 exposure_max : IMX219_EXPOSURE_DEFAULT;
886 __v4l2_ctrl_modify_range(imx219->exposure,
887 imx219->exposure->minimum,
888 exposure_max, imx219->exposure->step,
889 exposure_def);
890 /*
891 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
892 * depends on mode->width only, and is not changeble in any
893 * way other than changing the mode.
894 */
895 hblank = IMX219_PPL_DEFAULT - mode->width;
896 __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
897 hblank);
898 }
899
900 return 0;
901 }
902
imx219_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_selection * sel)903 static int imx219_get_selection(struct v4l2_subdev *sd,
904 struct v4l2_subdev_state *state,
905 struct v4l2_subdev_selection *sel)
906 {
907 switch (sel->target) {
908 case V4L2_SEL_TGT_CROP: {
909 sel->r = *v4l2_subdev_state_get_crop(state, 0);
910 return 0;
911 }
912
913 case V4L2_SEL_TGT_NATIVE_SIZE:
914 sel->r.top = 0;
915 sel->r.left = 0;
916 sel->r.width = IMX219_NATIVE_WIDTH;
917 sel->r.height = IMX219_NATIVE_HEIGHT;
918
919 return 0;
920
921 case V4L2_SEL_TGT_CROP_DEFAULT:
922 case V4L2_SEL_TGT_CROP_BOUNDS:
923 sel->r.top = IMX219_PIXEL_ARRAY_TOP;
924 sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
925 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
926 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
927
928 return 0;
929 }
930
931 return -EINVAL;
932 }
933
imx219_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)934 static int imx219_init_state(struct v4l2_subdev *sd,
935 struct v4l2_subdev_state *state)
936 {
937 struct v4l2_subdev_format fmt = {
938 .which = V4L2_SUBDEV_FORMAT_TRY,
939 .pad = 0,
940 .format = {
941 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
942 .width = supported_modes[0].width,
943 .height = supported_modes[0].height,
944 },
945 };
946
947 imx219_set_pad_format(sd, state, &fmt);
948
949 return 0;
950 }
951
952 static const struct v4l2_subdev_core_ops imx219_core_ops = {
953 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
954 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
955 };
956
957 static const struct v4l2_subdev_video_ops imx219_video_ops = {
958 .s_stream = imx219_set_stream,
959 };
960
961 static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
962 .enum_mbus_code = imx219_enum_mbus_code,
963 .get_fmt = v4l2_subdev_get_fmt,
964 .set_fmt = imx219_set_pad_format,
965 .get_selection = imx219_get_selection,
966 .enum_frame_size = imx219_enum_frame_size,
967 };
968
969 static const struct v4l2_subdev_ops imx219_subdev_ops = {
970 .core = &imx219_core_ops,
971 .video = &imx219_video_ops,
972 .pad = &imx219_pad_ops,
973 };
974
975 static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
976 .init_state = imx219_init_state,
977 };
978
979 /* -----------------------------------------------------------------------------
980 * Power management
981 */
982
imx219_power_on(struct device * dev)983 static int imx219_power_on(struct device *dev)
984 {
985 struct v4l2_subdev *sd = dev_get_drvdata(dev);
986 struct imx219 *imx219 = to_imx219(sd);
987 int ret;
988
989 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
990 imx219->supplies);
991 if (ret) {
992 dev_err(dev, "%s: failed to enable regulators\n",
993 __func__);
994 return ret;
995 }
996
997 ret = clk_prepare_enable(imx219->xclk);
998 if (ret) {
999 dev_err(dev, "%s: failed to enable clock\n",
1000 __func__);
1001 goto reg_off;
1002 }
1003
1004 gpiod_set_value_cansleep(imx219->reset_gpio, 1);
1005 usleep_range(IMX219_XCLR_MIN_DELAY_US,
1006 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
1007
1008 return 0;
1009
1010 reg_off:
1011 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1012
1013 return ret;
1014 }
1015
imx219_power_off(struct device * dev)1016 static int imx219_power_off(struct device *dev)
1017 {
1018 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1019 struct imx219 *imx219 = to_imx219(sd);
1020
1021 gpiod_set_value_cansleep(imx219->reset_gpio, 0);
1022 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1023 clk_disable_unprepare(imx219->xclk);
1024
1025 return 0;
1026 }
1027
1028 /* -----------------------------------------------------------------------------
1029 * Probe & remove
1030 */
1031
imx219_get_regulators(struct imx219 * imx219)1032 static int imx219_get_regulators(struct imx219 *imx219)
1033 {
1034 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1035 unsigned int i;
1036
1037 for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1038 imx219->supplies[i].supply = imx219_supply_name[i];
1039
1040 return devm_regulator_bulk_get(&client->dev,
1041 IMX219_NUM_SUPPLIES,
1042 imx219->supplies);
1043 }
1044
1045 /* Verify chip ID */
imx219_identify_module(struct imx219 * imx219)1046 static int imx219_identify_module(struct imx219 *imx219)
1047 {
1048 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1049 int ret;
1050 u64 val;
1051
1052 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL);
1053 if (ret)
1054 return dev_err_probe(&client->dev, ret,
1055 "failed to read chip id %x\n",
1056 IMX219_CHIP_ID);
1057
1058 if (val != IMX219_CHIP_ID)
1059 return dev_err_probe(&client->dev, -EIO,
1060 "chip id mismatch: %x!=%llx\n",
1061 IMX219_CHIP_ID, val);
1062
1063 return 0;
1064 }
1065
imx219_check_hwcfg(struct device * dev,struct imx219 * imx219)1066 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
1067 {
1068 struct fwnode_handle *endpoint;
1069 struct v4l2_fwnode_endpoint ep_cfg = {
1070 .bus_type = V4L2_MBUS_CSI2_DPHY
1071 };
1072 unsigned long link_freq_bitmap;
1073 int ret = -EINVAL;
1074
1075 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1076 if (!endpoint)
1077 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
1078
1079 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {
1080 dev_err_probe(dev, -EINVAL, "could not parse endpoint\n");
1081 goto error_out;
1082 }
1083
1084 /* Check the number of MIPI CSI2 data lanes */
1085 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1086 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1087 dev_err_probe(dev, -EINVAL,
1088 "only 2 or 4 data lanes are currently supported\n");
1089 goto error_out;
1090 }
1091 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1092
1093 /* Check the link frequency set in device tree */
1094 switch (imx219->lanes) {
1095 case 2:
1096 ret = v4l2_link_freq_to_bitmap(dev,
1097 ep_cfg.link_frequencies,
1098 ep_cfg.nr_of_link_frequencies,
1099 imx219_link_freq_menu,
1100 ARRAY_SIZE(imx219_link_freq_menu),
1101 &link_freq_bitmap);
1102 break;
1103 case 4:
1104 ret = v4l2_link_freq_to_bitmap(dev,
1105 ep_cfg.link_frequencies,
1106 ep_cfg.nr_of_link_frequencies,
1107 imx219_link_freq_4lane_menu,
1108 ARRAY_SIZE(imx219_link_freq_4lane_menu),
1109 &link_freq_bitmap);
1110
1111 if (!ret && (link_freq_bitmap & BIT(1))) {
1112 dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n",
1113 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED);
1114 dev_warn(dev, "Using link frequency of %d\n",
1115 IMX219_DEFAULT_LINK_FREQ_4LANE);
1116 link_freq_bitmap |= BIT(0);
1117 }
1118 break;
1119 }
1120
1121 if (ret || !(link_freq_bitmap & BIT(0))) {
1122 ret = -EINVAL;
1123 dev_err_probe(dev, -EINVAL,
1124 "Link frequency not supported: %lld\n",
1125 ep_cfg.link_frequencies[0]);
1126 }
1127
1128 error_out:
1129 v4l2_fwnode_endpoint_free(&ep_cfg);
1130 fwnode_handle_put(endpoint);
1131
1132 return ret;
1133 }
1134
imx219_probe(struct i2c_client * client)1135 static int imx219_probe(struct i2c_client *client)
1136 {
1137 struct device *dev = &client->dev;
1138 struct imx219 *imx219;
1139 int ret;
1140
1141 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
1142 if (!imx219)
1143 return -ENOMEM;
1144
1145 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
1146 imx219->sd.internal_ops = &imx219_internal_ops;
1147
1148 /* Check the hardware configuration in device tree */
1149 if (imx219_check_hwcfg(dev, imx219))
1150 return -EINVAL;
1151
1152 imx219->regmap = devm_cci_regmap_init_i2c(client, 16);
1153 if (IS_ERR(imx219->regmap))
1154 return dev_err_probe(dev, PTR_ERR(imx219->regmap),
1155 "failed to initialize CCI\n");
1156
1157 /* Get system clock (xclk) */
1158 imx219->xclk = devm_clk_get(dev, NULL);
1159 if (IS_ERR(imx219->xclk))
1160 return dev_err_probe(dev, PTR_ERR(imx219->xclk),
1161 "failed to get xclk\n");
1162
1163 imx219->xclk_freq = clk_get_rate(imx219->xclk);
1164 if (imx219->xclk_freq != IMX219_XCLK_FREQ)
1165 return dev_err_probe(dev, -EINVAL,
1166 "xclk frequency not supported: %d Hz\n",
1167 imx219->xclk_freq);
1168
1169 ret = imx219_get_regulators(imx219);
1170 if (ret)
1171 return dev_err_probe(dev, ret, "failed to get regulators\n");
1172
1173 /* Request optional enable pin */
1174 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1175 GPIOD_OUT_HIGH);
1176
1177 /*
1178 * The sensor must be powered for imx219_identify_module()
1179 * to be able to read the CHIP_ID register
1180 */
1181 ret = imx219_power_on(dev);
1182 if (ret)
1183 return ret;
1184
1185 ret = imx219_identify_module(imx219);
1186 if (ret)
1187 goto error_power_off;
1188
1189 /*
1190 * Sensor doesn't enter LP-11 state upon power up until and unless
1191 * streaming is started, so upon power up switch the modes to:
1192 * streaming -> standby
1193 */
1194 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1195 IMX219_MODE_STREAMING, NULL);
1196 if (ret < 0)
1197 goto error_power_off;
1198
1199 usleep_range(100, 110);
1200
1201 /* put sensor back to standby mode */
1202 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1203 IMX219_MODE_STANDBY, NULL);
1204 if (ret < 0)
1205 goto error_power_off;
1206
1207 usleep_range(100, 110);
1208
1209 ret = imx219_init_controls(imx219);
1210 if (ret)
1211 goto error_power_off;
1212
1213 /* Initialize subdev */
1214 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1215 V4L2_SUBDEV_FL_HAS_EVENTS;
1216 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1217
1218 /* Initialize source pad */
1219 imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1220
1221 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
1222 if (ret) {
1223 dev_err_probe(dev, ret, "failed to init entity pads\n");
1224 goto error_handler_free;
1225 }
1226
1227 imx219->sd.state_lock = imx219->ctrl_handler.lock;
1228 ret = v4l2_subdev_init_finalize(&imx219->sd);
1229 if (ret < 0) {
1230 dev_err_probe(dev, ret, "subdev init error\n");
1231 goto error_media_entity;
1232 }
1233
1234 pm_runtime_set_active(dev);
1235 pm_runtime_enable(dev);
1236
1237 ret = v4l2_async_register_subdev_sensor(&imx219->sd);
1238 if (ret < 0) {
1239 dev_err_probe(dev, ret,
1240 "failed to register sensor sub-device\n");
1241 goto error_subdev_cleanup;
1242 }
1243
1244 pm_runtime_idle(dev);
1245
1246 return 0;
1247
1248 error_subdev_cleanup:
1249 v4l2_subdev_cleanup(&imx219->sd);
1250 pm_runtime_disable(dev);
1251 pm_runtime_set_suspended(dev);
1252
1253 error_media_entity:
1254 media_entity_cleanup(&imx219->sd.entity);
1255
1256 error_handler_free:
1257 imx219_free_controls(imx219);
1258
1259 error_power_off:
1260 imx219_power_off(dev);
1261
1262 return ret;
1263 }
1264
imx219_remove(struct i2c_client * client)1265 static void imx219_remove(struct i2c_client *client)
1266 {
1267 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1268 struct imx219 *imx219 = to_imx219(sd);
1269
1270 v4l2_async_unregister_subdev(sd);
1271 v4l2_subdev_cleanup(sd);
1272 media_entity_cleanup(&sd->entity);
1273 imx219_free_controls(imx219);
1274
1275 pm_runtime_disable(&client->dev);
1276 if (!pm_runtime_status_suspended(&client->dev)) {
1277 imx219_power_off(&client->dev);
1278 pm_runtime_set_suspended(&client->dev);
1279 }
1280 }
1281
1282 static const struct of_device_id imx219_dt_ids[] = {
1283 { .compatible = "sony,imx219" },
1284 { /* sentinel */ }
1285 };
1286 MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1287
1288 static const struct dev_pm_ops imx219_pm_ops = {
1289 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1290 };
1291
1292 static struct i2c_driver imx219_i2c_driver = {
1293 .driver = {
1294 .name = "imx219",
1295 .of_match_table = imx219_dt_ids,
1296 .pm = &imx219_pm_ops,
1297 },
1298 .probe = imx219_probe,
1299 .remove = imx219_remove,
1300 };
1301
1302 module_i2c_driver(imx219_i2c_driver);
1303
1304 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com");
1305 MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1306 MODULE_LICENSE("GPL v2");
1307