1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_idle.c - native hardware idle loop for modern Intel processors
4 *
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 */
9
10 /*
11 * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
15 */
16
17 /*
18 * Design Assumptions
19 *
20 * All CPUs have same idle states as boot CPU
21 *
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-states
24 *
25 * CPU will flush caches as needed when entering a C-state via MWAIT
26 * (in contrast to entering ACPI C3, in which case the WBINVD
27 * instruction needs to be executed to flush the caches)
28 */
29
30 /*
31 * Known limitations
32 *
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
34 * to avoid complications with the lapic timer workaround.
35 * Have not seen issues with suspend, but may need same workaround here.
36 *
37 */
38
39 /* un-comment DEBUG to enable pr_debug() statements */
40 /* #define DEBUG */
41
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44 #include <linux/acpi.h>
45 #include <linux/kernel.h>
46 #include <linux/cpuidle.h>
47 #include <linux/tick.h>
48 #include <trace/events/power.h>
49 #include <linux/sched.h>
50 #include <linux/sched/smt.h>
51 #include <linux/notifier.h>
52 #include <linux/cpu.h>
53 #include <linux/moduleparam.h>
54 #include <asm/cpu_device_id.h>
55 #include <asm/intel-family.h>
56 #include <asm/mwait.h>
57 #include <asm/spec-ctrl.h>
58 #include <asm/tsc.h>
59 #include <asm/fpu/api.h>
60
61 #define INTEL_IDLE_VERSION "0.5.1"
62
63 static struct cpuidle_driver intel_idle_driver = {
64 .name = "intel_idle",
65 .owner = THIS_MODULE,
66 };
67 /* intel_idle.max_cstate=0 disables driver */
68 static int max_cstate = CPUIDLE_STATE_MAX - 1;
69 static unsigned int disabled_states_mask __read_mostly;
70 static unsigned int preferred_states_mask __read_mostly;
71 static bool force_irq_on __read_mostly;
72 static bool ibrs_off __read_mostly;
73
74 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
75
76 static unsigned long auto_demotion_disable_flags;
77
78 static enum {
79 C1E_PROMOTION_PRESERVE,
80 C1E_PROMOTION_ENABLE,
81 C1E_PROMOTION_DISABLE
82 } c1e_promotion = C1E_PROMOTION_PRESERVE;
83
84 struct idle_cpu {
85 struct cpuidle_state *state_table;
86
87 /*
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
90 */
91 unsigned long auto_demotion_disable_flags;
92 bool byt_auto_demotion_disable_flag;
93 bool disable_promotion_to_c1e;
94 bool use_acpi;
95 };
96
97 static const struct idle_cpu *icpu __initdata;
98 static struct cpuidle_state *cpuidle_state_table __initdata;
99
100 static unsigned int mwait_substates __initdata;
101
102 /*
103 * Enable interrupts before entering the C-state. On some platforms and for
104 * some C-states, this may measurably decrease interrupt latency.
105 */
106 #define CPUIDLE_FLAG_IRQ_ENABLE BIT(14)
107
108 /*
109 * Enable this state by default even if the ACPI _CST does not list it.
110 */
111 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
112
113 /*
114 * Disable IBRS across idle (when KERNEL_IBRS), is exclusive vs IRQ_ENABLE
115 * above.
116 */
117 #define CPUIDLE_FLAG_IBRS BIT(16)
118
119 /*
120 * Initialize large xstate for the C6-state entrance.
121 */
122 #define CPUIDLE_FLAG_INIT_XSTATE BIT(17)
123
124 /*
125 * Ignore the sub-state when matching mwait hints between the ACPI _CST and
126 * custom tables.
127 */
128 #define CPUIDLE_FLAG_PARTIAL_HINT_MATCH BIT(18)
129
130 /*
131 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
132 * the C-state (top nibble) and sub-state (bottom nibble)
133 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
134 *
135 * We store the hint at the top of our "flags" for each state.
136 */
137 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
138 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
139
__intel_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index,bool irqoff)140 static __always_inline int __intel_idle(struct cpuidle_device *dev,
141 struct cpuidle_driver *drv,
142 int index, bool irqoff)
143 {
144 struct cpuidle_state *state = &drv->states[index];
145 unsigned long eax = flg2MWAIT(state->flags);
146 unsigned long ecx = 1*irqoff; /* break on interrupt flag */
147
148 mwait_idle_with_hints(eax, ecx);
149
150 return index;
151 }
152
153 /**
154 * intel_idle - Ask the processor to enter the given idle state.
155 * @dev: cpuidle device of the target CPU.
156 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
157 * @index: Target idle state index.
158 *
159 * Use the MWAIT instruction to notify the processor that the CPU represented by
160 * @dev is idle and it can try to enter the idle state corresponding to @index.
161 *
162 * If the local APIC timer is not known to be reliable in the target idle state,
163 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
164 *
165 * Must be called under local_irq_disable().
166 */
intel_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)167 static __cpuidle int intel_idle(struct cpuidle_device *dev,
168 struct cpuidle_driver *drv, int index)
169 {
170 return __intel_idle(dev, drv, index, true);
171 }
172
intel_idle_irq(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)173 static __cpuidle int intel_idle_irq(struct cpuidle_device *dev,
174 struct cpuidle_driver *drv, int index)
175 {
176 return __intel_idle(dev, drv, index, false);
177 }
178
intel_idle_ibrs(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)179 static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
180 struct cpuidle_driver *drv, int index)
181 {
182 bool smt_active = sched_smt_active();
183 u64 spec_ctrl = spec_ctrl_current();
184 int ret;
185
186 if (smt_active)
187 __update_spec_ctrl(0);
188
189 ret = __intel_idle(dev, drv, index, true);
190
191 if (smt_active)
192 __update_spec_ctrl(spec_ctrl);
193
194 return ret;
195 }
196
intel_idle_xstate(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)197 static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,
198 struct cpuidle_driver *drv, int index)
199 {
200 fpu_idle_fpregs();
201 return __intel_idle(dev, drv, index, true);
202 }
203
204 /**
205 * intel_idle_s2idle - Ask the processor to enter the given idle state.
206 * @dev: cpuidle device of the target CPU.
207 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
208 * @index: Target idle state index.
209 *
210 * Use the MWAIT instruction to notify the processor that the CPU represented by
211 * @dev is idle and it can try to enter the idle state corresponding to @index.
212 *
213 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
214 * scheduler tick and suspended scheduler clock on the target CPU.
215 */
intel_idle_s2idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)216 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
217 struct cpuidle_driver *drv, int index)
218 {
219 unsigned long ecx = 1; /* break on interrupt flag */
220 struct cpuidle_state *state = &drv->states[index];
221 unsigned long eax = flg2MWAIT(state->flags);
222
223 if (state->flags & CPUIDLE_FLAG_INIT_XSTATE)
224 fpu_idle_fpregs();
225
226 mwait_idle_with_hints(eax, ecx);
227
228 return 0;
229 }
230
231 /*
232 * States are indexed by the cstate number,
233 * which is also the index into the MWAIT hint array.
234 * Thus C0 is a dummy.
235 */
236 static struct cpuidle_state nehalem_cstates[] __initdata = {
237 {
238 .name = "C1",
239 .desc = "MWAIT 0x00",
240 .flags = MWAIT2flg(0x00),
241 .exit_latency = 3,
242 .target_residency = 6,
243 .enter = &intel_idle,
244 .enter_s2idle = intel_idle_s2idle, },
245 {
246 .name = "C1E",
247 .desc = "MWAIT 0x01",
248 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
249 .exit_latency = 10,
250 .target_residency = 20,
251 .enter = &intel_idle,
252 .enter_s2idle = intel_idle_s2idle, },
253 {
254 .name = "C3",
255 .desc = "MWAIT 0x10",
256 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
257 .exit_latency = 20,
258 .target_residency = 80,
259 .enter = &intel_idle,
260 .enter_s2idle = intel_idle_s2idle, },
261 {
262 .name = "C6",
263 .desc = "MWAIT 0x20",
264 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
265 .exit_latency = 200,
266 .target_residency = 800,
267 .enter = &intel_idle,
268 .enter_s2idle = intel_idle_s2idle, },
269 {
270 .enter = NULL }
271 };
272
273 static struct cpuidle_state snb_cstates[] __initdata = {
274 {
275 .name = "C1",
276 .desc = "MWAIT 0x00",
277 .flags = MWAIT2flg(0x00),
278 .exit_latency = 2,
279 .target_residency = 2,
280 .enter = &intel_idle,
281 .enter_s2idle = intel_idle_s2idle, },
282 {
283 .name = "C1E",
284 .desc = "MWAIT 0x01",
285 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
286 .exit_latency = 10,
287 .target_residency = 20,
288 .enter = &intel_idle,
289 .enter_s2idle = intel_idle_s2idle, },
290 {
291 .name = "C3",
292 .desc = "MWAIT 0x10",
293 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
294 .exit_latency = 80,
295 .target_residency = 211,
296 .enter = &intel_idle,
297 .enter_s2idle = intel_idle_s2idle, },
298 {
299 .name = "C6",
300 .desc = "MWAIT 0x20",
301 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
302 .exit_latency = 104,
303 .target_residency = 345,
304 .enter = &intel_idle,
305 .enter_s2idle = intel_idle_s2idle, },
306 {
307 .name = "C7",
308 .desc = "MWAIT 0x30",
309 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
310 .exit_latency = 109,
311 .target_residency = 345,
312 .enter = &intel_idle,
313 .enter_s2idle = intel_idle_s2idle, },
314 {
315 .enter = NULL }
316 };
317
318 static struct cpuidle_state byt_cstates[] __initdata = {
319 {
320 .name = "C1",
321 .desc = "MWAIT 0x00",
322 .flags = MWAIT2flg(0x00),
323 .exit_latency = 1,
324 .target_residency = 1,
325 .enter = &intel_idle,
326 .enter_s2idle = intel_idle_s2idle, },
327 {
328 .name = "C6N",
329 .desc = "MWAIT 0x58",
330 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
331 .exit_latency = 300,
332 .target_residency = 275,
333 .enter = &intel_idle,
334 .enter_s2idle = intel_idle_s2idle, },
335 {
336 .name = "C6S",
337 .desc = "MWAIT 0x52",
338 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
339 .exit_latency = 500,
340 .target_residency = 560,
341 .enter = &intel_idle,
342 .enter_s2idle = intel_idle_s2idle, },
343 {
344 .name = "C7",
345 .desc = "MWAIT 0x60",
346 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
347 .exit_latency = 1200,
348 .target_residency = 4000,
349 .enter = &intel_idle,
350 .enter_s2idle = intel_idle_s2idle, },
351 {
352 .name = "C7S",
353 .desc = "MWAIT 0x64",
354 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
355 .exit_latency = 10000,
356 .target_residency = 20000,
357 .enter = &intel_idle,
358 .enter_s2idle = intel_idle_s2idle, },
359 {
360 .enter = NULL }
361 };
362
363 static struct cpuidle_state cht_cstates[] __initdata = {
364 {
365 .name = "C1",
366 .desc = "MWAIT 0x00",
367 .flags = MWAIT2flg(0x00),
368 .exit_latency = 1,
369 .target_residency = 1,
370 .enter = &intel_idle,
371 .enter_s2idle = intel_idle_s2idle, },
372 {
373 .name = "C6N",
374 .desc = "MWAIT 0x58",
375 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
376 .exit_latency = 80,
377 .target_residency = 275,
378 .enter = &intel_idle,
379 .enter_s2idle = intel_idle_s2idle, },
380 {
381 .name = "C6S",
382 .desc = "MWAIT 0x52",
383 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
384 .exit_latency = 200,
385 .target_residency = 560,
386 .enter = &intel_idle,
387 .enter_s2idle = intel_idle_s2idle, },
388 {
389 .name = "C7",
390 .desc = "MWAIT 0x60",
391 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
392 .exit_latency = 1200,
393 .target_residency = 4000,
394 .enter = &intel_idle,
395 .enter_s2idle = intel_idle_s2idle, },
396 {
397 .name = "C7S",
398 .desc = "MWAIT 0x64",
399 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
400 .exit_latency = 10000,
401 .target_residency = 20000,
402 .enter = &intel_idle,
403 .enter_s2idle = intel_idle_s2idle, },
404 {
405 .enter = NULL }
406 };
407
408 static struct cpuidle_state ivb_cstates[] __initdata = {
409 {
410 .name = "C1",
411 .desc = "MWAIT 0x00",
412 .flags = MWAIT2flg(0x00),
413 .exit_latency = 1,
414 .target_residency = 1,
415 .enter = &intel_idle,
416 .enter_s2idle = intel_idle_s2idle, },
417 {
418 .name = "C1E",
419 .desc = "MWAIT 0x01",
420 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
421 .exit_latency = 10,
422 .target_residency = 20,
423 .enter = &intel_idle,
424 .enter_s2idle = intel_idle_s2idle, },
425 {
426 .name = "C3",
427 .desc = "MWAIT 0x10",
428 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
429 .exit_latency = 59,
430 .target_residency = 156,
431 .enter = &intel_idle,
432 .enter_s2idle = intel_idle_s2idle, },
433 {
434 .name = "C6",
435 .desc = "MWAIT 0x20",
436 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
437 .exit_latency = 80,
438 .target_residency = 300,
439 .enter = &intel_idle,
440 .enter_s2idle = intel_idle_s2idle, },
441 {
442 .name = "C7",
443 .desc = "MWAIT 0x30",
444 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
445 .exit_latency = 87,
446 .target_residency = 300,
447 .enter = &intel_idle,
448 .enter_s2idle = intel_idle_s2idle, },
449 {
450 .enter = NULL }
451 };
452
453 static struct cpuidle_state ivt_cstates[] __initdata = {
454 {
455 .name = "C1",
456 .desc = "MWAIT 0x00",
457 .flags = MWAIT2flg(0x00),
458 .exit_latency = 1,
459 .target_residency = 1,
460 .enter = &intel_idle,
461 .enter_s2idle = intel_idle_s2idle, },
462 {
463 .name = "C1E",
464 .desc = "MWAIT 0x01",
465 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
466 .exit_latency = 10,
467 .target_residency = 80,
468 .enter = &intel_idle,
469 .enter_s2idle = intel_idle_s2idle, },
470 {
471 .name = "C3",
472 .desc = "MWAIT 0x10",
473 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
474 .exit_latency = 59,
475 .target_residency = 156,
476 .enter = &intel_idle,
477 .enter_s2idle = intel_idle_s2idle, },
478 {
479 .name = "C6",
480 .desc = "MWAIT 0x20",
481 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
482 .exit_latency = 82,
483 .target_residency = 300,
484 .enter = &intel_idle,
485 .enter_s2idle = intel_idle_s2idle, },
486 {
487 .enter = NULL }
488 };
489
490 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
491 {
492 .name = "C1",
493 .desc = "MWAIT 0x00",
494 .flags = MWAIT2flg(0x00),
495 .exit_latency = 1,
496 .target_residency = 1,
497 .enter = &intel_idle,
498 .enter_s2idle = intel_idle_s2idle, },
499 {
500 .name = "C1E",
501 .desc = "MWAIT 0x01",
502 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
503 .exit_latency = 10,
504 .target_residency = 250,
505 .enter = &intel_idle,
506 .enter_s2idle = intel_idle_s2idle, },
507 {
508 .name = "C3",
509 .desc = "MWAIT 0x10",
510 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
511 .exit_latency = 59,
512 .target_residency = 300,
513 .enter = &intel_idle,
514 .enter_s2idle = intel_idle_s2idle, },
515 {
516 .name = "C6",
517 .desc = "MWAIT 0x20",
518 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
519 .exit_latency = 84,
520 .target_residency = 400,
521 .enter = &intel_idle,
522 .enter_s2idle = intel_idle_s2idle, },
523 {
524 .enter = NULL }
525 };
526
527 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
528 {
529 .name = "C1",
530 .desc = "MWAIT 0x00",
531 .flags = MWAIT2flg(0x00),
532 .exit_latency = 1,
533 .target_residency = 1,
534 .enter = &intel_idle,
535 .enter_s2idle = intel_idle_s2idle, },
536 {
537 .name = "C1E",
538 .desc = "MWAIT 0x01",
539 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
540 .exit_latency = 10,
541 .target_residency = 500,
542 .enter = &intel_idle,
543 .enter_s2idle = intel_idle_s2idle, },
544 {
545 .name = "C3",
546 .desc = "MWAIT 0x10",
547 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
548 .exit_latency = 59,
549 .target_residency = 600,
550 .enter = &intel_idle,
551 .enter_s2idle = intel_idle_s2idle, },
552 {
553 .name = "C6",
554 .desc = "MWAIT 0x20",
555 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
556 .exit_latency = 88,
557 .target_residency = 700,
558 .enter = &intel_idle,
559 .enter_s2idle = intel_idle_s2idle, },
560 {
561 .enter = NULL }
562 };
563
564 static struct cpuidle_state hsw_cstates[] __initdata = {
565 {
566 .name = "C1",
567 .desc = "MWAIT 0x00",
568 .flags = MWAIT2flg(0x00),
569 .exit_latency = 2,
570 .target_residency = 2,
571 .enter = &intel_idle,
572 .enter_s2idle = intel_idle_s2idle, },
573 {
574 .name = "C1E",
575 .desc = "MWAIT 0x01",
576 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
577 .exit_latency = 10,
578 .target_residency = 20,
579 .enter = &intel_idle,
580 .enter_s2idle = intel_idle_s2idle, },
581 {
582 .name = "C3",
583 .desc = "MWAIT 0x10",
584 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
585 .exit_latency = 33,
586 .target_residency = 100,
587 .enter = &intel_idle,
588 .enter_s2idle = intel_idle_s2idle, },
589 {
590 .name = "C6",
591 .desc = "MWAIT 0x20",
592 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
593 .exit_latency = 133,
594 .target_residency = 400,
595 .enter = &intel_idle,
596 .enter_s2idle = intel_idle_s2idle, },
597 {
598 .name = "C7s",
599 .desc = "MWAIT 0x32",
600 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
601 .exit_latency = 166,
602 .target_residency = 500,
603 .enter = &intel_idle,
604 .enter_s2idle = intel_idle_s2idle, },
605 {
606 .name = "C8",
607 .desc = "MWAIT 0x40",
608 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
609 .exit_latency = 300,
610 .target_residency = 900,
611 .enter = &intel_idle,
612 .enter_s2idle = intel_idle_s2idle, },
613 {
614 .name = "C9",
615 .desc = "MWAIT 0x50",
616 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
617 .exit_latency = 600,
618 .target_residency = 1800,
619 .enter = &intel_idle,
620 .enter_s2idle = intel_idle_s2idle, },
621 {
622 .name = "C10",
623 .desc = "MWAIT 0x60",
624 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
625 .exit_latency = 2600,
626 .target_residency = 7700,
627 .enter = &intel_idle,
628 .enter_s2idle = intel_idle_s2idle, },
629 {
630 .enter = NULL }
631 };
632 static struct cpuidle_state bdw_cstates[] __initdata = {
633 {
634 .name = "C1",
635 .desc = "MWAIT 0x00",
636 .flags = MWAIT2flg(0x00),
637 .exit_latency = 2,
638 .target_residency = 2,
639 .enter = &intel_idle,
640 .enter_s2idle = intel_idle_s2idle, },
641 {
642 .name = "C1E",
643 .desc = "MWAIT 0x01",
644 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
645 .exit_latency = 10,
646 .target_residency = 20,
647 .enter = &intel_idle,
648 .enter_s2idle = intel_idle_s2idle, },
649 {
650 .name = "C3",
651 .desc = "MWAIT 0x10",
652 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
653 .exit_latency = 40,
654 .target_residency = 100,
655 .enter = &intel_idle,
656 .enter_s2idle = intel_idle_s2idle, },
657 {
658 .name = "C6",
659 .desc = "MWAIT 0x20",
660 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
661 .exit_latency = 133,
662 .target_residency = 400,
663 .enter = &intel_idle,
664 .enter_s2idle = intel_idle_s2idle, },
665 {
666 .name = "C7s",
667 .desc = "MWAIT 0x32",
668 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
669 .exit_latency = 166,
670 .target_residency = 500,
671 .enter = &intel_idle,
672 .enter_s2idle = intel_idle_s2idle, },
673 {
674 .name = "C8",
675 .desc = "MWAIT 0x40",
676 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
677 .exit_latency = 300,
678 .target_residency = 900,
679 .enter = &intel_idle,
680 .enter_s2idle = intel_idle_s2idle, },
681 {
682 .name = "C9",
683 .desc = "MWAIT 0x50",
684 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
685 .exit_latency = 600,
686 .target_residency = 1800,
687 .enter = &intel_idle,
688 .enter_s2idle = intel_idle_s2idle, },
689 {
690 .name = "C10",
691 .desc = "MWAIT 0x60",
692 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
693 .exit_latency = 2600,
694 .target_residency = 7700,
695 .enter = &intel_idle,
696 .enter_s2idle = intel_idle_s2idle, },
697 {
698 .enter = NULL }
699 };
700
701 static struct cpuidle_state skl_cstates[] __initdata = {
702 {
703 .name = "C1",
704 .desc = "MWAIT 0x00",
705 .flags = MWAIT2flg(0x00),
706 .exit_latency = 2,
707 .target_residency = 2,
708 .enter = &intel_idle,
709 .enter_s2idle = intel_idle_s2idle, },
710 {
711 .name = "C1E",
712 .desc = "MWAIT 0x01",
713 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
714 .exit_latency = 10,
715 .target_residency = 20,
716 .enter = &intel_idle,
717 .enter_s2idle = intel_idle_s2idle, },
718 {
719 .name = "C3",
720 .desc = "MWAIT 0x10",
721 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
722 .exit_latency = 70,
723 .target_residency = 100,
724 .enter = &intel_idle,
725 .enter_s2idle = intel_idle_s2idle, },
726 {
727 .name = "C6",
728 .desc = "MWAIT 0x20",
729 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
730 .exit_latency = 85,
731 .target_residency = 200,
732 .enter = &intel_idle,
733 .enter_s2idle = intel_idle_s2idle, },
734 {
735 .name = "C7s",
736 .desc = "MWAIT 0x33",
737 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
738 .exit_latency = 124,
739 .target_residency = 800,
740 .enter = &intel_idle,
741 .enter_s2idle = intel_idle_s2idle, },
742 {
743 .name = "C8",
744 .desc = "MWAIT 0x40",
745 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
746 .exit_latency = 200,
747 .target_residency = 800,
748 .enter = &intel_idle,
749 .enter_s2idle = intel_idle_s2idle, },
750 {
751 .name = "C9",
752 .desc = "MWAIT 0x50",
753 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
754 .exit_latency = 480,
755 .target_residency = 5000,
756 .enter = &intel_idle,
757 .enter_s2idle = intel_idle_s2idle, },
758 {
759 .name = "C10",
760 .desc = "MWAIT 0x60",
761 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
762 .exit_latency = 890,
763 .target_residency = 5000,
764 .enter = &intel_idle,
765 .enter_s2idle = intel_idle_s2idle, },
766 {
767 .enter = NULL }
768 };
769
770 static struct cpuidle_state skx_cstates[] __initdata = {
771 {
772 .name = "C1",
773 .desc = "MWAIT 0x00",
774 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
775 .exit_latency = 2,
776 .target_residency = 2,
777 .enter = &intel_idle,
778 .enter_s2idle = intel_idle_s2idle, },
779 {
780 .name = "C1E",
781 .desc = "MWAIT 0x01",
782 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
783 .exit_latency = 10,
784 .target_residency = 20,
785 .enter = &intel_idle,
786 .enter_s2idle = intel_idle_s2idle, },
787 {
788 .name = "C6",
789 .desc = "MWAIT 0x20",
790 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS,
791 .exit_latency = 133,
792 .target_residency = 600,
793 .enter = &intel_idle,
794 .enter_s2idle = intel_idle_s2idle, },
795 {
796 .enter = NULL }
797 };
798
799 static struct cpuidle_state icx_cstates[] __initdata = {
800 {
801 .name = "C1",
802 .desc = "MWAIT 0x00",
803 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
804 .exit_latency = 1,
805 .target_residency = 1,
806 .enter = &intel_idle,
807 .enter_s2idle = intel_idle_s2idle, },
808 {
809 .name = "C1E",
810 .desc = "MWAIT 0x01",
811 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
812 .exit_latency = 4,
813 .target_residency = 4,
814 .enter = &intel_idle,
815 .enter_s2idle = intel_idle_s2idle, },
816 {
817 .name = "C6",
818 .desc = "MWAIT 0x20",
819 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
820 .exit_latency = 170,
821 .target_residency = 600,
822 .enter = &intel_idle,
823 .enter_s2idle = intel_idle_s2idle, },
824 {
825 .enter = NULL }
826 };
827
828 /*
829 * On AlderLake C1 has to be disabled if C1E is enabled, and vice versa.
830 * C1E is enabled only if "C1E promotion" bit is set in MSR_IA32_POWER_CTL.
831 * But in this case there is effectively no C1, because C1 requests are
832 * promoted to C1E. If the "C1E promotion" bit is cleared, then both C1
833 * and C1E requests end up with C1, so there is effectively no C1E.
834 *
835 * By default we enable C1E and disable C1 by marking it with
836 * 'CPUIDLE_FLAG_UNUSABLE'.
837 */
838 static struct cpuidle_state adl_cstates[] __initdata = {
839 {
840 .name = "C1",
841 .desc = "MWAIT 0x00",
842 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
843 .exit_latency = 1,
844 .target_residency = 1,
845 .enter = &intel_idle,
846 .enter_s2idle = intel_idle_s2idle, },
847 {
848 .name = "C1E",
849 .desc = "MWAIT 0x01",
850 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
851 .exit_latency = 2,
852 .target_residency = 4,
853 .enter = &intel_idle,
854 .enter_s2idle = intel_idle_s2idle, },
855 {
856 .name = "C6",
857 .desc = "MWAIT 0x20",
858 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
859 .exit_latency = 220,
860 .target_residency = 600,
861 .enter = &intel_idle,
862 .enter_s2idle = intel_idle_s2idle, },
863 {
864 .name = "C8",
865 .desc = "MWAIT 0x40",
866 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
867 .exit_latency = 280,
868 .target_residency = 800,
869 .enter = &intel_idle,
870 .enter_s2idle = intel_idle_s2idle, },
871 {
872 .name = "C10",
873 .desc = "MWAIT 0x60",
874 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
875 .exit_latency = 680,
876 .target_residency = 2000,
877 .enter = &intel_idle,
878 .enter_s2idle = intel_idle_s2idle, },
879 {
880 .enter = NULL }
881 };
882
883 static struct cpuidle_state adl_l_cstates[] __initdata = {
884 {
885 .name = "C1",
886 .desc = "MWAIT 0x00",
887 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
888 .exit_latency = 1,
889 .target_residency = 1,
890 .enter = &intel_idle,
891 .enter_s2idle = intel_idle_s2idle, },
892 {
893 .name = "C1E",
894 .desc = "MWAIT 0x01",
895 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
896 .exit_latency = 2,
897 .target_residency = 4,
898 .enter = &intel_idle,
899 .enter_s2idle = intel_idle_s2idle, },
900 {
901 .name = "C6",
902 .desc = "MWAIT 0x20",
903 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
904 .exit_latency = 170,
905 .target_residency = 500,
906 .enter = &intel_idle,
907 .enter_s2idle = intel_idle_s2idle, },
908 {
909 .name = "C8",
910 .desc = "MWAIT 0x40",
911 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
912 .exit_latency = 200,
913 .target_residency = 600,
914 .enter = &intel_idle,
915 .enter_s2idle = intel_idle_s2idle, },
916 {
917 .name = "C10",
918 .desc = "MWAIT 0x60",
919 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
920 .exit_latency = 230,
921 .target_residency = 700,
922 .enter = &intel_idle,
923 .enter_s2idle = intel_idle_s2idle, },
924 {
925 .enter = NULL }
926 };
927
928 static struct cpuidle_state mtl_l_cstates[] __initdata = {
929 {
930 .name = "C1E",
931 .desc = "MWAIT 0x01",
932 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
933 .exit_latency = 1,
934 .target_residency = 1,
935 .enter = &intel_idle,
936 .enter_s2idle = intel_idle_s2idle, },
937 {
938 .name = "C6",
939 .desc = "MWAIT 0x20",
940 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
941 .exit_latency = 140,
942 .target_residency = 420,
943 .enter = &intel_idle,
944 .enter_s2idle = intel_idle_s2idle, },
945 {
946 .name = "C10",
947 .desc = "MWAIT 0x60",
948 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
949 .exit_latency = 310,
950 .target_residency = 930,
951 .enter = &intel_idle,
952 .enter_s2idle = intel_idle_s2idle, },
953 {
954 .enter = NULL }
955 };
956
957 static struct cpuidle_state gmt_cstates[] __initdata = {
958 {
959 .name = "C1",
960 .desc = "MWAIT 0x00",
961 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
962 .exit_latency = 1,
963 .target_residency = 1,
964 .enter = &intel_idle,
965 .enter_s2idle = intel_idle_s2idle, },
966 {
967 .name = "C1E",
968 .desc = "MWAIT 0x01",
969 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
970 .exit_latency = 2,
971 .target_residency = 4,
972 .enter = &intel_idle,
973 .enter_s2idle = intel_idle_s2idle, },
974 {
975 .name = "C6",
976 .desc = "MWAIT 0x20",
977 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
978 .exit_latency = 195,
979 .target_residency = 585,
980 .enter = &intel_idle,
981 .enter_s2idle = intel_idle_s2idle, },
982 {
983 .name = "C8",
984 .desc = "MWAIT 0x40",
985 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
986 .exit_latency = 260,
987 .target_residency = 1040,
988 .enter = &intel_idle,
989 .enter_s2idle = intel_idle_s2idle, },
990 {
991 .name = "C10",
992 .desc = "MWAIT 0x60",
993 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
994 .exit_latency = 660,
995 .target_residency = 1980,
996 .enter = &intel_idle,
997 .enter_s2idle = intel_idle_s2idle, },
998 {
999 .enter = NULL }
1000 };
1001
1002 static struct cpuidle_state spr_cstates[] __initdata = {
1003 {
1004 .name = "C1",
1005 .desc = "MWAIT 0x00",
1006 .flags = MWAIT2flg(0x00),
1007 .exit_latency = 1,
1008 .target_residency = 1,
1009 .enter = &intel_idle,
1010 .enter_s2idle = intel_idle_s2idle, },
1011 {
1012 .name = "C1E",
1013 .desc = "MWAIT 0x01",
1014 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1015 .exit_latency = 2,
1016 .target_residency = 4,
1017 .enter = &intel_idle,
1018 .enter_s2idle = intel_idle_s2idle, },
1019 {
1020 .name = "C6",
1021 .desc = "MWAIT 0x20",
1022 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |
1023 CPUIDLE_FLAG_INIT_XSTATE,
1024 .exit_latency = 290,
1025 .target_residency = 800,
1026 .enter = &intel_idle,
1027 .enter_s2idle = intel_idle_s2idle, },
1028 {
1029 .enter = NULL }
1030 };
1031
1032 static struct cpuidle_state gnr_cstates[] __initdata = {
1033 {
1034 .name = "C1",
1035 .desc = "MWAIT 0x00",
1036 .flags = MWAIT2flg(0x00),
1037 .exit_latency = 1,
1038 .target_residency = 1,
1039 .enter = &intel_idle,
1040 .enter_s2idle = intel_idle_s2idle, },
1041 {
1042 .name = "C1E",
1043 .desc = "MWAIT 0x01",
1044 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1045 .exit_latency = 4,
1046 .target_residency = 4,
1047 .enter = &intel_idle,
1048 .enter_s2idle = intel_idle_s2idle, },
1049 {
1050 .name = "C6",
1051 .desc = "MWAIT 0x20",
1052 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |
1053 CPUIDLE_FLAG_INIT_XSTATE |
1054 CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
1055 .exit_latency = 170,
1056 .target_residency = 650,
1057 .enter = &intel_idle,
1058 .enter_s2idle = intel_idle_s2idle, },
1059 {
1060 .name = "C6P",
1061 .desc = "MWAIT 0x21",
1062 .flags = MWAIT2flg(0x21) | CPUIDLE_FLAG_TLB_FLUSHED |
1063 CPUIDLE_FLAG_INIT_XSTATE |
1064 CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
1065 .exit_latency = 210,
1066 .target_residency = 1000,
1067 .enter = &intel_idle,
1068 .enter_s2idle = intel_idle_s2idle, },
1069 {
1070 .enter = NULL }
1071 };
1072
1073 static struct cpuidle_state atom_cstates[] __initdata = {
1074 {
1075 .name = "C1E",
1076 .desc = "MWAIT 0x00",
1077 .flags = MWAIT2flg(0x00),
1078 .exit_latency = 10,
1079 .target_residency = 20,
1080 .enter = &intel_idle,
1081 .enter_s2idle = intel_idle_s2idle, },
1082 {
1083 .name = "C2",
1084 .desc = "MWAIT 0x10",
1085 .flags = MWAIT2flg(0x10),
1086 .exit_latency = 20,
1087 .target_residency = 80,
1088 .enter = &intel_idle,
1089 .enter_s2idle = intel_idle_s2idle, },
1090 {
1091 .name = "C4",
1092 .desc = "MWAIT 0x30",
1093 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
1094 .exit_latency = 100,
1095 .target_residency = 400,
1096 .enter = &intel_idle,
1097 .enter_s2idle = intel_idle_s2idle, },
1098 {
1099 .name = "C6",
1100 .desc = "MWAIT 0x52",
1101 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
1102 .exit_latency = 140,
1103 .target_residency = 560,
1104 .enter = &intel_idle,
1105 .enter_s2idle = intel_idle_s2idle, },
1106 {
1107 .enter = NULL }
1108 };
1109 static struct cpuidle_state tangier_cstates[] __initdata = {
1110 {
1111 .name = "C1",
1112 .desc = "MWAIT 0x00",
1113 .flags = MWAIT2flg(0x00),
1114 .exit_latency = 1,
1115 .target_residency = 4,
1116 .enter = &intel_idle,
1117 .enter_s2idle = intel_idle_s2idle, },
1118 {
1119 .name = "C4",
1120 .desc = "MWAIT 0x30",
1121 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
1122 .exit_latency = 100,
1123 .target_residency = 400,
1124 .enter = &intel_idle,
1125 .enter_s2idle = intel_idle_s2idle, },
1126 {
1127 .name = "C6",
1128 .desc = "MWAIT 0x52",
1129 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
1130 .exit_latency = 140,
1131 .target_residency = 560,
1132 .enter = &intel_idle,
1133 .enter_s2idle = intel_idle_s2idle, },
1134 {
1135 .name = "C7",
1136 .desc = "MWAIT 0x60",
1137 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
1138 .exit_latency = 1200,
1139 .target_residency = 4000,
1140 .enter = &intel_idle,
1141 .enter_s2idle = intel_idle_s2idle, },
1142 {
1143 .name = "C9",
1144 .desc = "MWAIT 0x64",
1145 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
1146 .exit_latency = 10000,
1147 .target_residency = 20000,
1148 .enter = &intel_idle,
1149 .enter_s2idle = intel_idle_s2idle, },
1150 {
1151 .enter = NULL }
1152 };
1153 static struct cpuidle_state avn_cstates[] __initdata = {
1154 {
1155 .name = "C1",
1156 .desc = "MWAIT 0x00",
1157 .flags = MWAIT2flg(0x00),
1158 .exit_latency = 2,
1159 .target_residency = 2,
1160 .enter = &intel_idle,
1161 .enter_s2idle = intel_idle_s2idle, },
1162 {
1163 .name = "C6",
1164 .desc = "MWAIT 0x51",
1165 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
1166 .exit_latency = 15,
1167 .target_residency = 45,
1168 .enter = &intel_idle,
1169 .enter_s2idle = intel_idle_s2idle, },
1170 {
1171 .enter = NULL }
1172 };
1173 static struct cpuidle_state knl_cstates[] __initdata = {
1174 {
1175 .name = "C1",
1176 .desc = "MWAIT 0x00",
1177 .flags = MWAIT2flg(0x00),
1178 .exit_latency = 1,
1179 .target_residency = 2,
1180 .enter = &intel_idle,
1181 .enter_s2idle = intel_idle_s2idle },
1182 {
1183 .name = "C6",
1184 .desc = "MWAIT 0x10",
1185 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
1186 .exit_latency = 120,
1187 .target_residency = 500,
1188 .enter = &intel_idle,
1189 .enter_s2idle = intel_idle_s2idle },
1190 {
1191 .enter = NULL }
1192 };
1193
1194 static struct cpuidle_state bxt_cstates[] __initdata = {
1195 {
1196 .name = "C1",
1197 .desc = "MWAIT 0x00",
1198 .flags = MWAIT2flg(0x00),
1199 .exit_latency = 2,
1200 .target_residency = 2,
1201 .enter = &intel_idle,
1202 .enter_s2idle = intel_idle_s2idle, },
1203 {
1204 .name = "C1E",
1205 .desc = "MWAIT 0x01",
1206 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1207 .exit_latency = 10,
1208 .target_residency = 20,
1209 .enter = &intel_idle,
1210 .enter_s2idle = intel_idle_s2idle, },
1211 {
1212 .name = "C6",
1213 .desc = "MWAIT 0x20",
1214 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1215 .exit_latency = 133,
1216 .target_residency = 133,
1217 .enter = &intel_idle,
1218 .enter_s2idle = intel_idle_s2idle, },
1219 {
1220 .name = "C7s",
1221 .desc = "MWAIT 0x31",
1222 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
1223 .exit_latency = 155,
1224 .target_residency = 155,
1225 .enter = &intel_idle,
1226 .enter_s2idle = intel_idle_s2idle, },
1227 {
1228 .name = "C8",
1229 .desc = "MWAIT 0x40",
1230 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
1231 .exit_latency = 1000,
1232 .target_residency = 1000,
1233 .enter = &intel_idle,
1234 .enter_s2idle = intel_idle_s2idle, },
1235 {
1236 .name = "C9",
1237 .desc = "MWAIT 0x50",
1238 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
1239 .exit_latency = 2000,
1240 .target_residency = 2000,
1241 .enter = &intel_idle,
1242 .enter_s2idle = intel_idle_s2idle, },
1243 {
1244 .name = "C10",
1245 .desc = "MWAIT 0x60",
1246 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
1247 .exit_latency = 10000,
1248 .target_residency = 10000,
1249 .enter = &intel_idle,
1250 .enter_s2idle = intel_idle_s2idle, },
1251 {
1252 .enter = NULL }
1253 };
1254
1255 static struct cpuidle_state dnv_cstates[] __initdata = {
1256 {
1257 .name = "C1",
1258 .desc = "MWAIT 0x00",
1259 .flags = MWAIT2flg(0x00),
1260 .exit_latency = 2,
1261 .target_residency = 2,
1262 .enter = &intel_idle,
1263 .enter_s2idle = intel_idle_s2idle, },
1264 {
1265 .name = "C1E",
1266 .desc = "MWAIT 0x01",
1267 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1268 .exit_latency = 10,
1269 .target_residency = 20,
1270 .enter = &intel_idle,
1271 .enter_s2idle = intel_idle_s2idle, },
1272 {
1273 .name = "C6",
1274 .desc = "MWAIT 0x20",
1275 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1276 .exit_latency = 50,
1277 .target_residency = 500,
1278 .enter = &intel_idle,
1279 .enter_s2idle = intel_idle_s2idle, },
1280 {
1281 .enter = NULL }
1282 };
1283
1284 /*
1285 * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
1286 * C6, and this is indicated in the CPUID mwait leaf.
1287 */
1288 static struct cpuidle_state snr_cstates[] __initdata = {
1289 {
1290 .name = "C1",
1291 .desc = "MWAIT 0x00",
1292 .flags = MWAIT2flg(0x00),
1293 .exit_latency = 2,
1294 .target_residency = 2,
1295 .enter = &intel_idle,
1296 .enter_s2idle = intel_idle_s2idle, },
1297 {
1298 .name = "C1E",
1299 .desc = "MWAIT 0x01",
1300 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1301 .exit_latency = 15,
1302 .target_residency = 25,
1303 .enter = &intel_idle,
1304 .enter_s2idle = intel_idle_s2idle, },
1305 {
1306 .name = "C6",
1307 .desc = "MWAIT 0x20",
1308 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1309 .exit_latency = 130,
1310 .target_residency = 500,
1311 .enter = &intel_idle,
1312 .enter_s2idle = intel_idle_s2idle, },
1313 {
1314 .enter = NULL }
1315 };
1316
1317 static struct cpuidle_state grr_cstates[] __initdata = {
1318 {
1319 .name = "C1",
1320 .desc = "MWAIT 0x00",
1321 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1322 .exit_latency = 1,
1323 .target_residency = 1,
1324 .enter = &intel_idle,
1325 .enter_s2idle = intel_idle_s2idle, },
1326 {
1327 .name = "C1E",
1328 .desc = "MWAIT 0x01",
1329 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1330 .exit_latency = 2,
1331 .target_residency = 10,
1332 .enter = &intel_idle,
1333 .enter_s2idle = intel_idle_s2idle, },
1334 {
1335 .name = "C6S",
1336 .desc = "MWAIT 0x22",
1337 .flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,
1338 .exit_latency = 140,
1339 .target_residency = 500,
1340 .enter = &intel_idle,
1341 .enter_s2idle = intel_idle_s2idle, },
1342 {
1343 .enter = NULL }
1344 };
1345
1346 static struct cpuidle_state srf_cstates[] __initdata = {
1347 {
1348 .name = "C1",
1349 .desc = "MWAIT 0x00",
1350 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1351 .exit_latency = 1,
1352 .target_residency = 1,
1353 .enter = &intel_idle,
1354 .enter_s2idle = intel_idle_s2idle, },
1355 {
1356 .name = "C1E",
1357 .desc = "MWAIT 0x01",
1358 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1359 .exit_latency = 2,
1360 .target_residency = 10,
1361 .enter = &intel_idle,
1362 .enter_s2idle = intel_idle_s2idle, },
1363 {
1364 .name = "C6S",
1365 .desc = "MWAIT 0x22",
1366 .flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED |
1367 CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
1368 .exit_latency = 270,
1369 .target_residency = 700,
1370 .enter = &intel_idle,
1371 .enter_s2idle = intel_idle_s2idle, },
1372 {
1373 .name = "C6SP",
1374 .desc = "MWAIT 0x23",
1375 .flags = MWAIT2flg(0x23) | CPUIDLE_FLAG_TLB_FLUSHED |
1376 CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
1377 .exit_latency = 310,
1378 .target_residency = 900,
1379 .enter = &intel_idle,
1380 .enter_s2idle = intel_idle_s2idle, },
1381 {
1382 .enter = NULL }
1383 };
1384
1385 static const struct idle_cpu idle_cpu_nehalem __initconst = {
1386 .state_table = nehalem_cstates,
1387 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1388 .disable_promotion_to_c1e = true,
1389 };
1390
1391 static const struct idle_cpu idle_cpu_nhx __initconst = {
1392 .state_table = nehalem_cstates,
1393 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1394 .disable_promotion_to_c1e = true,
1395 .use_acpi = true,
1396 };
1397
1398 static const struct idle_cpu idle_cpu_atom __initconst = {
1399 .state_table = atom_cstates,
1400 };
1401
1402 static const struct idle_cpu idle_cpu_tangier __initconst = {
1403 .state_table = tangier_cstates,
1404 };
1405
1406 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1407 .state_table = atom_cstates,
1408 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1409 };
1410
1411 static const struct idle_cpu idle_cpu_snb __initconst = {
1412 .state_table = snb_cstates,
1413 .disable_promotion_to_c1e = true,
1414 };
1415
1416 static const struct idle_cpu idle_cpu_snx __initconst = {
1417 .state_table = snb_cstates,
1418 .disable_promotion_to_c1e = true,
1419 .use_acpi = true,
1420 };
1421
1422 static const struct idle_cpu idle_cpu_byt __initconst = {
1423 .state_table = byt_cstates,
1424 .disable_promotion_to_c1e = true,
1425 .byt_auto_demotion_disable_flag = true,
1426 };
1427
1428 static const struct idle_cpu idle_cpu_cht __initconst = {
1429 .state_table = cht_cstates,
1430 .disable_promotion_to_c1e = true,
1431 .byt_auto_demotion_disable_flag = true,
1432 };
1433
1434 static const struct idle_cpu idle_cpu_ivb __initconst = {
1435 .state_table = ivb_cstates,
1436 .disable_promotion_to_c1e = true,
1437 };
1438
1439 static const struct idle_cpu idle_cpu_ivt __initconst = {
1440 .state_table = ivt_cstates,
1441 .disable_promotion_to_c1e = true,
1442 .use_acpi = true,
1443 };
1444
1445 static const struct idle_cpu idle_cpu_hsw __initconst = {
1446 .state_table = hsw_cstates,
1447 .disable_promotion_to_c1e = true,
1448 };
1449
1450 static const struct idle_cpu idle_cpu_hsx __initconst = {
1451 .state_table = hsw_cstates,
1452 .disable_promotion_to_c1e = true,
1453 .use_acpi = true,
1454 };
1455
1456 static const struct idle_cpu idle_cpu_bdw __initconst = {
1457 .state_table = bdw_cstates,
1458 .disable_promotion_to_c1e = true,
1459 };
1460
1461 static const struct idle_cpu idle_cpu_bdx __initconst = {
1462 .state_table = bdw_cstates,
1463 .disable_promotion_to_c1e = true,
1464 .use_acpi = true,
1465 };
1466
1467 static const struct idle_cpu idle_cpu_skl __initconst = {
1468 .state_table = skl_cstates,
1469 .disable_promotion_to_c1e = true,
1470 };
1471
1472 static const struct idle_cpu idle_cpu_skx __initconst = {
1473 .state_table = skx_cstates,
1474 .disable_promotion_to_c1e = true,
1475 .use_acpi = true,
1476 };
1477
1478 static const struct idle_cpu idle_cpu_icx __initconst = {
1479 .state_table = icx_cstates,
1480 .disable_promotion_to_c1e = true,
1481 .use_acpi = true,
1482 };
1483
1484 static const struct idle_cpu idle_cpu_adl __initconst = {
1485 .state_table = adl_cstates,
1486 };
1487
1488 static const struct idle_cpu idle_cpu_adl_l __initconst = {
1489 .state_table = adl_l_cstates,
1490 };
1491
1492 static const struct idle_cpu idle_cpu_mtl_l __initconst = {
1493 .state_table = mtl_l_cstates,
1494 };
1495
1496 static const struct idle_cpu idle_cpu_gmt __initconst = {
1497 .state_table = gmt_cstates,
1498 };
1499
1500 static const struct idle_cpu idle_cpu_spr __initconst = {
1501 .state_table = spr_cstates,
1502 .disable_promotion_to_c1e = true,
1503 .use_acpi = true,
1504 };
1505
1506 static const struct idle_cpu idle_cpu_gnr __initconst = {
1507 .state_table = gnr_cstates,
1508 .disable_promotion_to_c1e = true,
1509 .use_acpi = true,
1510 };
1511
1512 static const struct idle_cpu idle_cpu_avn __initconst = {
1513 .state_table = avn_cstates,
1514 .disable_promotion_to_c1e = true,
1515 .use_acpi = true,
1516 };
1517
1518 static const struct idle_cpu idle_cpu_knl __initconst = {
1519 .state_table = knl_cstates,
1520 .use_acpi = true,
1521 };
1522
1523 static const struct idle_cpu idle_cpu_bxt __initconst = {
1524 .state_table = bxt_cstates,
1525 .disable_promotion_to_c1e = true,
1526 };
1527
1528 static const struct idle_cpu idle_cpu_dnv __initconst = {
1529 .state_table = dnv_cstates,
1530 .disable_promotion_to_c1e = true,
1531 .use_acpi = true,
1532 };
1533
1534 static const struct idle_cpu idle_cpu_tmt __initconst = {
1535 .disable_promotion_to_c1e = true,
1536 };
1537
1538 static const struct idle_cpu idle_cpu_snr __initconst = {
1539 .state_table = snr_cstates,
1540 .disable_promotion_to_c1e = true,
1541 .use_acpi = true,
1542 };
1543
1544 static const struct idle_cpu idle_cpu_grr __initconst = {
1545 .state_table = grr_cstates,
1546 .disable_promotion_to_c1e = true,
1547 .use_acpi = true,
1548 };
1549
1550 static const struct idle_cpu idle_cpu_srf __initconst = {
1551 .state_table = srf_cstates,
1552 .disable_promotion_to_c1e = true,
1553 .use_acpi = true,
1554 };
1555
1556 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1557 X86_MATCH_VFM(INTEL_NEHALEM_EP, &idle_cpu_nhx),
1558 X86_MATCH_VFM(INTEL_NEHALEM, &idle_cpu_nehalem),
1559 X86_MATCH_VFM(INTEL_NEHALEM_G, &idle_cpu_nehalem),
1560 X86_MATCH_VFM(INTEL_WESTMERE, &idle_cpu_nehalem),
1561 X86_MATCH_VFM(INTEL_WESTMERE_EP, &idle_cpu_nhx),
1562 X86_MATCH_VFM(INTEL_NEHALEM_EX, &idle_cpu_nhx),
1563 X86_MATCH_VFM(INTEL_ATOM_BONNELL, &idle_cpu_atom),
1564 X86_MATCH_VFM(INTEL_ATOM_BONNELL_MID, &idle_cpu_lincroft),
1565 X86_MATCH_VFM(INTEL_WESTMERE_EX, &idle_cpu_nhx),
1566 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &idle_cpu_snb),
1567 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &idle_cpu_snx),
1568 X86_MATCH_VFM(INTEL_ATOM_SALTWELL, &idle_cpu_atom),
1569 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &idle_cpu_byt),
1570 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1571 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &idle_cpu_cht),
1572 X86_MATCH_VFM(INTEL_IVYBRIDGE, &idle_cpu_ivb),
1573 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &idle_cpu_ivt),
1574 X86_MATCH_VFM(INTEL_HASWELL, &idle_cpu_hsw),
1575 X86_MATCH_VFM(INTEL_HASWELL_X, &idle_cpu_hsx),
1576 X86_MATCH_VFM(INTEL_HASWELL_L, &idle_cpu_hsw),
1577 X86_MATCH_VFM(INTEL_HASWELL_G, &idle_cpu_hsw),
1578 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D, &idle_cpu_avn),
1579 X86_MATCH_VFM(INTEL_BROADWELL, &idle_cpu_bdw),
1580 X86_MATCH_VFM(INTEL_BROADWELL_G, &idle_cpu_bdw),
1581 X86_MATCH_VFM(INTEL_BROADWELL_X, &idle_cpu_bdx),
1582 X86_MATCH_VFM(INTEL_BROADWELL_D, &idle_cpu_bdx),
1583 X86_MATCH_VFM(INTEL_SKYLAKE_L, &idle_cpu_skl),
1584 X86_MATCH_VFM(INTEL_SKYLAKE, &idle_cpu_skl),
1585 X86_MATCH_VFM(INTEL_KABYLAKE_L, &idle_cpu_skl),
1586 X86_MATCH_VFM(INTEL_KABYLAKE, &idle_cpu_skl),
1587 X86_MATCH_VFM(INTEL_SKYLAKE_X, &idle_cpu_skx),
1588 X86_MATCH_VFM(INTEL_ICELAKE_X, &idle_cpu_icx),
1589 X86_MATCH_VFM(INTEL_ICELAKE_D, &idle_cpu_icx),
1590 X86_MATCH_VFM(INTEL_ALDERLAKE, &idle_cpu_adl),
1591 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &idle_cpu_adl_l),
1592 X86_MATCH_VFM(INTEL_METEORLAKE_L, &idle_cpu_mtl_l),
1593 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &idle_cpu_gmt),
1594 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &idle_cpu_spr),
1595 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &idle_cpu_spr),
1596 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &idle_cpu_gnr),
1597 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &idle_cpu_knl),
1598 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &idle_cpu_knl),
1599 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &idle_cpu_bxt),
1600 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1601 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &idle_cpu_dnv),
1602 X86_MATCH_VFM(INTEL_ATOM_TREMONT, &idle_cpu_tmt),
1603 X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &idle_cpu_tmt),
1604 X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &idle_cpu_snr),
1605 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &idle_cpu_grr),
1606 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &idle_cpu_srf),
1607 {}
1608 };
1609
1610 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1611 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, X86_FAMILY_ANY, X86_FEATURE_MWAIT, NULL),
1612 {}
1613 };
1614
intel_idle_max_cstate_reached(int cstate)1615 static bool __init intel_idle_max_cstate_reached(int cstate)
1616 {
1617 if (cstate + 1 > max_cstate) {
1618 pr_info("max_cstate %d reached\n", max_cstate);
1619 return true;
1620 }
1621 return false;
1622 }
1623
intel_idle_state_needs_timer_stop(struct cpuidle_state * state)1624 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1625 {
1626 unsigned long eax = flg2MWAIT(state->flags);
1627
1628 if (boot_cpu_has(X86_FEATURE_ARAT))
1629 return false;
1630
1631 /*
1632 * Switch over to one-shot tick broadcast if the target C-state
1633 * is deeper than C1.
1634 */
1635 return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1636 }
1637
1638 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1639 #include <acpi/processor.h>
1640
1641 static bool no_acpi __read_mostly;
1642 module_param(no_acpi, bool, 0444);
1643 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1644
1645 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1646 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1647 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1648
1649 static struct acpi_processor_power acpi_state_table __initdata;
1650
1651 /**
1652 * intel_idle_cst_usable - Check if the _CST information can be used.
1653 *
1654 * Check if all of the C-states listed by _CST in the max_cstate range are
1655 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1656 */
intel_idle_cst_usable(void)1657 static bool __init intel_idle_cst_usable(void)
1658 {
1659 int cstate, limit;
1660
1661 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1662 acpi_state_table.count);
1663
1664 for (cstate = 1; cstate < limit; cstate++) {
1665 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1666
1667 if (cx->entry_method != ACPI_CSTATE_FFH)
1668 return false;
1669 }
1670
1671 return true;
1672 }
1673
intel_idle_acpi_cst_extract(void)1674 static bool __init intel_idle_acpi_cst_extract(void)
1675 {
1676 unsigned int cpu;
1677
1678 if (no_acpi) {
1679 pr_debug("Not allowed to use ACPI _CST\n");
1680 return false;
1681 }
1682
1683 for_each_possible_cpu(cpu) {
1684 struct acpi_processor *pr = per_cpu(processors, cpu);
1685
1686 if (!pr)
1687 continue;
1688
1689 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1690 continue;
1691
1692 acpi_state_table.count++;
1693
1694 if (!intel_idle_cst_usable())
1695 continue;
1696
1697 if (!acpi_processor_claim_cst_control())
1698 break;
1699
1700 return true;
1701 }
1702
1703 acpi_state_table.count = 0;
1704 pr_debug("ACPI _CST not found or not usable\n");
1705 return false;
1706 }
1707
intel_idle_init_cstates_acpi(struct cpuidle_driver * drv)1708 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1709 {
1710 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1711
1712 /*
1713 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1714 * the interesting states are ACPI_CSTATE_FFH.
1715 */
1716 for (cstate = 1; cstate < limit; cstate++) {
1717 struct acpi_processor_cx *cx;
1718 struct cpuidle_state *state;
1719
1720 if (intel_idle_max_cstate_reached(cstate - 1))
1721 break;
1722
1723 cx = &acpi_state_table.states[cstate];
1724
1725 state = &drv->states[drv->state_count++];
1726
1727 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1728 strscpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1729 state->exit_latency = cx->latency;
1730 /*
1731 * For C1-type C-states use the same number for both the exit
1732 * latency and target residency, because that is the case for
1733 * C1 in the majority of the static C-states tables above.
1734 * For the other types of C-states, however, set the target
1735 * residency to 3 times the exit latency which should lead to
1736 * a reasonable balance between energy-efficiency and
1737 * performance in the majority of interesting cases.
1738 */
1739 state->target_residency = cx->latency;
1740 if (cx->type > ACPI_STATE_C1)
1741 state->target_residency *= 3;
1742
1743 state->flags = MWAIT2flg(cx->address);
1744 if (cx->type > ACPI_STATE_C2)
1745 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1746
1747 if (disabled_states_mask & BIT(cstate))
1748 state->flags |= CPUIDLE_FLAG_OFF;
1749
1750 if (intel_idle_state_needs_timer_stop(state))
1751 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1752
1753 if (cx->type > ACPI_STATE_C1 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1754 mark_tsc_unstable("TSC halts in idle");
1755
1756 state->enter = intel_idle;
1757 state->enter_s2idle = intel_idle_s2idle;
1758 }
1759 }
1760
intel_idle_off_by_default(unsigned int flags,u32 mwait_hint)1761 static bool __init intel_idle_off_by_default(unsigned int flags, u32 mwait_hint)
1762 {
1763 int cstate, limit;
1764
1765 /*
1766 * If there are no _CST C-states, do not disable any C-states by
1767 * default.
1768 */
1769 if (!acpi_state_table.count)
1770 return false;
1771
1772 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1773 /*
1774 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1775 * the interesting states are ACPI_CSTATE_FFH.
1776 */
1777 for (cstate = 1; cstate < limit; cstate++) {
1778 u32 acpi_hint = acpi_state_table.states[cstate].address;
1779 u32 table_hint = mwait_hint;
1780
1781 if (flags & CPUIDLE_FLAG_PARTIAL_HINT_MATCH) {
1782 acpi_hint &= ~MWAIT_SUBSTATE_MASK;
1783 table_hint &= ~MWAIT_SUBSTATE_MASK;
1784 }
1785
1786 if (acpi_hint == table_hint)
1787 return false;
1788 }
1789 return true;
1790 }
1791 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1792 #define force_use_acpi (false)
1793
intel_idle_acpi_cst_extract(void)1794 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
intel_idle_init_cstates_acpi(struct cpuidle_driver * drv)1795 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
intel_idle_off_by_default(unsigned int flags,u32 mwait_hint)1796 static inline bool intel_idle_off_by_default(unsigned int flags, u32 mwait_hint)
1797 {
1798 return false;
1799 }
1800 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1801
1802 /**
1803 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1804 *
1805 * Tune IVT multi-socket targets.
1806 * Assumption: num_sockets == (max_package_num + 1).
1807 */
ivt_idle_state_table_update(void)1808 static void __init ivt_idle_state_table_update(void)
1809 {
1810 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1811 int cpu, package_num, num_sockets = 1;
1812
1813 for_each_online_cpu(cpu) {
1814 package_num = topology_physical_package_id(cpu);
1815 if (package_num + 1 > num_sockets) {
1816 num_sockets = package_num + 1;
1817
1818 if (num_sockets > 4) {
1819 cpuidle_state_table = ivt_cstates_8s;
1820 return;
1821 }
1822 }
1823 }
1824
1825 if (num_sockets > 2)
1826 cpuidle_state_table = ivt_cstates_4s;
1827
1828 /* else, 1 and 2 socket systems use default ivt_cstates */
1829 }
1830
1831 /**
1832 * irtl_2_usec - IRTL to microseconds conversion.
1833 * @irtl: IRTL MSR value.
1834 *
1835 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1836 */
irtl_2_usec(unsigned long long irtl)1837 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1838 {
1839 static const unsigned int irtl_ns_units[] __initconst = {
1840 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1841 };
1842 unsigned long long ns;
1843
1844 if (!irtl)
1845 return 0;
1846
1847 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1848
1849 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1850 }
1851
1852 /**
1853 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1854 *
1855 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1856 * definitive maximum latency and use the same value for target_residency.
1857 */
bxt_idle_state_table_update(void)1858 static void __init bxt_idle_state_table_update(void)
1859 {
1860 unsigned long long msr;
1861 unsigned int usec;
1862
1863 rdmsrl(MSR_PKGC6_IRTL, msr);
1864 usec = irtl_2_usec(msr);
1865 if (usec) {
1866 bxt_cstates[2].exit_latency = usec;
1867 bxt_cstates[2].target_residency = usec;
1868 }
1869
1870 rdmsrl(MSR_PKGC7_IRTL, msr);
1871 usec = irtl_2_usec(msr);
1872 if (usec) {
1873 bxt_cstates[3].exit_latency = usec;
1874 bxt_cstates[3].target_residency = usec;
1875 }
1876
1877 rdmsrl(MSR_PKGC8_IRTL, msr);
1878 usec = irtl_2_usec(msr);
1879 if (usec) {
1880 bxt_cstates[4].exit_latency = usec;
1881 bxt_cstates[4].target_residency = usec;
1882 }
1883
1884 rdmsrl(MSR_PKGC9_IRTL, msr);
1885 usec = irtl_2_usec(msr);
1886 if (usec) {
1887 bxt_cstates[5].exit_latency = usec;
1888 bxt_cstates[5].target_residency = usec;
1889 }
1890
1891 rdmsrl(MSR_PKGC10_IRTL, msr);
1892 usec = irtl_2_usec(msr);
1893 if (usec) {
1894 bxt_cstates[6].exit_latency = usec;
1895 bxt_cstates[6].target_residency = usec;
1896 }
1897
1898 }
1899
1900 /**
1901 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1902 *
1903 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1904 */
sklh_idle_state_table_update(void)1905 static void __init sklh_idle_state_table_update(void)
1906 {
1907 unsigned long long msr;
1908 unsigned int eax, ebx, ecx, edx;
1909
1910
1911 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1912 if (max_cstate <= 7)
1913 return;
1914
1915 /* if PC10 not present in CPUID.MWAIT.EDX */
1916 if ((mwait_substates & (0xF << 28)) == 0)
1917 return;
1918
1919 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1920
1921 /* PC10 is not enabled in PKG C-state limit */
1922 if ((msr & 0xF) != 8)
1923 return;
1924
1925 ecx = 0;
1926 cpuid(7, &eax, &ebx, &ecx, &edx);
1927
1928 /* if SGX is present */
1929 if (ebx & (1 << 2)) {
1930
1931 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1932
1933 /* if SGX is enabled */
1934 if (msr & (1 << 18))
1935 return;
1936 }
1937
1938 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1939 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1940 }
1941
1942 /**
1943 * skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
1944 * idle states table.
1945 */
skx_idle_state_table_update(void)1946 static void __init skx_idle_state_table_update(void)
1947 {
1948 unsigned long long msr;
1949
1950 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1951
1952 /*
1953 * 000b: C0/C1 (no package C-state support)
1954 * 001b: C2
1955 * 010b: C6 (non-retention)
1956 * 011b: C6 (retention)
1957 * 111b: No Package C state limits.
1958 */
1959 if ((msr & 0x7) < 2) {
1960 /*
1961 * Uses the CC6 + PC0 latency and 3 times of
1962 * latency for target_residency if the PC6
1963 * is disabled in BIOS. This is consistent
1964 * with how intel_idle driver uses _CST
1965 * to set the target_residency.
1966 */
1967 skx_cstates[2].exit_latency = 92;
1968 skx_cstates[2].target_residency = 276;
1969 }
1970 }
1971
1972 /**
1973 * adl_idle_state_table_update - Adjust AlderLake idle states table.
1974 */
adl_idle_state_table_update(void)1975 static void __init adl_idle_state_table_update(void)
1976 {
1977 /* Check if user prefers C1 over C1E. */
1978 if (preferred_states_mask & BIT(1) && !(preferred_states_mask & BIT(2))) {
1979 cpuidle_state_table[0].flags &= ~CPUIDLE_FLAG_UNUSABLE;
1980 cpuidle_state_table[1].flags |= CPUIDLE_FLAG_UNUSABLE;
1981
1982 /* Disable C1E by clearing the "C1E promotion" bit. */
1983 c1e_promotion = C1E_PROMOTION_DISABLE;
1984 return;
1985 }
1986
1987 /* Make sure C1E is enabled by default */
1988 c1e_promotion = C1E_PROMOTION_ENABLE;
1989 }
1990
1991 /**
1992 * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table.
1993 */
spr_idle_state_table_update(void)1994 static void __init spr_idle_state_table_update(void)
1995 {
1996 unsigned long long msr;
1997
1998 /*
1999 * By default, the C6 state assumes the worst-case scenario of package
2000 * C6. However, if PC6 is disabled, we update the numbers to match
2001 * core C6.
2002 */
2003 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
2004
2005 /* Limit value 2 and above allow for PC6. */
2006 if ((msr & 0x7) < 2) {
2007 spr_cstates[2].exit_latency = 190;
2008 spr_cstates[2].target_residency = 600;
2009 }
2010 }
2011
intel_idle_verify_cstate(unsigned int mwait_hint)2012 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
2013 {
2014 unsigned int mwait_cstate = (MWAIT_HINT2CSTATE(mwait_hint) + 1) &
2015 MWAIT_CSTATE_MASK;
2016 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
2017 MWAIT_SUBSTATE_MASK;
2018
2019 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
2020 if (num_substates == 0)
2021 return false;
2022
2023 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
2024 mark_tsc_unstable("TSC halts in idle states deeper than C2");
2025
2026 return true;
2027 }
2028
state_update_enter_method(struct cpuidle_state * state,int cstate)2029 static void state_update_enter_method(struct cpuidle_state *state, int cstate)
2030 {
2031 if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) {
2032 /*
2033 * Combining with XSTATE with IBRS or IRQ_ENABLE flags
2034 * is not currently supported but this driver.
2035 */
2036 WARN_ON_ONCE(state->flags & CPUIDLE_FLAG_IBRS);
2037 WARN_ON_ONCE(state->flags & CPUIDLE_FLAG_IRQ_ENABLE);
2038 state->enter = intel_idle_xstate;
2039 return;
2040 }
2041
2042 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) &&
2043 ((state->flags & CPUIDLE_FLAG_IBRS) || ibrs_off)) {
2044 /*
2045 * IBRS mitigation requires that C-states are entered
2046 * with interrupts disabled.
2047 */
2048 if (ibrs_off && (state->flags & CPUIDLE_FLAG_IRQ_ENABLE))
2049 state->flags &= ~CPUIDLE_FLAG_IRQ_ENABLE;
2050 WARN_ON_ONCE(state->flags & CPUIDLE_FLAG_IRQ_ENABLE);
2051 state->enter = intel_idle_ibrs;
2052 return;
2053 }
2054
2055 if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE) {
2056 state->enter = intel_idle_irq;
2057 return;
2058 }
2059
2060 if (force_irq_on) {
2061 pr_info("forced intel_idle_irq for state %d\n", cstate);
2062 state->enter = intel_idle_irq;
2063 }
2064 }
2065
intel_idle_init_cstates_icpu(struct cpuidle_driver * drv)2066 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
2067 {
2068 int cstate;
2069
2070 switch (boot_cpu_data.x86_vfm) {
2071 case INTEL_IVYBRIDGE_X:
2072 ivt_idle_state_table_update();
2073 break;
2074 case INTEL_ATOM_GOLDMONT:
2075 case INTEL_ATOM_GOLDMONT_PLUS:
2076 bxt_idle_state_table_update();
2077 break;
2078 case INTEL_SKYLAKE:
2079 sklh_idle_state_table_update();
2080 break;
2081 case INTEL_SKYLAKE_X:
2082 skx_idle_state_table_update();
2083 break;
2084 case INTEL_SAPPHIRERAPIDS_X:
2085 case INTEL_EMERALDRAPIDS_X:
2086 spr_idle_state_table_update();
2087 break;
2088 case INTEL_ALDERLAKE:
2089 case INTEL_ALDERLAKE_L:
2090 case INTEL_ATOM_GRACEMONT:
2091 adl_idle_state_table_update();
2092 break;
2093 }
2094
2095 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
2096 struct cpuidle_state *state;
2097 unsigned int mwait_hint;
2098
2099 if (intel_idle_max_cstate_reached(cstate))
2100 break;
2101
2102 if (!cpuidle_state_table[cstate].enter &&
2103 !cpuidle_state_table[cstate].enter_s2idle)
2104 break;
2105
2106 /* If marked as unusable, skip this state. */
2107 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
2108 pr_debug("state %s is disabled\n",
2109 cpuidle_state_table[cstate].name);
2110 continue;
2111 }
2112
2113 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
2114 if (!intel_idle_verify_cstate(mwait_hint))
2115 continue;
2116
2117 /* Structure copy. */
2118 drv->states[drv->state_count] = cpuidle_state_table[cstate];
2119 state = &drv->states[drv->state_count];
2120
2121 state_update_enter_method(state, cstate);
2122
2123
2124 if ((disabled_states_mask & BIT(drv->state_count)) ||
2125 ((icpu->use_acpi || force_use_acpi) &&
2126 intel_idle_off_by_default(state->flags, mwait_hint) &&
2127 !(state->flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
2128 state->flags |= CPUIDLE_FLAG_OFF;
2129
2130 if (intel_idle_state_needs_timer_stop(state))
2131 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
2132
2133 drv->state_count++;
2134 }
2135
2136 if (icpu->byt_auto_demotion_disable_flag) {
2137 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
2138 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
2139 }
2140 }
2141
2142 /**
2143 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
2144 * @drv: cpuidle driver structure to initialize.
2145 */
intel_idle_cpuidle_driver_init(struct cpuidle_driver * drv)2146 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
2147 {
2148 cpuidle_poll_state_init(drv);
2149
2150 if (disabled_states_mask & BIT(0))
2151 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
2152
2153 drv->state_count = 1;
2154
2155 if (icpu && icpu->state_table)
2156 intel_idle_init_cstates_icpu(drv);
2157 else
2158 intel_idle_init_cstates_acpi(drv);
2159 }
2160
auto_demotion_disable(void)2161 static void auto_demotion_disable(void)
2162 {
2163 unsigned long long msr_bits;
2164
2165 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
2166 msr_bits &= ~auto_demotion_disable_flags;
2167 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
2168 }
2169
c1e_promotion_enable(void)2170 static void c1e_promotion_enable(void)
2171 {
2172 unsigned long long msr_bits;
2173
2174 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
2175 msr_bits |= 0x2;
2176 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
2177 }
2178
c1e_promotion_disable(void)2179 static void c1e_promotion_disable(void)
2180 {
2181 unsigned long long msr_bits;
2182
2183 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
2184 msr_bits &= ~0x2;
2185 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
2186 }
2187
2188 /**
2189 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
2190 * @cpu: CPU to initialize.
2191 *
2192 * Register a cpuidle device object for @cpu and update its MSRs in accordance
2193 * with the processor model flags.
2194 */
intel_idle_cpu_init(unsigned int cpu)2195 static int intel_idle_cpu_init(unsigned int cpu)
2196 {
2197 struct cpuidle_device *dev;
2198
2199 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
2200 dev->cpu = cpu;
2201
2202 if (cpuidle_register_device(dev)) {
2203 pr_debug("cpuidle_register_device %d failed!\n", cpu);
2204 return -EIO;
2205 }
2206
2207 if (auto_demotion_disable_flags)
2208 auto_demotion_disable();
2209
2210 if (c1e_promotion == C1E_PROMOTION_ENABLE)
2211 c1e_promotion_enable();
2212 else if (c1e_promotion == C1E_PROMOTION_DISABLE)
2213 c1e_promotion_disable();
2214
2215 return 0;
2216 }
2217
intel_idle_cpu_online(unsigned int cpu)2218 static int intel_idle_cpu_online(unsigned int cpu)
2219 {
2220 struct cpuidle_device *dev;
2221
2222 if (!boot_cpu_has(X86_FEATURE_ARAT))
2223 tick_broadcast_enable();
2224
2225 /*
2226 * Some systems can hotplug a cpu at runtime after
2227 * the kernel has booted, we have to initialize the
2228 * driver in this case
2229 */
2230 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
2231 if (!dev->registered)
2232 return intel_idle_cpu_init(cpu);
2233
2234 return 0;
2235 }
2236
2237 /**
2238 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
2239 */
intel_idle_cpuidle_devices_uninit(void)2240 static void __init intel_idle_cpuidle_devices_uninit(void)
2241 {
2242 int i;
2243
2244 for_each_online_cpu(i)
2245 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
2246 }
2247
intel_idle_init(void)2248 static int __init intel_idle_init(void)
2249 {
2250 const struct x86_cpu_id *id;
2251 unsigned int eax, ebx, ecx;
2252 int retval;
2253
2254 /* Do not load intel_idle at all for now if idle= is passed */
2255 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
2256 return -ENODEV;
2257
2258 if (max_cstate == 0) {
2259 pr_debug("disabled\n");
2260 return -EPERM;
2261 }
2262
2263 id = x86_match_cpu(intel_idle_ids);
2264 if (id) {
2265 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
2266 pr_debug("Please enable MWAIT in BIOS SETUP\n");
2267 return -ENODEV;
2268 }
2269 } else {
2270 id = x86_match_cpu(intel_mwait_ids);
2271 if (!id)
2272 return -ENODEV;
2273 }
2274
2275 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
2276 return -ENODEV;
2277
2278 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
2279
2280 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
2281 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
2282 !mwait_substates)
2283 return -ENODEV;
2284
2285 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
2286
2287 icpu = (const struct idle_cpu *)id->driver_data;
2288 if (icpu) {
2289 if (icpu->state_table)
2290 cpuidle_state_table = icpu->state_table;
2291 else if (!intel_idle_acpi_cst_extract())
2292 return -ENODEV;
2293
2294 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
2295 if (icpu->disable_promotion_to_c1e)
2296 c1e_promotion = C1E_PROMOTION_DISABLE;
2297 if (icpu->use_acpi || force_use_acpi)
2298 intel_idle_acpi_cst_extract();
2299 } else if (!intel_idle_acpi_cst_extract()) {
2300 return -ENODEV;
2301 }
2302
2303 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
2304 boot_cpu_data.x86_model);
2305
2306 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
2307 if (!intel_idle_cpuidle_devices)
2308 return -ENOMEM;
2309
2310 intel_idle_cpuidle_driver_init(&intel_idle_driver);
2311
2312 retval = cpuidle_register_driver(&intel_idle_driver);
2313 if (retval) {
2314 struct cpuidle_driver *drv = cpuidle_get_driver();
2315 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
2316 drv ? drv->name : "none");
2317 goto init_driver_fail;
2318 }
2319
2320 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
2321 intel_idle_cpu_online, NULL);
2322 if (retval < 0)
2323 goto hp_setup_fail;
2324
2325 pr_debug("Local APIC timer is reliable in %s\n",
2326 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
2327
2328 return 0;
2329
2330 hp_setup_fail:
2331 intel_idle_cpuidle_devices_uninit();
2332 cpuidle_unregister_driver(&intel_idle_driver);
2333 init_driver_fail:
2334 free_percpu(intel_idle_cpuidle_devices);
2335 return retval;
2336
2337 }
2338 device_initcall(intel_idle_init);
2339
2340 /*
2341 * We are not really modular, but we used to support that. Meaning we also
2342 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
2343 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
2344 * is the easiest way (currently) to continue doing that.
2345 */
2346 module_param(max_cstate, int, 0444);
2347 /*
2348 * The positions of the bits that are set in this number are the indices of the
2349 * idle states to be disabled by default (as reflected by the names of the
2350 * corresponding idle state directories in sysfs, "state0", "state1" ...
2351 * "state<i>" ..., where <i> is the index of the given state).
2352 */
2353 module_param_named(states_off, disabled_states_mask, uint, 0444);
2354 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");
2355 /*
2356 * Some platforms come with mutually exclusive C-states, so that if one is
2357 * enabled, the other C-states must not be used. Example: C1 and C1E on
2358 * Sapphire Rapids platform. This parameter allows for selecting the
2359 * preferred C-states among the groups of mutually exclusive C-states - the
2360 * selected C-states will be registered, the other C-states from the mutually
2361 * exclusive group won't be registered. If the platform has no mutually
2362 * exclusive C-states, this parameter has no effect.
2363 */
2364 module_param_named(preferred_cstates, preferred_states_mask, uint, 0444);
2365 MODULE_PARM_DESC(preferred_cstates, "Mask of preferred idle states");
2366 /*
2367 * Debugging option that forces the driver to enter all C-states with
2368 * interrupts enabled. Does not apply to C-states with
2369 * 'CPUIDLE_FLAG_INIT_XSTATE' and 'CPUIDLE_FLAG_IBRS' flags.
2370 */
2371 module_param(force_irq_on, bool, 0444);
2372 /*
2373 * Force the disabling of IBRS when X86_FEATURE_KERNEL_IBRS is on and
2374 * CPUIDLE_FLAG_IRQ_ENABLE isn't set.
2375 */
2376 module_param(ibrs_off, bool, 0444);
2377 MODULE_PARM_DESC(ibrs_off, "Disable IBRS when idle");
2378