1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_REVERSE_CPUID_H
3 #define ARCH_X86_KVM_REVERSE_CPUID_H
4
5 #include <uapi/asm/kvm.h>
6 #include <asm/cpufeature.h>
7 #include <asm/cpufeatures.h>
8
9 /*
10 * Hardware-defined CPUID leafs that are either scattered by the kernel or are
11 * unknown to the kernel, but need to be directly used by KVM. Note, these
12 * word values conflict with the kernel's "bug" caps, but KVM doesn't use those.
13 */
14 enum kvm_only_cpuid_leafs {
15 CPUID_12_EAX = NCAPINTS,
16 CPUID_7_1_EDX,
17 CPUID_8000_0007_EDX,
18 CPUID_8000_0022_EAX,
19 CPUID_7_2_EDX,
20 CPUID_24_0_EBX,
21 CPUID_8000_0021_ECX,
22 NR_KVM_CPU_CAPS,
23
24 NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
25 };
26
27 /*
28 * Define a KVM-only feature flag.
29 *
30 * For features that are scattered by cpufeatures.h, __feature_translate() also
31 * needs to be updated to translate the kernel-defined feature into the
32 * KVM-defined feature.
33 *
34 * For features that are 100% KVM-only, i.e. not defined by cpufeatures.h,
35 * forego the intermediate KVM_X86_FEATURE and directly define X86_FEATURE_* so
36 * that X86_FEATURE_* can be used in KVM. No __feature_translate() handling is
37 * needed in this case.
38 */
39 #define KVM_X86_FEATURE(w, f) ((w)*32 + (f))
40
41 /* Intel-defined SGX sub-features, CPUID level 0x12 (EAX). */
42 #define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0)
43 #define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1)
44 #define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11)
45
46 /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
47 #define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
48 #define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
49 #define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
50 #define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
51 #define X86_FEATURE_AVX10 KVM_X86_FEATURE(CPUID_7_1_EDX, 19)
52
53 /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */
54 #define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0)
55 #define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1)
56 #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2)
57 #define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3)
58 #define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
59 #define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
60
61 /* Intel-defined sub-features, CPUID level 0x00000024:0 (EBX) */
62 #define X86_FEATURE_AVX10_128 KVM_X86_FEATURE(CPUID_24_0_EBX, 16)
63 #define X86_FEATURE_AVX10_256 KVM_X86_FEATURE(CPUID_24_0_EBX, 17)
64 #define X86_FEATURE_AVX10_512 KVM_X86_FEATURE(CPUID_24_0_EBX, 18)
65
66 /* CPUID level 0x80000007 (EDX). */
67 #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8)
68
69 /* CPUID level 0x80000022 (EAX) */
70 #define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0)
71
72 /* CPUID level 0x80000021 (ECX) */
73 #define KVM_X86_FEATURE_TSA_SQ_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 1)
74 #define KVM_X86_FEATURE_TSA_L1_NO KVM_X86_FEATURE(CPUID_8000_0021_ECX, 2)
75
76 struct cpuid_reg {
77 u32 function;
78 u32 index;
79 int reg;
80 };
81
82 static const struct cpuid_reg reverse_cpuid[] = {
83 [CPUID_1_EDX] = { 1, 0, CPUID_EDX},
84 [CPUID_8000_0001_EDX] = {0x80000001, 0, CPUID_EDX},
85 [CPUID_8086_0001_EDX] = {0x80860001, 0, CPUID_EDX},
86 [CPUID_1_ECX] = { 1, 0, CPUID_ECX},
87 [CPUID_C000_0001_EDX] = {0xc0000001, 0, CPUID_EDX},
88 [CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX},
89 [CPUID_7_0_EBX] = { 7, 0, CPUID_EBX},
90 [CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX},
91 [CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX},
92 [CPUID_6_EAX] = { 6, 0, CPUID_EAX},
93 [CPUID_8000_000A_EDX] = {0x8000000a, 0, CPUID_EDX},
94 [CPUID_7_ECX] = { 7, 0, CPUID_ECX},
95 [CPUID_8000_0007_EBX] = {0x80000007, 0, CPUID_EBX},
96 [CPUID_7_EDX] = { 7, 0, CPUID_EDX},
97 [CPUID_7_1_EAX] = { 7, 1, CPUID_EAX},
98 [CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
99 [CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
100 [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX},
101 [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX},
102 [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
103 [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX},
104 [CPUID_7_2_EDX] = { 7, 2, CPUID_EDX},
105 [CPUID_24_0_EBX] = { 0x24, 0, CPUID_EBX},
106 [CPUID_8000_0021_ECX] = {0x80000021, 0, CPUID_ECX},
107 };
108
109 /*
110 * Reverse CPUID and its derivatives can only be used for hardware-defined
111 * feature words, i.e. words whose bits directly correspond to a CPUID leaf.
112 * Retrieving a feature bit or masking guest CPUID from a Linux-defined word
113 * is nonsensical as the bit number/mask is an arbitrary software-defined value
114 * and can't be used by KVM to query/control guest capabilities. And obviously
115 * the leaf being queried must have an entry in the lookup table.
116 */
reverse_cpuid_check(unsigned int x86_leaf)117 static __always_inline void reverse_cpuid_check(unsigned int x86_leaf)
118 {
119 BUILD_BUG_ON(NR_CPUID_WORDS != NCAPINTS);
120 BUILD_BUG_ON(x86_leaf == CPUID_LNX_1);
121 BUILD_BUG_ON(x86_leaf == CPUID_LNX_2);
122 BUILD_BUG_ON(x86_leaf == CPUID_LNX_3);
123 BUILD_BUG_ON(x86_leaf == CPUID_LNX_4);
124 BUILD_BUG_ON(x86_leaf == CPUID_LNX_5);
125 BUILD_BUG_ON(x86_leaf >= ARRAY_SIZE(reverse_cpuid));
126 BUILD_BUG_ON(reverse_cpuid[x86_leaf].function == 0);
127 }
128
129 /*
130 * Translate feature bits that are scattered in the kernel's cpufeatures word
131 * into KVM feature words that align with hardware's definitions.
132 */
__feature_translate(int x86_feature)133 static __always_inline u32 __feature_translate(int x86_feature)
134 {
135 #define KVM_X86_TRANSLATE_FEATURE(f) \
136 case X86_FEATURE_##f: return KVM_X86_FEATURE_##f
137
138 switch (x86_feature) {
139 KVM_X86_TRANSLATE_FEATURE(SGX1);
140 KVM_X86_TRANSLATE_FEATURE(SGX2);
141 KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA);
142 KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC);
143 KVM_X86_TRANSLATE_FEATURE(PERFMON_V2);
144 KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL);
145 KVM_X86_TRANSLATE_FEATURE(BHI_CTRL);
146 KVM_X86_TRANSLATE_FEATURE(TSA_SQ_NO);
147 KVM_X86_TRANSLATE_FEATURE(TSA_L1_NO);
148 default:
149 return x86_feature;
150 }
151 }
152
__feature_leaf(int x86_feature)153 static __always_inline u32 __feature_leaf(int x86_feature)
154 {
155 return __feature_translate(x86_feature) / 32;
156 }
157
158 /*
159 * Retrieve the bit mask from an X86_FEATURE_* definition. Features contain
160 * the hardware defined bit number (stored in bits 4:0) and a software defined
161 * "word" (stored in bits 31:5). The word is used to index into arrays of
162 * bit masks that hold the per-cpu feature capabilities, e.g. this_cpu_has().
163 */
__feature_bit(int x86_feature)164 static __always_inline u32 __feature_bit(int x86_feature)
165 {
166 x86_feature = __feature_translate(x86_feature);
167
168 reverse_cpuid_check(x86_feature / 32);
169 return 1 << (x86_feature & 31);
170 }
171
172 #define feature_bit(name) __feature_bit(X86_FEATURE_##name)
173
x86_feature_cpuid(unsigned int x86_feature)174 static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned int x86_feature)
175 {
176 unsigned int x86_leaf = __feature_leaf(x86_feature);
177
178 reverse_cpuid_check(x86_leaf);
179 return reverse_cpuid[x86_leaf];
180 }
181
__cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,u32 reg)182 static __always_inline u32 *__cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
183 u32 reg)
184 {
185 switch (reg) {
186 case CPUID_EAX:
187 return &entry->eax;
188 case CPUID_EBX:
189 return &entry->ebx;
190 case CPUID_ECX:
191 return &entry->ecx;
192 case CPUID_EDX:
193 return &entry->edx;
194 default:
195 BUILD_BUG();
196 return NULL;
197 }
198 }
199
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature)200 static __always_inline u32 *cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
201 unsigned int x86_feature)
202 {
203 const struct cpuid_reg cpuid = x86_feature_cpuid(x86_feature);
204
205 return __cpuid_entry_get_reg(entry, cpuid.reg);
206 }
207
cpuid_entry_get(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature)208 static __always_inline u32 cpuid_entry_get(struct kvm_cpuid_entry2 *entry,
209 unsigned int x86_feature)
210 {
211 u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
212
213 return *reg & __feature_bit(x86_feature);
214 }
215
cpuid_entry_has(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature)216 static __always_inline bool cpuid_entry_has(struct kvm_cpuid_entry2 *entry,
217 unsigned int x86_feature)
218 {
219 return cpuid_entry_get(entry, x86_feature);
220 }
221
cpuid_entry_clear(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature)222 static __always_inline void cpuid_entry_clear(struct kvm_cpuid_entry2 *entry,
223 unsigned int x86_feature)
224 {
225 u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
226
227 *reg &= ~__feature_bit(x86_feature);
228 }
229
cpuid_entry_set(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature)230 static __always_inline void cpuid_entry_set(struct kvm_cpuid_entry2 *entry,
231 unsigned int x86_feature)
232 {
233 u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
234
235 *reg |= __feature_bit(x86_feature);
236 }
237
cpuid_entry_change(struct kvm_cpuid_entry2 * entry,unsigned int x86_feature,bool set)238 static __always_inline void cpuid_entry_change(struct kvm_cpuid_entry2 *entry,
239 unsigned int x86_feature,
240 bool set)
241 {
242 u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
243
244 /*
245 * Open coded instead of using cpuid_entry_{clear,set}() to coerce the
246 * compiler into using CMOV instead of Jcc when possible.
247 */
248 if (set)
249 *reg |= __feature_bit(x86_feature);
250 else
251 *reg &= ~__feature_bit(x86_feature);
252 }
253
254 #endif /* ARCH_X86_KVM_REVERSE_CPUID_H */
255