1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 power-domains = <&CPU_PD0>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clocks { 43 clk_dsi_txbyte: txbyteclk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <0>; 47 }; 48 49 clk_rcbsec: clk-rcbsec { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <64000000>; 53 }; 54 }; 55 56 firmware { 57 optee: optee { 58 compatible = "linaro,optee-tz"; 59 method = "smc"; 60 interrupt-parent = <&intc>; 61 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 62 }; 63 64 scmi { 65 compatible = "linaro,scmi-optee"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 linaro,optee-channel-id = <0>; 69 70 scmi_clk: protocol@14 { 71 reg = <0x14>; 72 #clock-cells = <1>; 73 }; 74 75 scmi_reset: protocol@16 { 76 reg = <0x16>; 77 #reset-cells = <1>; 78 }; 79 80 scmi_voltd: protocol@17 { 81 reg = <0x17>; 82 83 scmi_regu: regulators { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 scmi_vddio1: regulator@0 { 88 reg = <VOLTD_SCMI_VDDIO1>; 89 regulator-name = "vddio1"; 90 }; 91 scmi_vddio2: regulator@1 { 92 reg = <VOLTD_SCMI_VDDIO2>; 93 regulator-name = "vddio2"; 94 }; 95 scmi_vddio3: regulator@2 { 96 reg = <VOLTD_SCMI_VDDIO3>; 97 regulator-name = "vddio3"; 98 }; 99 scmi_vddio4: regulator@3 { 100 reg = <VOLTD_SCMI_VDDIO4>; 101 regulator-name = "vddio4"; 102 }; 103 scmi_vdd33ucpd: regulator@5 { 104 reg = <VOLTD_SCMI_UCPD>; 105 regulator-name = "vdd33ucpd"; 106 }; 107 scmi_vdda18adc: regulator@7 { 108 reg = <VOLTD_SCMI_ADC>; 109 regulator-name = "vdda18adc"; 110 }; 111 }; 112 }; 113 }; 114 }; 115 116 intc: interrupt-controller@4ac00000 { 117 compatible = "arm,gic-400"; 118 #interrupt-cells = <3>; 119 interrupt-controller; 120 reg = <0x0 0x4ac10000 0x0 0x1000>, 121 <0x0 0x4ac20000 0x0 0x20000>, 122 <0x0 0x4ac40000 0x0 0x20000>, 123 <0x0 0x4ac60000 0x0 0x20000>; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0"; 128 method = "smc"; 129 130 CPU_PD0: power-domain-cpu0 { 131 #power-domain-cells = <0>; 132 power-domains = <&CLUSTER_PD>; 133 }; 134 135 CLUSTER_PD: power-domain-cluster { 136 #power-domain-cells = <0>; 137 power-domains = <&RET_PD>; 138 }; 139 140 RET_PD: power-domain-retention { 141 #power-domain-cells = <0>; 142 }; 143 }; 144 145 timer { 146 compatible = "arm,armv8-timer"; 147 interrupt-parent = <&intc>; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 152 arm,no-tick-in-suspend; 153 }; 154 155 soc@0 { 156 compatible = "simple-bus"; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 interrupt-parent = <&intc>; 160 ranges = <0x0 0x0 0x0 0x80000000>; 161 162 hpdma: dma-controller@40400000 { 163 compatible = "st,stm32mp25-dma3"; 164 reg = <0x40400000 0x1000>; 165 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 182 #dma-cells = <3>; 183 }; 184 185 hpdma2: dma-controller@40410000 { 186 compatible = "st,stm32mp25-dma3"; 187 reg = <0x40410000 0x1000>; 188 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 205 #dma-cells = <3>; 206 }; 207 208 hpdma3: dma-controller@40420000 { 209 compatible = "st,stm32mp25-dma3"; 210 reg = <0x40420000 0x1000>; 211 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 228 #dma-cells = <3>; 229 }; 230 231 rifsc: bus@42080000 { 232 compatible = "st,stm32mp25-rifsc", "simple-bus"; 233 reg = <0x42080000 0x1000>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 #access-controller-cells = <1>; 237 ranges; 238 239 spi2: spi@400b0000 { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 compatible = "st,stm32mp25-spi"; 243 reg = <0x400b0000 0x400>; 244 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&rcc CK_KER_SPI2>; 246 resets = <&rcc SPI2_R>; 247 access-controllers = <&rifsc 23>; 248 status = "disabled"; 249 }; 250 251 spi3: spi@400c0000 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "st,stm32mp25-spi"; 255 reg = <0x400c0000 0x400>; 256 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&rcc CK_KER_SPI3>; 258 resets = <&rcc SPI3_R>; 259 access-controllers = <&rifsc 24>; 260 status = "disabled"; 261 }; 262 263 usart2: serial@400e0000 { 264 compatible = "st,stm32h7-uart"; 265 reg = <0x400e0000 0x400>; 266 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&rcc CK_KER_USART2>; 268 access-controllers = <&rifsc 32>; 269 status = "disabled"; 270 }; 271 272 usart3: serial@400f0000 { 273 compatible = "st,stm32h7-uart"; 274 reg = <0x400f0000 0x400>; 275 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&rcc CK_KER_USART3>; 277 access-controllers = <&rifsc 33>; 278 status = "disabled"; 279 }; 280 281 uart4: serial@40100000 { 282 compatible = "st,stm32h7-uart"; 283 reg = <0x40100000 0x400>; 284 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&rcc CK_KER_UART4>; 286 access-controllers = <&rifsc 34>; 287 status = "disabled"; 288 }; 289 290 uart5: serial@40110000 { 291 compatible = "st,stm32h7-uart"; 292 reg = <0x40110000 0x400>; 293 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&rcc CK_KER_UART5>; 295 access-controllers = <&rifsc 35>; 296 status = "disabled"; 297 }; 298 299 i2c1: i2c@40120000 { 300 compatible = "st,stm32mp25-i2c"; 301 reg = <0x40120000 0x400>; 302 interrupt-names = "event"; 303 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&rcc CK_KER_I2C1>; 305 resets = <&rcc I2C1_R>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 access-controllers = <&rifsc 41>; 309 status = "disabled"; 310 }; 311 312 i2c2: i2c@40130000 { 313 compatible = "st,stm32mp25-i2c"; 314 reg = <0x40130000 0x400>; 315 interrupt-names = "event"; 316 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&rcc CK_KER_I2C2>; 318 resets = <&rcc I2C2_R>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 access-controllers = <&rifsc 42>; 322 status = "disabled"; 323 }; 324 325 i2c3: i2c@40140000 { 326 compatible = "st,stm32mp25-i2c"; 327 reg = <0x40140000 0x400>; 328 interrupt-names = "event"; 329 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&rcc CK_KER_I2C3>; 331 resets = <&rcc I2C3_R>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 access-controllers = <&rifsc 43>; 335 status = "disabled"; 336 }; 337 338 i2c4: i2c@40150000 { 339 compatible = "st,stm32mp25-i2c"; 340 reg = <0x40150000 0x400>; 341 interrupt-names = "event"; 342 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&rcc CK_KER_I2C4>; 344 resets = <&rcc I2C4_R>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 access-controllers = <&rifsc 44>; 348 status = "disabled"; 349 }; 350 351 i2c5: i2c@40160000 { 352 compatible = "st,stm32mp25-i2c"; 353 reg = <0x40160000 0x400>; 354 interrupt-names = "event"; 355 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&rcc CK_KER_I2C5>; 357 resets = <&rcc I2C5_R>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 access-controllers = <&rifsc 45>; 361 status = "disabled"; 362 }; 363 364 i2c6: i2c@40170000 { 365 compatible = "st,stm32mp25-i2c"; 366 reg = <0x40170000 0x400>; 367 interrupt-names = "event"; 368 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&rcc CK_KER_I2C6>; 370 resets = <&rcc I2C6_R>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 access-controllers = <&rifsc 46>; 374 status = "disabled"; 375 }; 376 377 i2c7: i2c@40180000 { 378 compatible = "st,stm32mp25-i2c"; 379 reg = <0x40180000 0x400>; 380 interrupt-names = "event"; 381 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&rcc CK_KER_I2C7>; 383 resets = <&rcc I2C7_R>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 access-controllers = <&rifsc 47>; 387 status = "disabled"; 388 }; 389 390 usart6: serial@40220000 { 391 compatible = "st,stm32h7-uart"; 392 reg = <0x40220000 0x400>; 393 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&rcc CK_KER_USART6>; 395 access-controllers = <&rifsc 36>; 396 status = "disabled"; 397 }; 398 399 spi1: spi@40230000 { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 compatible = "st,stm32mp25-spi"; 403 reg = <0x40230000 0x400>; 404 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&rcc CK_KER_SPI1>; 406 resets = <&rcc SPI1_R>; 407 access-controllers = <&rifsc 22>; 408 status = "disabled"; 409 }; 410 411 spi4: spi@40240000 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 compatible = "st,stm32mp25-spi"; 415 reg = <0x40240000 0x400>; 416 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&rcc CK_KER_SPI4>; 418 resets = <&rcc SPI4_R>; 419 access-controllers = <&rifsc 25>; 420 status = "disabled"; 421 }; 422 423 spi5: spi@40280000 { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 compatible = "st,stm32mp25-spi"; 427 reg = <0x40280000 0x400>; 428 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&rcc CK_KER_SPI5>; 430 resets = <&rcc SPI5_R>; 431 access-controllers = <&rifsc 26>; 432 status = "disabled"; 433 }; 434 435 uart9: serial@402c0000 { 436 compatible = "st,stm32h7-uart"; 437 reg = <0x402c0000 0x400>; 438 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&rcc CK_KER_UART9>; 440 access-controllers = <&rifsc 39>; 441 status = "disabled"; 442 }; 443 444 usart1: serial@40330000 { 445 compatible = "st,stm32h7-uart"; 446 reg = <0x40330000 0x400>; 447 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&rcc CK_KER_USART1>; 449 access-controllers = <&rifsc 31>; 450 status = "disabled"; 451 }; 452 453 spi6: spi@40350000 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 compatible = "st,stm32mp25-spi"; 457 reg = <0x40350000 0x400>; 458 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&rcc CK_KER_SPI6>; 460 resets = <&rcc SPI6_R>; 461 access-controllers = <&rifsc 27>; 462 status = "disabled"; 463 }; 464 465 spi7: spi@40360000 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 compatible = "st,stm32mp25-spi"; 469 reg = <0x40360000 0x400>; 470 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&rcc CK_KER_SPI7>; 472 resets = <&rcc SPI7_R>; 473 access-controllers = <&rifsc 28>; 474 status = "disabled"; 475 }; 476 477 uart7: serial@40370000 { 478 compatible = "st,stm32h7-uart"; 479 reg = <0x40370000 0x400>; 480 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&rcc CK_KER_UART7>; 482 access-controllers = <&rifsc 37>; 483 status = "disabled"; 484 }; 485 486 uart8: serial@40380000 { 487 compatible = "st,stm32h7-uart"; 488 reg = <0x40380000 0x400>; 489 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&rcc CK_KER_UART8>; 491 access-controllers = <&rifsc 38>; 492 status = "disabled"; 493 }; 494 495 spi8: spi@46020000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "st,stm32mp25-spi"; 499 reg = <0x46020000 0x400>; 500 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&rcc CK_KER_SPI8>; 502 resets = <&rcc SPI8_R>; 503 access-controllers = <&rifsc 29>; 504 status = "disabled"; 505 }; 506 507 i2c8: i2c@46040000 { 508 compatible = "st,stm32mp25-i2c"; 509 reg = <0x46040000 0x400>; 510 interrupt-names = "event"; 511 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&rcc CK_KER_I2C8>; 513 resets = <&rcc I2C8_R>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 access-controllers = <&rifsc 48>; 517 status = "disabled"; 518 }; 519 520 sdmmc1: mmc@48220000 { 521 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 522 arm,primecell-periphid = <0x00353180>; 523 reg = <0x48220000 0x400>, <0x44230400 0x8>; 524 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&rcc CK_KER_SDMMC1 >; 526 clock-names = "apb_pclk"; 527 resets = <&rcc SDMMC1_R>; 528 cap-sd-highspeed; 529 cap-mmc-highspeed; 530 max-frequency = <120000000>; 531 access-controllers = <&rifsc 76>; 532 status = "disabled"; 533 }; 534 535 ethernet1: ethernet@482c0000 { 536 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 537 reg = <0x482c0000 0x4000>; 538 reg-names = "stmmaceth"; 539 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 540 interrupt-names = "macirq"; 541 clock-names = "stmmaceth", 542 "mac-clk-tx", 543 "mac-clk-rx", 544 "ptp_ref", 545 "ethstp", 546 "eth-ck"; 547 clocks = <&rcc CK_ETH1_MAC>, 548 <&rcc CK_ETH1_TX>, 549 <&rcc CK_ETH1_RX>, 550 <&rcc CK_KER_ETH1PTP>, 551 <&rcc CK_ETH1_STP>, 552 <&rcc CK_KER_ETH1>; 553 snps,axi-config = <&stmmac_axi_config_1>; 554 snps,mixed-burst; 555 snps,mtl-rx-config = <&mtl_rx_setup_1>; 556 snps,mtl-tx-config = <&mtl_tx_setup_1>; 557 snps,pbl = <2>; 558 snps,tso; 559 st,syscon = <&syscfg 0x3000>; 560 access-controllers = <&rifsc 60>; 561 status = "disabled"; 562 563 mtl_rx_setup_1: rx-queues-config { 564 snps,rx-queues-to-use = <2>; 565 queue0 {}; 566 queue1 {}; 567 }; 568 569 mtl_tx_setup_1: tx-queues-config { 570 snps,tx-queues-to-use = <4>; 571 queue0 {}; 572 queue1 {}; 573 queue2 {}; 574 queue3 {}; 575 }; 576 577 stmmac_axi_config_1: stmmac-axi-config { 578 snps,blen = <0 0 0 0 16 8 4>; 579 snps,rd_osr_lmt = <0x7>; 580 snps,wr_osr_lmt = <0x7>; 581 }; 582 }; 583 }; 584 585 bsec: efuse@44000000 { 586 compatible = "st,stm32mp25-bsec"; 587 reg = <0x44000000 0x1000>; 588 #address-cells = <1>; 589 #size-cells = <1>; 590 591 part_number_otp@24 { 592 reg = <0x24 0x4>; 593 }; 594 595 package_otp@1e8 { 596 reg = <0x1e8 0x1>; 597 bits = <0 3>; 598 }; 599 }; 600 601 rcc: clock-controller@44200000 { 602 compatible = "st,stm32mp25-rcc"; 603 reg = <0x44200000 0x10000>; 604 #clock-cells = <1>; 605 #reset-cells = <1>; 606 clocks = <&scmi_clk CK_SCMI_HSE>, 607 <&scmi_clk CK_SCMI_HSI>, 608 <&scmi_clk CK_SCMI_MSI>, 609 <&scmi_clk CK_SCMI_LSE>, 610 <&scmi_clk CK_SCMI_LSI>, 611 <&scmi_clk CK_SCMI_HSE_DIV2>, 612 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 613 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 614 <&scmi_clk CK_SCMI_ICN_SDMMC>, 615 <&scmi_clk CK_SCMI_ICN_DDR>, 616 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 617 <&scmi_clk CK_SCMI_ICN_HSL>, 618 <&scmi_clk CK_SCMI_ICN_NIC>, 619 <&scmi_clk CK_SCMI_ICN_VID>, 620 <&scmi_clk CK_SCMI_FLEXGEN_07>, 621 <&scmi_clk CK_SCMI_FLEXGEN_08>, 622 <&scmi_clk CK_SCMI_FLEXGEN_09>, 623 <&scmi_clk CK_SCMI_FLEXGEN_10>, 624 <&scmi_clk CK_SCMI_FLEXGEN_11>, 625 <&scmi_clk CK_SCMI_FLEXGEN_12>, 626 <&scmi_clk CK_SCMI_FLEXGEN_13>, 627 <&scmi_clk CK_SCMI_FLEXGEN_14>, 628 <&scmi_clk CK_SCMI_FLEXGEN_15>, 629 <&scmi_clk CK_SCMI_FLEXGEN_16>, 630 <&scmi_clk CK_SCMI_FLEXGEN_17>, 631 <&scmi_clk CK_SCMI_FLEXGEN_18>, 632 <&scmi_clk CK_SCMI_FLEXGEN_19>, 633 <&scmi_clk CK_SCMI_FLEXGEN_20>, 634 <&scmi_clk CK_SCMI_FLEXGEN_21>, 635 <&scmi_clk CK_SCMI_FLEXGEN_22>, 636 <&scmi_clk CK_SCMI_FLEXGEN_23>, 637 <&scmi_clk CK_SCMI_FLEXGEN_24>, 638 <&scmi_clk CK_SCMI_FLEXGEN_25>, 639 <&scmi_clk CK_SCMI_FLEXGEN_26>, 640 <&scmi_clk CK_SCMI_FLEXGEN_27>, 641 <&scmi_clk CK_SCMI_FLEXGEN_28>, 642 <&scmi_clk CK_SCMI_FLEXGEN_29>, 643 <&scmi_clk CK_SCMI_FLEXGEN_30>, 644 <&scmi_clk CK_SCMI_FLEXGEN_31>, 645 <&scmi_clk CK_SCMI_FLEXGEN_32>, 646 <&scmi_clk CK_SCMI_FLEXGEN_33>, 647 <&scmi_clk CK_SCMI_FLEXGEN_34>, 648 <&scmi_clk CK_SCMI_FLEXGEN_35>, 649 <&scmi_clk CK_SCMI_FLEXGEN_36>, 650 <&scmi_clk CK_SCMI_FLEXGEN_37>, 651 <&scmi_clk CK_SCMI_FLEXGEN_38>, 652 <&scmi_clk CK_SCMI_FLEXGEN_39>, 653 <&scmi_clk CK_SCMI_FLEXGEN_40>, 654 <&scmi_clk CK_SCMI_FLEXGEN_41>, 655 <&scmi_clk CK_SCMI_FLEXGEN_42>, 656 <&scmi_clk CK_SCMI_FLEXGEN_43>, 657 <&scmi_clk CK_SCMI_FLEXGEN_44>, 658 <&scmi_clk CK_SCMI_FLEXGEN_45>, 659 <&scmi_clk CK_SCMI_FLEXGEN_46>, 660 <&scmi_clk CK_SCMI_FLEXGEN_47>, 661 <&scmi_clk CK_SCMI_FLEXGEN_48>, 662 <&scmi_clk CK_SCMI_FLEXGEN_49>, 663 <&scmi_clk CK_SCMI_FLEXGEN_50>, 664 <&scmi_clk CK_SCMI_FLEXGEN_51>, 665 <&scmi_clk CK_SCMI_FLEXGEN_52>, 666 <&scmi_clk CK_SCMI_FLEXGEN_53>, 667 <&scmi_clk CK_SCMI_FLEXGEN_54>, 668 <&scmi_clk CK_SCMI_FLEXGEN_55>, 669 <&scmi_clk CK_SCMI_FLEXGEN_56>, 670 <&scmi_clk CK_SCMI_FLEXGEN_57>, 671 <&scmi_clk CK_SCMI_FLEXGEN_58>, 672 <&scmi_clk CK_SCMI_FLEXGEN_59>, 673 <&scmi_clk CK_SCMI_FLEXGEN_60>, 674 <&scmi_clk CK_SCMI_FLEXGEN_61>, 675 <&scmi_clk CK_SCMI_FLEXGEN_62>, 676 <&scmi_clk CK_SCMI_FLEXGEN_63>, 677 <&scmi_clk CK_SCMI_ICN_APB1>, 678 <&scmi_clk CK_SCMI_ICN_APB2>, 679 <&scmi_clk CK_SCMI_ICN_APB3>, 680 <&scmi_clk CK_SCMI_ICN_APB4>, 681 <&scmi_clk CK_SCMI_ICN_APBDBG>, 682 <&scmi_clk CK_SCMI_TIMG1>, 683 <&scmi_clk CK_SCMI_TIMG2>, 684 <&scmi_clk CK_SCMI_PLL3>, 685 <&clk_dsi_txbyte>; 686 access-controllers = <&rifsc 156>; 687 }; 688 689 exti1: interrupt-controller@44220000 { 690 compatible = "st,stm32mp1-exti", "syscon"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 reg = <0x44220000 0x400>; 694 interrupts-extended = 695 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 696 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 697 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 698 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 699 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 700 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 701 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 702 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 703 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 704 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 705 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 706 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 707 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 708 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 709 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 710 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 711 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 712 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 713 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 714 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 715 <0>, /* EXTI_20 */ 716 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 717 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 718 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 719 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 720 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 721 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 722 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 723 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 724 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 725 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 726 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 727 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 728 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 729 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 730 <0>, 731 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 732 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 733 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 734 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 735 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 736 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 737 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 738 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 739 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 740 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 741 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 742 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 743 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 744 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 745 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 746 <0>, 747 <0>, 748 <0>, 749 <0>, 750 <0>, 751 <0>, 752 <0>, 753 <0>, 754 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 755 <0>, /* EXTI_60 */ 756 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 757 <0>, 758 <0>, 759 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 760 <0>, 761 <0>, 762 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 763 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 764 <0>, 765 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 766 <0>, 767 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 768 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 769 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 770 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 771 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 772 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 773 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 774 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 775 <0>, /* EXTI_80 */ 776 <0>, 777 <0>, 778 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 779 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 780 }; 781 782 syscfg: syscon@44230000 { 783 compatible = "st,stm32mp25-syscfg", "syscon"; 784 reg = <0x44230000 0x10000>; 785 }; 786 787 pinctrl: pinctrl@44240000 { 788 #address-cells = <1>; 789 #size-cells = <1>; 790 compatible = "st,stm32mp257-pinctrl"; 791 ranges = <0 0x44240000 0xa0400>; 792 interrupt-parent = <&exti1>; 793 st,syscfg = <&exti1 0x60 0xff>; 794 pins-are-numbered; 795 796 gpioa: gpio@44240000 { 797 gpio-controller; 798 #gpio-cells = <2>; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 reg = <0x0 0x400>; 802 clocks = <&scmi_clk CK_SCMI_GPIOA>; 803 st,bank-name = "GPIOA"; 804 status = "disabled"; 805 }; 806 807 gpiob: gpio@44250000 { 808 gpio-controller; 809 #gpio-cells = <2>; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 reg = <0x10000 0x400>; 813 clocks = <&scmi_clk CK_SCMI_GPIOB>; 814 st,bank-name = "GPIOB"; 815 status = "disabled"; 816 }; 817 818 gpioc: gpio@44260000 { 819 gpio-controller; 820 #gpio-cells = <2>; 821 interrupt-controller; 822 #interrupt-cells = <2>; 823 reg = <0x20000 0x400>; 824 clocks = <&scmi_clk CK_SCMI_GPIOC>; 825 st,bank-name = "GPIOC"; 826 status = "disabled"; 827 }; 828 829 gpiod: gpio@44270000 { 830 gpio-controller; 831 #gpio-cells = <2>; 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 reg = <0x30000 0x400>; 835 clocks = <&scmi_clk CK_SCMI_GPIOD>; 836 st,bank-name = "GPIOD"; 837 status = "disabled"; 838 }; 839 840 gpioe: gpio@44280000 { 841 gpio-controller; 842 #gpio-cells = <2>; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 reg = <0x40000 0x400>; 846 clocks = <&scmi_clk CK_SCMI_GPIOE>; 847 st,bank-name = "GPIOE"; 848 status = "disabled"; 849 }; 850 851 gpiof: gpio@44290000 { 852 gpio-controller; 853 #gpio-cells = <2>; 854 interrupt-controller; 855 #interrupt-cells = <2>; 856 reg = <0x50000 0x400>; 857 clocks = <&scmi_clk CK_SCMI_GPIOF>; 858 st,bank-name = "GPIOF"; 859 status = "disabled"; 860 }; 861 862 gpiog: gpio@442a0000 { 863 gpio-controller; 864 #gpio-cells = <2>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 reg = <0x60000 0x400>; 868 clocks = <&scmi_clk CK_SCMI_GPIOG>; 869 st,bank-name = "GPIOG"; 870 status = "disabled"; 871 }; 872 873 gpioh: gpio@442b0000 { 874 gpio-controller; 875 #gpio-cells = <2>; 876 interrupt-controller; 877 #interrupt-cells = <2>; 878 reg = <0x70000 0x400>; 879 clocks = <&scmi_clk CK_SCMI_GPIOH>; 880 st,bank-name = "GPIOH"; 881 status = "disabled"; 882 }; 883 884 gpioi: gpio@442c0000 { 885 gpio-controller; 886 #gpio-cells = <2>; 887 interrupt-controller; 888 #interrupt-cells = <2>; 889 reg = <0x80000 0x400>; 890 clocks = <&scmi_clk CK_SCMI_GPIOI>; 891 st,bank-name = "GPIOI"; 892 status = "disabled"; 893 }; 894 895 gpioj: gpio@442d0000 { 896 gpio-controller; 897 #gpio-cells = <2>; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 reg = <0x90000 0x400>; 901 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 902 st,bank-name = "GPIOJ"; 903 status = "disabled"; 904 }; 905 906 gpiok: gpio@442e0000 { 907 gpio-controller; 908 #gpio-cells = <2>; 909 interrupt-controller; 910 #interrupt-cells = <2>; 911 reg = <0xa0000 0x400>; 912 clocks = <&scmi_clk CK_SCMI_GPIOK>; 913 st,bank-name = "GPIOK"; 914 status = "disabled"; 915 }; 916 }; 917 918 pinctrl_z: pinctrl@46200000 { 919 #address-cells = <1>; 920 #size-cells = <1>; 921 compatible = "st,stm32mp257-z-pinctrl"; 922 ranges = <0 0x46200000 0x400>; 923 interrupt-parent = <&exti1>; 924 st,syscfg = <&exti1 0x60 0xff>; 925 pins-are-numbered; 926 927 gpioz: gpio@46200000 { 928 gpio-controller; 929 #gpio-cells = <2>; 930 interrupt-controller; 931 #interrupt-cells = <2>; 932 reg = <0 0x400>; 933 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 934 st,bank-name = "GPIOZ"; 935 st,bank-ioport = <11>; 936 status = "disabled"; 937 }; 938 939 }; 940 941 exti2: interrupt-controller@46230000 { 942 compatible = "st,stm32mp1-exti", "syscon"; 943 interrupt-controller; 944 #interrupt-cells = <2>; 945 reg = <0x46230000 0x400>; 946 interrupts-extended = 947 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 948 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 949 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 950 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 951 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 952 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 953 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 954 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 955 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 956 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 957 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 958 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 959 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 960 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 961 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 962 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 963 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 964 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 965 <0>, 966 <0>, 967 <0>, /* EXTI_20 */ 968 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 969 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 970 <0>, 971 <0>, 972 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 973 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 974 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 975 <0>, 976 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 977 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 978 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 979 <0>, 980 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 981 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 982 <0>, 983 <0>, 984 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 985 <0>, 986 <0>, 987 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 988 <0>, 989 <0>, 990 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 991 <0>, 992 <0>, 993 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 994 <0>, 995 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 996 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 997 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 998 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 999 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1000 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1001 <0>, 1002 <0>, 1003 <0>, 1004 <0>, 1005 <0>, 1006 <0>, 1007 <0>, /* EXTI_60 */ 1008 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1009 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1010 <0>, 1011 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1012 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1013 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1014 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1015 <0>, 1016 <0>, 1017 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1018 }; 1019 }; 1020}; 1021