1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_hdmi_state_helper.h>
36 #include <drm/display/drm_scdc_helper.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_drv.h>
39 #include <drm/drm_edid.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_simple_kms_helper.h>
42 #include <linux/clk.h>
43 #include <linux/component.h>
44 #include <linux/gpio/consumer.h>
45 #include <linux/i2c.h>
46 #include <linux/of.h>
47 #include <linux/of_address.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/rational.h>
50 #include <linux/reset.h>
51 #include <sound/dmaengine_pcm.h>
52 #include <sound/hdmi-codec.h>
53 #include <sound/pcm_drm_eld.h>
54 #include <sound/pcm_params.h>
55 #include <sound/soc.h>
56 #include "media/cec.h"
57 #include "vc4_drv.h"
58 #include "vc4_hdmi.h"
59 #include "vc4_hdmi_regs.h"
60 #include "vc4_regs.h"
61
62 #define VC5_HDMI_HORZA_HFP_SHIFT 16
63 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
64 #define VC5_HDMI_HORZA_VPOS BIT(15)
65 #define VC5_HDMI_HORZA_HPOS BIT(14)
66 #define VC5_HDMI_HORZA_HAP_SHIFT 0
67 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68
69 #define VC5_HDMI_HORZB_HBP_SHIFT 16
70 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
71 #define VC5_HDMI_HORZB_HSP_SHIFT 0
72 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73
74 #define VC5_HDMI_VERTA_VSP_SHIFT 24
75 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
76 #define VC5_HDMI_VERTA_VFP_SHIFT 16
77 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
78 #define VC5_HDMI_VERTA_VAL_SHIFT 0
79 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80
81 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
82 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83
84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
88
89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
90
91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
93
94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
96
97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
98
99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
101
102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
105
106 # define VC4_HD_M_SW_RST BIT(2)
107 # define VC4_HD_M_ENABLE BIT(0)
108
109 #define HSM_MIN_CLOCK_FREQ 120000000
110 #define CEC_CLOCK_FREQ 40000
111
112 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
113
vc4_hdmi_supports_scrambling(struct vc4_hdmi * vc4_hdmi)114 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
115 {
116 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
117
118 lockdep_assert_held(&vc4_hdmi->mutex);
119
120 if (!display->is_hdmi)
121 return false;
122
123 if (!display->hdmi.scdc.supported ||
124 !display->hdmi.scdc.scrambling.supported)
125 return false;
126
127 return true;
128 }
129
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode,unsigned int bpc,enum hdmi_colorspace fmt)130 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
131 unsigned int bpc,
132 enum hdmi_colorspace fmt)
133 {
134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
135
136 return clock > HDMI_14_MAX_TMDS_CLK;
137 }
138
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
140 {
141 struct drm_debugfs_entry *entry = m->private;
142 struct vc4_hdmi *vc4_hdmi = entry->file.data;
143 struct drm_device *drm = vc4_hdmi->connector.dev;
144 struct drm_printer p = drm_seq_file_printer(m);
145 int idx;
146
147 if (!drm_dev_enter(drm, &idx))
148 return -ENODEV;
149
150 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
151
152 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
153 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
154 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
155 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
156 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
157 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
158 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
159 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
160
161 pm_runtime_put(&vc4_hdmi->pdev->dev);
162
163 drm_dev_exit(idx);
164
165 return 0;
166 }
167
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)168 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
169 {
170 struct drm_device *drm = vc4_hdmi->connector.dev;
171 unsigned long flags;
172 int idx;
173
174 /*
175 * We can be called by our bind callback, when the
176 * connector->dev pointer might not be initialised yet.
177 */
178 if (drm && !drm_dev_enter(drm, &idx))
179 return;
180
181 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
182
183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
184 udelay(1);
185 HDMI_WRITE(HDMI_M_CTL, 0);
186
187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
188
189 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
190 VC4_HDMI_SW_RESET_HDMI |
191 VC4_HDMI_SW_RESET_FORMAT_DETECT);
192
193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
194
195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
196
197 if (drm)
198 drm_dev_exit(idx);
199 }
200
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)201 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
202 {
203 struct drm_device *drm = vc4_hdmi->connector.dev;
204 unsigned long flags;
205 int idx;
206
207 /*
208 * We can be called by our bind callback, when the
209 * connector->dev pointer might not be initialised yet.
210 */
211 if (drm && !drm_dev_enter(drm, &idx))
212 return;
213
214 reset_control_reset(vc4_hdmi->reset);
215
216 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
217
218 HDMI_WRITE(HDMI_DVP_CTL, 0);
219
220 HDMI_WRITE(HDMI_CLOCK_STOP,
221 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
222
223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
224
225 if (drm)
226 drm_dev_exit(idx);
227 }
228
229 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)230 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
231 {
232 struct drm_device *drm = vc4_hdmi->connector.dev;
233 unsigned long cec_rate;
234 unsigned long flags;
235 u16 clk_cnt;
236 u32 value;
237 int idx;
238
239 /*
240 * This function is called by our runtime_resume implementation
241 * and thus at bind time, when we haven't registered our
242 * connector yet and thus don't have a pointer to the DRM
243 * device.
244 */
245 if (drm && !drm_dev_enter(drm, &idx))
246 return;
247
248 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
249
250 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
251
252 value = HDMI_READ(HDMI_CEC_CNTRL_1);
253 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
254
255 /*
256 * Set the clock divider: the hsm_clock rate and this divider
257 * setting will give a 40 kHz CEC clock.
258 */
259 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
260 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
261 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
262
263 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
264
265 if (drm)
266 drm_dev_exit(idx);
267 }
268 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)269 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
270 #endif
271
reset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)272 static int reset_pipe(struct drm_crtc *crtc,
273 struct drm_modeset_acquire_ctx *ctx)
274 {
275 struct drm_atomic_state *state;
276 struct drm_crtc_state *crtc_state;
277 int ret;
278
279 state = drm_atomic_state_alloc(crtc->dev);
280 if (!state)
281 return -ENOMEM;
282
283 state->acquire_ctx = ctx;
284
285 crtc_state = drm_atomic_get_crtc_state(state, crtc);
286 if (IS_ERR(crtc_state)) {
287 ret = PTR_ERR(crtc_state);
288 goto out;
289 }
290
291 crtc_state->connectors_changed = true;
292
293 ret = drm_atomic_commit(state);
294 out:
295 drm_atomic_state_put(state);
296
297 return ret;
298 }
299
vc4_hdmi_reset_link(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx)300 static int vc4_hdmi_reset_link(struct drm_connector *connector,
301 struct drm_modeset_acquire_ctx *ctx)
302 {
303 struct drm_device *drm;
304 struct vc4_hdmi *vc4_hdmi;
305 struct drm_connector_state *conn_state;
306 struct drm_crtc_state *crtc_state;
307 struct drm_crtc *crtc;
308 bool scrambling_needed;
309 u8 config;
310 int ret;
311
312 if (!connector)
313 return 0;
314
315 drm = connector->dev;
316 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
317 if (ret)
318 return ret;
319
320 conn_state = connector->state;
321 crtc = conn_state->crtc;
322 if (!crtc)
323 return 0;
324
325 ret = drm_modeset_lock(&crtc->mutex, ctx);
326 if (ret)
327 return ret;
328
329 crtc_state = crtc->state;
330 if (!crtc_state->active)
331 return 0;
332
333 vc4_hdmi = connector_to_vc4_hdmi(connector);
334 mutex_lock(&vc4_hdmi->mutex);
335
336 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
337 mutex_unlock(&vc4_hdmi->mutex);
338 return 0;
339 }
340
341 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
342 vc4_hdmi->output_bpc,
343 vc4_hdmi->output_format);
344 if (!scrambling_needed) {
345 mutex_unlock(&vc4_hdmi->mutex);
346 return 0;
347 }
348
349 if (conn_state->commit &&
350 !try_wait_for_completion(&conn_state->commit->hw_done)) {
351 mutex_unlock(&vc4_hdmi->mutex);
352 return 0;
353 }
354
355 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
356 if (ret < 0) {
357 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
358 mutex_unlock(&vc4_hdmi->mutex);
359 return 0;
360 }
361
362 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
363 mutex_unlock(&vc4_hdmi->mutex);
364 return 0;
365 }
366
367 mutex_unlock(&vc4_hdmi->mutex);
368
369 /*
370 * HDMI 2.0 says that one should not send scrambled data
371 * prior to configuring the sink scrambling, and that
372 * TMDS clock/data transmission should be suspended when
373 * changing the TMDS clock rate in the sink. So let's
374 * just do a full modeset here, even though some sinks
375 * would be perfectly happy if were to just reconfigure
376 * the SCDC settings on the fly.
377 */
378 return reset_pipe(crtc, ctx);
379 }
380
vc4_hdmi_handle_hotplug(struct vc4_hdmi * vc4_hdmi,struct drm_modeset_acquire_ctx * ctx,enum drm_connector_status status)381 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
382 struct drm_modeset_acquire_ctx *ctx,
383 enum drm_connector_status status)
384 {
385 struct drm_connector *connector = &vc4_hdmi->connector;
386 const struct drm_edid *drm_edid;
387 int ret;
388
389 /*
390 * NOTE: This function should really be called with vc4_hdmi->mutex
391 * held, but doing so results in reentrancy issues since
392 * cec_s_phys_addr() might call .adap_enable, which leads to that
393 * funtion being called with our mutex held.
394 *
395 * A similar situation occurs with vc4_hdmi_reset_link() that
396 * will call into our KMS hooks if the scrambling was enabled.
397 *
398 * Concurrency isn't an issue at the moment since we don't share
399 * any state with any of the other frameworks so we can ignore
400 * the lock for now.
401 */
402
403 if (status == connector_status_disconnected) {
404 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
405 return;
406 }
407
408 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
409
410 drm_edid_connector_update(connector, drm_edid);
411 cec_s_phys_addr(vc4_hdmi->cec_adap,
412 connector->display_info.source_physical_address, false);
413
414 if (!drm_edid)
415 return;
416
417 drm_edid_free(drm_edid);
418
419 for (;;) {
420 ret = vc4_hdmi_reset_link(connector, ctx);
421 if (ret == -EDEADLK) {
422 drm_modeset_backoff(ctx);
423 continue;
424 }
425
426 break;
427 }
428 }
429
vc4_hdmi_connector_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)430 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
431 struct drm_modeset_acquire_ctx *ctx,
432 bool force)
433 {
434 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
435 enum drm_connector_status status = connector_status_disconnected;
436 int ret;
437
438 /*
439 * NOTE: This function should really take vc4_hdmi->mutex, but
440 * doing so results in reentrancy issues since
441 * vc4_hdmi_handle_hotplug() can call into other functions that
442 * would take the mutex while it's held here.
443 *
444 * Concurrency isn't an issue at the moment since we don't share
445 * any state with any of the other frameworks so we can ignore
446 * the lock for now.
447 */
448
449 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
450 if (ret) {
451 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
452 ret);
453 return connector_status_unknown;
454 }
455
456 if (vc4_hdmi->hpd_gpio) {
457 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
458 status = connector_status_connected;
459 } else {
460 if (vc4_hdmi->variant->hp_detect &&
461 vc4_hdmi->variant->hp_detect(vc4_hdmi))
462 status = connector_status_connected;
463 }
464
465 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
466 pm_runtime_put(&vc4_hdmi->pdev->dev);
467
468 return status;
469 }
470
vc4_hdmi_connector_get_modes(struct drm_connector * connector)471 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
472 {
473 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
474 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
475 const struct drm_edid *drm_edid;
476 int ret = 0;
477
478 /*
479 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
480 * results in reentrancy issues since cec_s_phys_addr() might call
481 * .adap_enable, which leads to that funtion being called with our mutex
482 * held.
483 *
484 * Concurrency isn't an issue at the moment since we don't share
485 * any state with any of the other frameworks so we can ignore
486 * the lock for now.
487 */
488
489 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
490 drm_edid_connector_update(connector, drm_edid);
491 cec_s_phys_addr(vc4_hdmi->cec_adap,
492 connector->display_info.source_physical_address, false);
493 if (!drm_edid)
494 return 0;
495
496 ret = drm_edid_connector_add_modes(connector);
497 drm_edid_free(drm_edid);
498
499 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
500 struct drm_device *drm = connector->dev;
501 const struct drm_display_mode *mode;
502
503 list_for_each_entry(mode, &connector->probed_modes, head) {
504 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
505 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
506 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
507 }
508 }
509 }
510
511 return ret;
512 }
513
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)514 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
515 struct drm_atomic_state *state)
516 {
517 struct drm_connector_state *old_state =
518 drm_atomic_get_old_connector_state(state, connector);
519 struct drm_connector_state *new_state =
520 drm_atomic_get_new_connector_state(state, connector);
521 struct drm_crtc *crtc = new_state->crtc;
522
523 if (!crtc)
524 return 0;
525
526 if (old_state->tv.margins.left != new_state->tv.margins.left ||
527 old_state->tv.margins.right != new_state->tv.margins.right ||
528 old_state->tv.margins.top != new_state->tv.margins.top ||
529 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
530 struct drm_crtc_state *crtc_state;
531 int ret;
532
533 crtc_state = drm_atomic_get_crtc_state(state, crtc);
534 if (IS_ERR(crtc_state))
535 return PTR_ERR(crtc_state);
536
537 /*
538 * Strictly speaking, we should be calling
539 * drm_atomic_helper_check_planes() after our call to
540 * drm_atomic_add_affected_planes(). However, the
541 * connector atomic_check is called as part of
542 * drm_atomic_helper_check_modeset() that already
543 * happens before a call to
544 * drm_atomic_helper_check_planes() in
545 * drm_atomic_helper_check().
546 */
547 ret = drm_atomic_add_affected_planes(state, crtc);
548 if (ret)
549 return ret;
550 }
551
552 if (old_state->colorspace != new_state->colorspace) {
553 struct drm_crtc_state *crtc_state;
554
555 crtc_state = drm_atomic_get_crtc_state(state, crtc);
556 if (IS_ERR(crtc_state))
557 return PTR_ERR(crtc_state);
558
559 crtc_state->mode_changed = true;
560 }
561
562 return drm_atomic_helper_connector_hdmi_check(connector, state);
563 }
564
vc4_hdmi_connector_reset(struct drm_connector * connector)565 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
566 {
567 drm_atomic_helper_connector_reset(connector);
568 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
569 drm_atomic_helper_connector_tv_margins_reset(connector);
570 }
571
572 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
573 .fill_modes = drm_helper_probe_single_connector_modes,
574 .reset = vc4_hdmi_connector_reset,
575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
577 };
578
579 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
580 .detect_ctx = vc4_hdmi_connector_detect_ctx,
581 .get_modes = vc4_hdmi_connector_get_modes,
582 .atomic_check = vc4_hdmi_connector_atomic_check,
583 };
584
585 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
586
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)587 static int vc4_hdmi_connector_init(struct drm_device *dev,
588 struct vc4_hdmi *vc4_hdmi)
589 {
590 struct drm_connector *connector = &vc4_hdmi->connector;
591 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
592 unsigned int max_bpc = 8;
593 int ret;
594
595 if (vc4_hdmi->variant->supports_hdr)
596 max_bpc = 12;
597
598 ret = drmm_connector_hdmi_init(dev, connector,
599 "Broadcom", "Videocore",
600 &vc4_hdmi_connector_funcs,
601 &vc4_hdmi_hdmi_connector_funcs,
602 DRM_MODE_CONNECTOR_HDMIA,
603 vc4_hdmi->ddc,
604 BIT(HDMI_COLORSPACE_RGB) |
605 BIT(HDMI_COLORSPACE_YUV422) |
606 BIT(HDMI_COLORSPACE_YUV444),
607 max_bpc);
608 if (ret)
609 return ret;
610
611 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
612
613 /*
614 * Some of the properties below require access to state, like bpc.
615 * Allocate some default initial connector state with our reset helper.
616 */
617 if (connector->funcs->reset)
618 connector->funcs->reset(connector);
619
620 /* Create and attach TV margin props to this connector. */
621 ret = drm_mode_create_tv_margin_properties(dev);
622 if (ret)
623 return ret;
624
625 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
626 if (ret)
627 return ret;
628
629 drm_connector_attach_colorspace_property(connector);
630 drm_connector_attach_tv_margin_properties(connector);
631
632 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
633 DRM_CONNECTOR_POLL_DISCONNECT);
634
635 connector->interlace_allowed = 1;
636 connector->doublescan_allowed = 0;
637 connector->stereo_allowed = 1;
638
639 ret = drm_connector_attach_broadcast_rgb_property(connector);
640 if (ret)
641 return ret;
642
643 drm_connector_attach_encoder(connector, encoder);
644
645 return 0;
646 }
647
vc4_hdmi_stop_packet(struct vc4_hdmi * vc4_hdmi,enum hdmi_infoframe_type type,bool poll)648 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
649 enum hdmi_infoframe_type type,
650 bool poll)
651 {
652 struct drm_device *drm = vc4_hdmi->connector.dev;
653 u32 packet_id = type - 0x80;
654 unsigned long flags;
655 int ret = 0;
656 int idx;
657
658 if (!drm_dev_enter(drm, &idx))
659 return -ENODEV;
660
661 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
662 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
663 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
664 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
665
666 if (poll) {
667 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
668 BIT(packet_id)), 100);
669 }
670
671 drm_dev_exit(idx);
672 return ret;
673 }
674
vc4_hdmi_write_infoframe(struct drm_connector * connector,enum hdmi_infoframe_type type,const u8 * infoframe,size_t len)675 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
676 enum hdmi_infoframe_type type,
677 const u8 *infoframe, size_t len)
678 {
679 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
680 struct drm_device *drm = connector->dev;
681 u32 packet_id = type - 0x80;
682 const struct vc4_hdmi_register *ram_packet_start =
683 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
684 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
685 u32 packet_reg_next = ram_packet_start->offset +
686 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
687 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
688 ram_packet_start->reg);
689 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
690 unsigned long flags;
691 ssize_t i;
692 int ret;
693 int idx;
694
695 if (!drm_dev_enter(drm, &idx))
696 return 0;
697
698 if (len > sizeof(buffer)) {
699 ret = -ENOMEM;
700 goto out;
701 }
702
703 memcpy(buffer, infoframe, len);
704
705 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
706 VC4_HDMI_RAM_PACKET_ENABLE),
707 "Packet RAM has to be on to store the packet.");
708
709 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
710 if (ret) {
711 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
712 goto out;
713 }
714
715 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
716
717 for (i = 0; i < len; i += 7) {
718 writel(buffer[i + 0] << 0 |
719 buffer[i + 1] << 8 |
720 buffer[i + 2] << 16,
721 base + packet_reg);
722 packet_reg += 4;
723
724 writel(buffer[i + 3] << 0 |
725 buffer[i + 4] << 8 |
726 buffer[i + 5] << 16 |
727 buffer[i + 6] << 24,
728 base + packet_reg);
729 packet_reg += 4;
730 }
731
732 /*
733 * clear remainder of packet ram as it's included in the
734 * infoframe and triggers a checksum error on hdmi analyser
735 */
736 for (; packet_reg < packet_reg_next; packet_reg += 4)
737 writel(0, base + packet_reg);
738
739 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
740 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
741
742 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
743
744 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
745 BIT(packet_id)), 100);
746 if (ret)
747 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
748
749 out:
750 drm_dev_exit(idx);
751 return ret;
752 }
753
754 #define SCRAMBLING_POLLING_DELAY_MS 1000
755
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)756 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
757 {
758 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
759 struct drm_connector *connector = &vc4_hdmi->connector;
760 struct drm_device *drm = connector->dev;
761 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
762 unsigned long flags;
763 int idx;
764
765 lockdep_assert_held(&vc4_hdmi->mutex);
766
767 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
768 return;
769
770 if (!vc4_hdmi_mode_needs_scrambling(mode,
771 vc4_hdmi->output_bpc,
772 vc4_hdmi->output_format))
773 return;
774
775 if (!drm_dev_enter(drm, &idx))
776 return;
777
778 drm_scdc_set_high_tmds_clock_ratio(connector, true);
779 drm_scdc_set_scrambling(connector, true);
780
781 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
782 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
783 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
784 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
785
786 drm_dev_exit(idx);
787
788 vc4_hdmi->scdc_enabled = true;
789
790 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
791 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
792 }
793
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)794 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
795 {
796 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
797 struct drm_connector *connector = &vc4_hdmi->connector;
798 struct drm_device *drm = connector->dev;
799 unsigned long flags;
800 int idx;
801
802 lockdep_assert_held(&vc4_hdmi->mutex);
803
804 if (!vc4_hdmi->scdc_enabled)
805 return;
806
807 vc4_hdmi->scdc_enabled = false;
808
809 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
810 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
811
812 if (!drm_dev_enter(drm, &idx))
813 return;
814
815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
816 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
817 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
818 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
819
820 drm_scdc_set_scrambling(connector, false);
821 drm_scdc_set_high_tmds_clock_ratio(connector, false);
822
823 drm_dev_exit(idx);
824 }
825
vc4_hdmi_scrambling_wq(struct work_struct * work)826 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
827 {
828 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
829 struct vc4_hdmi,
830 scrambling_work);
831 struct drm_connector *connector = &vc4_hdmi->connector;
832
833 if (drm_scdc_get_scrambling_status(connector))
834 return;
835
836 drm_scdc_set_high_tmds_clock_ratio(connector, true);
837 drm_scdc_set_scrambling(connector, true);
838
839 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
840 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
841 }
842
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)843 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
844 struct drm_atomic_state *state)
845 {
846 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
847 struct drm_device *drm = vc4_hdmi->connector.dev;
848 unsigned long flags;
849 int idx;
850
851 mutex_lock(&vc4_hdmi->mutex);
852
853 vc4_hdmi->packet_ram_enabled = false;
854
855 if (!drm_dev_enter(drm, &idx))
856 goto out;
857
858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
859
860 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
861
862 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
863
864 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
865
866 mdelay(1);
867
868 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
869 HDMI_WRITE(HDMI_VID_CTL,
870 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
872
873 vc4_hdmi_disable_scrambling(encoder);
874
875 drm_dev_exit(idx);
876
877 out:
878 mutex_unlock(&vc4_hdmi->mutex);
879 }
880
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)881 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
882 struct drm_atomic_state *state)
883 {
884 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
885 struct drm_device *drm = vc4_hdmi->connector.dev;
886 unsigned long flags;
887 int ret;
888 int idx;
889
890 mutex_lock(&vc4_hdmi->mutex);
891
892 if (!drm_dev_enter(drm, &idx))
893 goto out;
894
895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
896 HDMI_WRITE(HDMI_VID_CTL,
897 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
898 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
899
900 if (vc4_hdmi->variant->phy_disable)
901 vc4_hdmi->variant->phy_disable(vc4_hdmi);
902
903 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
904 clk_disable_unprepare(vc4_hdmi->pixel_clock);
905
906 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
907 if (ret < 0)
908 drm_err(drm, "Failed to release power domain: %d\n", ret);
909
910 drm_dev_exit(idx);
911
912 out:
913 mutex_unlock(&vc4_hdmi->mutex);
914 }
915
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)916 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
917 struct drm_connector_state *state,
918 const struct drm_display_mode *mode)
919 {
920 struct drm_device *drm = vc4_hdmi->connector.dev;
921 unsigned long flags;
922 u32 csc_ctl;
923 int idx;
924
925 if (!drm_dev_enter(drm, &idx))
926 return;
927
928 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
929
930 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
931 VC4_HD_CSC_CTL_ORDER);
932
933 if (state->hdmi.is_limited_range) {
934 /* CEA VICs other than #1 requre limited range RGB
935 * output unless overridden by an AVI infoframe.
936 * Apply a colorspace conversion to squash 0-255 down
937 * to 16-235. The matrix here is:
938 *
939 * [ 0 0 0.8594 16]
940 * [ 0 0.8594 0 16]
941 * [ 0.8594 0 0 16]
942 * [ 0 0 0 1]
943 */
944 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
945 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
946 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
947 VC4_HD_CSC_CTL_MODE);
948
949 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
950 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
951 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
952 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
953 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
954 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
955 }
956
957 /* The RGB order applies even when CSC is disabled. */
958 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
959
960 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
961
962 drm_dev_exit(idx);
963 }
964
965 /*
966 * Matrices for (internal) RGB to RGB output.
967 *
968 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
969 */
970 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
971 {
972 /*
973 * Full range - unity
974 *
975 * [ 1 0 0 0]
976 * [ 0 1 0 0]
977 * [ 0 0 1 0]
978 */
979 { 0x2000, 0x0000, 0x0000, 0x0000 },
980 { 0x0000, 0x2000, 0x0000, 0x0000 },
981 { 0x0000, 0x0000, 0x2000, 0x0000 },
982 },
983 {
984 /*
985 * Limited range
986 *
987 * CEA VICs other than #1 require limited range RGB
988 * output unless overridden by an AVI infoframe. Apply a
989 * colorspace conversion to squash 0-255 down to 16-235.
990 * The matrix here is:
991 *
992 * [ 0.8594 0 0 16]
993 * [ 0 0.8594 0 16]
994 * [ 0 0 0.8594 16]
995 */
996 { 0x1b80, 0x0000, 0x0000, 0x0400 },
997 { 0x0000, 0x1b80, 0x0000, 0x0400 },
998 { 0x0000, 0x0000, 0x1b80, 0x0400 },
999 },
1000 };
1001
1002 /*
1003 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1004 *
1005 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1006 */
1007 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1008 {
1009 /*
1010 * Full Range
1011 *
1012 * [ 0.299000 0.587000 0.114000 0 ]
1013 * [ -0.168736 -0.331264 0.500000 128 ]
1014 * [ 0.500000 -0.418688 -0.081312 128 ]
1015 */
1016 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1017 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1018 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1019 },
1020 {
1021 /* Limited Range
1022 *
1023 * [ 0.255785 0.502160 0.097523 16 ]
1024 * [ -0.147644 -0.289856 0.437500 128 ]
1025 * [ 0.437500 -0.366352 -0.071148 128 ]
1026 */
1027 { 0x082f, 0x1012, 0x031f, 0x0400 },
1028 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1029 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1030 },
1031 };
1032
1033 /*
1034 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1035 *
1036 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1037 */
1038 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1039 {
1040 /*
1041 * Full Range
1042 *
1043 * [ 0.212600 0.715200 0.072200 0 ]
1044 * [ -0.114572 -0.385428 0.500000 128 ]
1045 * [ 0.500000 -0.454153 -0.045847 128 ]
1046 */
1047 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1048 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1049 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1050 },
1051 {
1052 /*
1053 * Limited Range
1054 *
1055 * [ 0.181906 0.611804 0.061758 16 ]
1056 * [ -0.100268 -0.337232 0.437500 128 ]
1057 * [ 0.437500 -0.397386 -0.040114 128 ]
1058 */
1059 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1060 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1061 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1062 },
1063 };
1064
1065 /*
1066 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1067 *
1068 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1069 */
1070 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1071 {
1072 /*
1073 * Full Range
1074 *
1075 * [ 0.262700 0.678000 0.059300 0 ]
1076 * [ -0.139630 -0.360370 0.500000 128 ]
1077 * [ 0.500000 -0.459786 -0.040214 128 ]
1078 */
1079 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1080 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1081 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1082 },
1083 {
1084 /* Limited Range
1085 *
1086 * [ 0.224732 0.580008 0.050729 16 ]
1087 * [ -0.122176 -0.315324 0.437500 128 ]
1088 * [ 0.437500 -0.402312 -0.035188 128 ]
1089 */
1090 { 0x082f, 0x1012, 0x031f, 0x0400 },
1091 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1092 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1093 },
1094 };
1095
vc5_hdmi_set_csc_coeffs(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1096 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1097 const u16 coeffs[3][4])
1098 {
1099 lockdep_assert_held(&vc4_hdmi->hw_lock);
1100
1101 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1102 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1103 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1104 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1105 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1106 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1107 }
1108
vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1109 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1110 const u16 coeffs[3][4])
1111 {
1112 lockdep_assert_held(&vc4_hdmi->hw_lock);
1113
1114 /* YUV444 needs the CSC matrices using the channels in a different order */
1115 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1116 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1117 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1118 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1119 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1120 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1121 }
1122
1123 static const u16
vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi * vc4_hdmi,u32 colorspace,bool limited)1124 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1125 {
1126 switch (colorspace) {
1127 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1128 case DRM_MODE_COLORIMETRY_XVYCC_601:
1129 case DRM_MODE_COLORIMETRY_SYCC_601:
1130 case DRM_MODE_COLORIMETRY_OPYCC_601:
1131 case DRM_MODE_COLORIMETRY_BT601_YCC:
1132 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1133
1134 default:
1135 case DRM_MODE_COLORIMETRY_NO_DATA:
1136 case DRM_MODE_COLORIMETRY_BT709_YCC:
1137 case DRM_MODE_COLORIMETRY_XVYCC_709:
1138 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1139 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1140 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1141
1142 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1143 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1144 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1145 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1146 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1147 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1148 }
1149 }
1150
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1151 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1152 struct drm_connector_state *state,
1153 const struct drm_display_mode *mode)
1154 {
1155 struct drm_device *drm = vc4_hdmi->connector.dev;
1156 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1157 unsigned long flags;
1158 const u16 (*csc)[4];
1159 u32 if_cfg = 0;
1160 u32 if_xbar = 0x543210;
1161 u32 csc_chan_ctl = 0;
1162 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1163 VC5_MT_CP_CSC_CTL_MODE);
1164 int idx;
1165
1166 if (!drm_dev_enter(drm, &idx))
1167 return;
1168
1169 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1170
1171 switch (state->hdmi.output_format) {
1172 case HDMI_COLORSPACE_YUV444:
1173 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1174
1175 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1176 break;
1177
1178 case HDMI_COLORSPACE_YUV422:
1179 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1180
1181 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1182 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1183 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1184 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1185
1186 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1187 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1188
1189 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1190 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1191
1192 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1193 break;
1194
1195 case HDMI_COLORSPACE_RGB:
1196 if_xbar = 0x354021;
1197
1198 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1199 break;
1200
1201 default:
1202 break;
1203 }
1204
1205 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1206 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1207 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1208 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1209
1210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1211
1212 drm_dev_exit(idx);
1213 }
1214
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1215 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1216 struct drm_connector_state *state,
1217 const struct drm_display_mode *mode)
1218 {
1219 struct drm_device *drm = vc4_hdmi->connector.dev;
1220 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1221 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1222 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1223 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1224 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1225 VC4_HDMI_VERTA_VSP) |
1226 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1227 VC4_HDMI_VERTA_VFP) |
1228 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1229 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1230 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1231 interlaced,
1232 VC4_HDMI_VERTB_VBP));
1233 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1234 VC4_SET_FIELD(mode->crtc_vtotal -
1235 mode->crtc_vsync_end,
1236 VC4_HDMI_VERTB_VBP));
1237 unsigned long flags;
1238 u32 reg;
1239 int idx;
1240
1241 if (!drm_dev_enter(drm, &idx))
1242 return;
1243
1244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1245
1246 HDMI_WRITE(HDMI_HORZA,
1247 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1248 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1249 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1250 VC4_HDMI_HORZA_HAP));
1251
1252 HDMI_WRITE(HDMI_HORZB,
1253 VC4_SET_FIELD((mode->htotal -
1254 mode->hsync_end) * pixel_rep,
1255 VC4_HDMI_HORZB_HBP) |
1256 VC4_SET_FIELD((mode->hsync_end -
1257 mode->hsync_start) * pixel_rep,
1258 VC4_HDMI_HORZB_HSP) |
1259 VC4_SET_FIELD((mode->hsync_start -
1260 mode->hdisplay) * pixel_rep,
1261 VC4_HDMI_HORZB_HFP));
1262
1263 HDMI_WRITE(HDMI_VERTA0, verta);
1264 HDMI_WRITE(HDMI_VERTA1, verta);
1265
1266 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1267 HDMI_WRITE(HDMI_VERTB1, vertb);
1268
1269 reg = HDMI_READ(HDMI_MISC_CONTROL);
1270 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1271 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1272 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1273
1274 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1275
1276 drm_dev_exit(idx);
1277 }
1278
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1279 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1280 struct drm_connector_state *state,
1281 const struct drm_display_mode *mode)
1282 {
1283 struct drm_device *drm = vc4_hdmi->connector.dev;
1284 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1285 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1286 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1287 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1288 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1289 VC5_HDMI_VERTA_VSP) |
1290 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1291 VC5_HDMI_VERTA_VFP) |
1292 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1293 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1294 VC5_HDMI_VERTB_VSPO) |
1295 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1296 interlaced,
1297 VC4_HDMI_VERTB_VBP));
1298 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1299 VC4_SET_FIELD(mode->crtc_vtotal -
1300 mode->crtc_vsync_end,
1301 VC4_HDMI_VERTB_VBP));
1302 unsigned long flags;
1303 unsigned char gcp;
1304 u32 reg;
1305 int idx;
1306
1307 if (!drm_dev_enter(drm, &idx))
1308 return;
1309
1310 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1311
1312 HDMI_WRITE(HDMI_HORZA,
1313 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1314 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1315 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1316 VC5_HDMI_HORZA_HAP) |
1317 VC4_SET_FIELD((mode->hsync_start -
1318 mode->hdisplay) * pixel_rep,
1319 VC5_HDMI_HORZA_HFP));
1320
1321 HDMI_WRITE(HDMI_HORZB,
1322 VC4_SET_FIELD((mode->htotal -
1323 mode->hsync_end) * pixel_rep,
1324 VC5_HDMI_HORZB_HBP) |
1325 VC4_SET_FIELD((mode->hsync_end -
1326 mode->hsync_start) * pixel_rep,
1327 VC5_HDMI_HORZB_HSP));
1328
1329 HDMI_WRITE(HDMI_VERTA0, verta);
1330 HDMI_WRITE(HDMI_VERTA1, verta);
1331
1332 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1333 HDMI_WRITE(HDMI_VERTB1, vertb);
1334
1335 switch (state->hdmi.output_bpc) {
1336 case 12:
1337 gcp = 6;
1338 break;
1339 case 10:
1340 gcp = 5;
1341 break;
1342 case 8:
1343 default:
1344 gcp = 0;
1345 break;
1346 }
1347
1348 /*
1349 * YCC422 is always 36-bit and not considered deep colour so
1350 * doesn't signal in GCP.
1351 */
1352 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1353 gcp = 0;
1354 }
1355
1356 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1357 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1358 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1359 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1360 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1361 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1362
1363 reg = HDMI_READ(HDMI_GCP_WORD_1);
1364 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1365 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1366 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1367 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1368 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1369
1370 reg = HDMI_READ(HDMI_GCP_CONFIG);
1371 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1372 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1373
1374 reg = HDMI_READ(HDMI_MISC_CONTROL);
1375 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1376 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1377 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1378
1379 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1380
1381 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382
1383 drm_dev_exit(idx);
1384 }
1385
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)1386 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1387 {
1388 struct drm_device *drm = vc4_hdmi->connector.dev;
1389 unsigned long flags;
1390 u32 drift;
1391 int ret;
1392 int idx;
1393
1394 if (!drm_dev_enter(drm, &idx))
1395 return;
1396
1397 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1398
1399 drift = HDMI_READ(HDMI_FIFO_CTL);
1400 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1401
1402 HDMI_WRITE(HDMI_FIFO_CTL,
1403 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1404 HDMI_WRITE(HDMI_FIFO_CTL,
1405 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1406
1407 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1408
1409 usleep_range(1000, 1100);
1410
1411 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1412
1413 HDMI_WRITE(HDMI_FIFO_CTL,
1414 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1415 HDMI_WRITE(HDMI_FIFO_CTL,
1416 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1417
1418 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1419
1420 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1421 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1422 WARN_ONCE(ret, "Timeout waiting for "
1423 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1424
1425 drm_dev_exit(idx);
1426 }
1427
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)1428 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1429 struct drm_atomic_state *state)
1430 {
1431 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1432 struct drm_device *drm = vc4_hdmi->connector.dev;
1433 struct drm_connector *connector = &vc4_hdmi->connector;
1434 struct drm_connector_state *conn_state =
1435 drm_atomic_get_new_connector_state(state, connector);
1436 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1437 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1438 unsigned long bvb_rate, hsm_rate;
1439 unsigned long flags;
1440 int ret;
1441 int idx;
1442
1443 mutex_lock(&vc4_hdmi->mutex);
1444
1445 if (!drm_dev_enter(drm, &idx))
1446 goto out;
1447
1448 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1449 if (ret < 0) {
1450 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1451 goto err_dev_exit;
1452 }
1453
1454 /*
1455 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1456 * be faster than pixel clock, infinitesimally faster, tested in
1457 * simulation. Otherwise, exact value is unimportant for HDMI
1458 * operation." This conflicts with bcm2835's vc4 documentation, which
1459 * states HSM's clock has to be at least 108% of the pixel clock.
1460 *
1461 * Real life tests reveal that vc4's firmware statement holds up, and
1462 * users are able to use pixel clocks closer to HSM's, namely for
1463 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1464 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1465 * 162MHz.
1466 *
1467 * Additionally, the AXI clock needs to be at least 25% of
1468 * pixel clock, but HSM ends up being the limiting factor.
1469 */
1470 hsm_rate = max_t(unsigned long,
1471 HSM_MIN_CLOCK_FREQ,
1472 div_u64(tmds_char_rate, 100) * 101);
1473 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1474 if (ret) {
1475 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1476 goto err_put_runtime_pm;
1477 }
1478
1479 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1480 if (ret) {
1481 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1482 goto err_put_runtime_pm;
1483 }
1484
1485 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1486 if (ret) {
1487 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1488 goto err_put_runtime_pm;
1489 }
1490
1491
1492 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1493
1494 if (tmds_char_rate > 297000000)
1495 bvb_rate = 300000000;
1496 else if (tmds_char_rate > 148500000)
1497 bvb_rate = 150000000;
1498 else
1499 bvb_rate = 75000000;
1500
1501 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1502 if (ret) {
1503 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1504 goto err_disable_pixel_clock;
1505 }
1506
1507 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1508 if (ret) {
1509 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1510 goto err_disable_pixel_clock;
1511 }
1512
1513 if (vc4_hdmi->variant->phy_init)
1514 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1515
1516 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1517
1518 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1519 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1520 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1521 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1522
1523 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1524
1525 if (vc4_hdmi->variant->set_timings)
1526 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1527
1528 drm_dev_exit(idx);
1529
1530 mutex_unlock(&vc4_hdmi->mutex);
1531
1532 return;
1533
1534 err_disable_pixel_clock:
1535 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1536 err_put_runtime_pm:
1537 pm_runtime_put(&vc4_hdmi->pdev->dev);
1538 err_dev_exit:
1539 drm_dev_exit(idx);
1540 out:
1541 mutex_unlock(&vc4_hdmi->mutex);
1542 return;
1543 }
1544
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1545 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1546 struct drm_atomic_state *state)
1547 {
1548 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1549 struct drm_device *drm = vc4_hdmi->connector.dev;
1550 struct drm_connector *connector = &vc4_hdmi->connector;
1551 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1552 struct drm_connector_state *conn_state =
1553 drm_atomic_get_new_connector_state(state, connector);
1554 unsigned long flags;
1555 int idx;
1556
1557 mutex_lock(&vc4_hdmi->mutex);
1558
1559 if (!drm_dev_enter(drm, &idx))
1560 goto out;
1561
1562 if (vc4_hdmi->variant->csc_setup)
1563 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1564
1565 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1566 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1567 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1568
1569 drm_dev_exit(idx);
1570
1571 out:
1572 mutex_unlock(&vc4_hdmi->mutex);
1573 }
1574
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1575 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1576 struct drm_atomic_state *state)
1577 {
1578 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1579 struct drm_connector *connector = &vc4_hdmi->connector;
1580 struct drm_device *drm = connector->dev;
1581 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1582 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1583 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1584 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1585 unsigned long flags;
1586 int ret;
1587 int idx;
1588
1589 mutex_lock(&vc4_hdmi->mutex);
1590
1591 if (!drm_dev_enter(drm, &idx))
1592 goto out;
1593
1594 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1595
1596 HDMI_WRITE(HDMI_VID_CTL,
1597 VC4_HD_VID_CTL_ENABLE |
1598 VC4_HD_VID_CTL_CLRRGB |
1599 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1600 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1601 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1602 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1603
1604 HDMI_WRITE(HDMI_VID_CTL,
1605 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1606
1607 if (display->is_hdmi) {
1608 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1609 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1610 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1611
1612 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1613
1614 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1615 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1616 WARN_ONCE(ret, "Timeout waiting for "
1617 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1618 } else {
1619 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1620 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1621 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1622 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1623 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1624 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1625
1626 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1627
1628 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1629 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1630 WARN_ONCE(ret, "Timeout waiting for "
1631 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1632 }
1633
1634 if (display->is_hdmi) {
1635 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1636
1637 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1638 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1639
1640 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1641 VC4_HDMI_RAM_PACKET_ENABLE);
1642
1643 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1644 vc4_hdmi->packet_ram_enabled = true;
1645
1646 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1647 }
1648
1649 vc4_hdmi_recenter_fifo(vc4_hdmi);
1650 vc4_hdmi_enable_scrambling(encoder);
1651
1652 drm_dev_exit(idx);
1653
1654 out:
1655 mutex_unlock(&vc4_hdmi->mutex);
1656 }
1657
vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1658 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1659 struct drm_crtc_state *crtc_state,
1660 struct drm_connector_state *conn_state)
1661 {
1662 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1663
1664 mutex_lock(&vc4_hdmi->mutex);
1665 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1666 &crtc_state->adjusted_mode);
1667 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1668 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1669 mutex_unlock(&vc4_hdmi->mutex);
1670 }
1671
1672 static enum drm_mode_status
vc4_hdmi_connector_clock_valid(const struct drm_connector * connector,const struct drm_display_mode * mode,unsigned long long clock)1673 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1674 const struct drm_display_mode *mode,
1675 unsigned long long clock)
1676 {
1677 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1678 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1679
1680 if (clock > vc4_hdmi->variant->max_pixel_clock)
1681 return MODE_CLOCK_HIGH;
1682
1683 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1684 return MODE_CLOCK_HIGH;
1685
1686 /* 4096x2160@60 is not reliable without overclocking core */
1687 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1688 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1689 drm_mode_vrefresh(mode) >= 50)
1690 return MODE_CLOCK_HIGH;
1691
1692 return MODE_OK;
1693 }
1694
1695 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1696 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1697 .write_infoframe = vc4_hdmi_write_infoframe,
1698 };
1699
1700 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1701 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1702
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1703 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1704 struct drm_crtc_state *crtc_state,
1705 struct drm_connector_state *conn_state)
1706 {
1707 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1708 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1709 unsigned long long tmds_char_rate = mode->clock * 1000;
1710 unsigned long long tmds_bit_rate;
1711
1712 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1713 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1714 /* Only try to fixup DBLCLK modes to get 480i and 576i
1715 * working.
1716 * A generic solution for all modes with odd horizontal
1717 * timing values seems impossible based on trying to
1718 * solve it for 1366x768 monitors.
1719 */
1720 if ((mode->hsync_start - mode->hdisplay) & 1)
1721 mode->hsync_start--;
1722 if ((mode->hsync_end - mode->hsync_start) & 1)
1723 mode->hsync_end--;
1724 }
1725
1726 /* Now check whether we still have odd values remaining */
1727 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1728 (mode->hsync_end % 2) || (mode->htotal % 2))
1729 return -EINVAL;
1730 }
1731
1732 /*
1733 * The 1440p@60 pixel rate is in the same range than the first
1734 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1735 * bandwidth). Slightly lower the frequency to bring it out of
1736 * the WiFi range.
1737 */
1738 tmds_bit_rate = tmds_char_rate * 10;
1739 if (vc4_hdmi->disable_wifi_frequencies &&
1740 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1741 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1742 mode->clock = 238560;
1743 tmds_char_rate = mode->clock * 1000;
1744 }
1745
1746 return 0;
1747 }
1748
1749 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1750 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1751 const struct drm_display_mode *mode)
1752 {
1753 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1754 unsigned long long rate;
1755
1756 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1757 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1758 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1759 (mode->hsync_end % 2) || (mode->htotal % 2)))
1760 return MODE_H_ILLEGAL;
1761
1762 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
1763 return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate);
1764 }
1765
1766 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1767 .atomic_check = vc4_hdmi_encoder_atomic_check,
1768 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1769 .mode_valid = vc4_hdmi_encoder_mode_valid,
1770 };
1771
vc4_hdmi_late_register(struct drm_encoder * encoder)1772 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1773 {
1774 struct drm_device *drm = encoder->dev;
1775 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1776 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1777
1778 drm_debugfs_add_file(drm, variant->debugfs_name,
1779 vc4_hdmi_debugfs_regs, vc4_hdmi);
1780
1781 return 0;
1782 }
1783
1784 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1785 .late_register = vc4_hdmi_late_register,
1786 };
1787
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1788 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1789 {
1790 int i;
1791 u32 channel_map = 0;
1792
1793 for (i = 0; i < 8; i++) {
1794 if (channel_mask & BIT(i))
1795 channel_map |= i << (3 * i);
1796 }
1797 return channel_map;
1798 }
1799
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1800 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1801 {
1802 int i;
1803 u32 channel_map = 0;
1804
1805 for (i = 0; i < 8; i++) {
1806 if (channel_mask & BIT(i))
1807 channel_map |= i << (4 * i);
1808 }
1809 return channel_map;
1810 }
1811
vc5_hdmi_hp_detect(struct vc4_hdmi * vc4_hdmi)1812 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1813 {
1814 struct drm_device *drm = vc4_hdmi->connector.dev;
1815 unsigned long flags;
1816 u32 hotplug;
1817 int idx;
1818
1819 if (!drm_dev_enter(drm, &idx))
1820 return false;
1821
1822 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1823 hotplug = HDMI_READ(HDMI_HOTPLUG);
1824 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1825
1826 drm_dev_exit(idx);
1827
1828 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1829 }
1830
1831 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1832 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1833 unsigned int samplerate)
1834 {
1835 struct drm_device *drm = vc4_hdmi->connector.dev;
1836 u32 hsm_clock;
1837 unsigned long flags;
1838 unsigned long n, m;
1839 int idx;
1840
1841 if (!drm_dev_enter(drm, &idx))
1842 return;
1843
1844 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1845 rational_best_approximation(hsm_clock, samplerate,
1846 VC4_HD_MAI_SMP_N_MASK >>
1847 VC4_HD_MAI_SMP_N_SHIFT,
1848 (VC4_HD_MAI_SMP_M_MASK >>
1849 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1850 &n, &m);
1851
1852 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1853 HDMI_WRITE(HDMI_MAI_SMP,
1854 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1855 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1856 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1857
1858 drm_dev_exit(idx);
1859 }
1860
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1861 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1862 {
1863 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1864 u32 n, cts;
1865 u64 tmp;
1866
1867 lockdep_assert_held(&vc4_hdmi->mutex);
1868 lockdep_assert_held(&vc4_hdmi->hw_lock);
1869
1870 n = 128 * samplerate / 1000;
1871 tmp = (u64)(mode->clock * 1000) * n;
1872 do_div(tmp, 128 * samplerate);
1873 cts = tmp;
1874
1875 HDMI_WRITE(HDMI_CRP_CFG,
1876 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1877 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1878
1879 /*
1880 * We could get slightly more accurate clocks in some cases by
1881 * providing a CTS_1 value. The two CTS values are alternated
1882 * between based on the period fields
1883 */
1884 HDMI_WRITE(HDMI_CTS_0, cts);
1885 HDMI_WRITE(HDMI_CTS_1, cts);
1886 }
1887
dai_to_hdmi(struct snd_soc_dai * dai)1888 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1889 {
1890 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1891
1892 return snd_soc_card_get_drvdata(card);
1893 }
1894
vc4_hdmi_audio_can_stream(struct vc4_hdmi * vc4_hdmi)1895 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1896 {
1897 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1898
1899 lockdep_assert_held(&vc4_hdmi->mutex);
1900
1901 /*
1902 * If the encoder is currently in DVI mode, treat the codec DAI
1903 * as missing.
1904 */
1905 if (!display->is_hdmi)
1906 return false;
1907
1908 return true;
1909 }
1910
vc4_hdmi_audio_startup(struct device * dev,void * data)1911 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1912 {
1913 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1914 struct drm_device *drm = vc4_hdmi->connector.dev;
1915 unsigned long flags;
1916 int ret = 0;
1917 int idx;
1918
1919 mutex_lock(&vc4_hdmi->mutex);
1920
1921 if (!drm_dev_enter(drm, &idx)) {
1922 ret = -ENODEV;
1923 goto out;
1924 }
1925
1926 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1927 ret = -ENOTSUPP;
1928 goto out_dev_exit;
1929 }
1930
1931 vc4_hdmi->audio.streaming = true;
1932
1933 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1934 HDMI_WRITE(HDMI_MAI_CTL,
1935 VC4_HD_MAI_CTL_RESET |
1936 VC4_HD_MAI_CTL_FLUSH |
1937 VC4_HD_MAI_CTL_DLATE |
1938 VC4_HD_MAI_CTL_ERRORE |
1939 VC4_HD_MAI_CTL_ERRORF);
1940 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1941
1942 if (vc4_hdmi->variant->phy_rng_enable)
1943 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1944
1945 out_dev_exit:
1946 drm_dev_exit(idx);
1947 out:
1948 mutex_unlock(&vc4_hdmi->mutex);
1949
1950 return ret;
1951 }
1952
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1953 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1954 {
1955 struct device *dev = &vc4_hdmi->pdev->dev;
1956 unsigned long flags;
1957 int ret;
1958
1959 lockdep_assert_held(&vc4_hdmi->mutex);
1960
1961 vc4_hdmi->audio.streaming = false;
1962 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1963 if (ret)
1964 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1965
1966 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1967
1968 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1969 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1970 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1971
1972 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1973 }
1974
vc4_hdmi_audio_shutdown(struct device * dev,void * data)1975 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1976 {
1977 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1978 struct drm_device *drm = vc4_hdmi->connector.dev;
1979 unsigned long flags;
1980 int idx;
1981
1982 mutex_lock(&vc4_hdmi->mutex);
1983
1984 if (!drm_dev_enter(drm, &idx))
1985 goto out;
1986
1987 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1988
1989 HDMI_WRITE(HDMI_MAI_CTL,
1990 VC4_HD_MAI_CTL_DLATE |
1991 VC4_HD_MAI_CTL_ERRORE |
1992 VC4_HD_MAI_CTL_ERRORF);
1993
1994 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1995
1996 if (vc4_hdmi->variant->phy_rng_disable)
1997 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1998
1999 vc4_hdmi->audio.streaming = false;
2000 vc4_hdmi_audio_reset(vc4_hdmi);
2001
2002 drm_dev_exit(idx);
2003
2004 out:
2005 mutex_unlock(&vc4_hdmi->mutex);
2006 }
2007
sample_rate_to_mai_fmt(int samplerate)2008 static int sample_rate_to_mai_fmt(int samplerate)
2009 {
2010 switch (samplerate) {
2011 case 8000:
2012 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2013 case 11025:
2014 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2015 case 12000:
2016 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2017 case 16000:
2018 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2019 case 22050:
2020 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2021 case 24000:
2022 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2023 case 32000:
2024 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2025 case 44100:
2026 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2027 case 48000:
2028 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2029 case 64000:
2030 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2031 case 88200:
2032 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2033 case 96000:
2034 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2035 case 128000:
2036 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2037 case 176400:
2038 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2039 case 192000:
2040 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2041 default:
2042 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2043 }
2044 }
2045
2046 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2047 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2048 struct hdmi_codec_daifmt *daifmt,
2049 struct hdmi_codec_params *params)
2050 {
2051 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2052 struct drm_device *drm = vc4_hdmi->connector.dev;
2053 struct drm_connector *connector = &vc4_hdmi->connector;
2054 struct vc4_dev *vc4 = to_vc4_dev(drm);
2055 unsigned int sample_rate = params->sample_rate;
2056 unsigned int channels = params->channels;
2057 unsigned long flags;
2058 u32 audio_packet_config, channel_mask;
2059 u32 channel_map;
2060 u32 mai_audio_format;
2061 u32 mai_sample_rate;
2062 int ret = 0;
2063 int idx;
2064
2065 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2066 sample_rate, params->sample_width, channels);
2067
2068 mutex_lock(&vc4_hdmi->mutex);
2069
2070 if (!drm_dev_enter(drm, &idx)) {
2071 ret = -ENODEV;
2072 goto out;
2073 }
2074
2075 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2076 ret = -EINVAL;
2077 goto out_dev_exit;
2078 }
2079
2080 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2081
2082 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2083 HDMI_WRITE(HDMI_MAI_CTL,
2084 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2085 VC4_HD_MAI_CTL_WHOLSMP |
2086 VC4_HD_MAI_CTL_CHALIGN |
2087 VC4_HD_MAI_CTL_ENABLE);
2088
2089 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2090 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2091 params->channels == 8)
2092 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2093 else
2094 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2095 HDMI_WRITE(HDMI_MAI_FMT,
2096 VC4_SET_FIELD(mai_sample_rate,
2097 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2098 VC4_SET_FIELD(mai_audio_format,
2099 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2100
2101 /* The B frame identifier should match the value used by alsa-lib (8) */
2102 audio_packet_config =
2103 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2104 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2105 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2106
2107 channel_mask = GENMASK(channels - 1, 0);
2108 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2109 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2110
2111 /* Set the MAI threshold */
2112 if (vc4->gen >= VC4_GEN_5)
2113 HDMI_WRITE(HDMI_MAI_THR,
2114 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2115 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2116 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2117 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2118 else
2119 HDMI_WRITE(HDMI_MAI_THR,
2120 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2121 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2122 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2123 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2124
2125 HDMI_WRITE(HDMI_MAI_CONFIG,
2126 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2127 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2128 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2129
2130 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2131 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2132 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2133
2134 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2135
2136 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2137
2138 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2139 ¶ms->cea);
2140 if (ret)
2141 goto out_dev_exit;
2142
2143 out_dev_exit:
2144 drm_dev_exit(idx);
2145 out:
2146 mutex_unlock(&vc4_hdmi->mutex);
2147
2148 return ret;
2149 }
2150
2151 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2152 .name = "vc4-hdmi-cpu-dai-component",
2153 .legacy_dai_naming = 1,
2154 };
2155
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)2156 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2157 {
2158 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2159
2160 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2161
2162 return 0;
2163 }
2164
2165 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2166 .probe = vc4_hdmi_audio_cpu_dai_probe,
2167 };
2168
2169 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2170 .name = "vc4-hdmi-cpu-dai",
2171 .ops = &vc4_snd_dai_ops,
2172 .playback = {
2173 .stream_name = "Playback",
2174 .channels_min = 1,
2175 .channels_max = 8,
2176 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2177 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2178 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2179 SNDRV_PCM_RATE_192000,
2180 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2181 },
2182 };
2183
2184 static const struct snd_dmaengine_pcm_config pcm_conf = {
2185 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2186 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2187 };
2188
vc4_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2189 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2190 uint8_t *buf, size_t len)
2191 {
2192 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2193 struct drm_connector *connector = &vc4_hdmi->connector;
2194
2195 mutex_lock(&connector->eld_mutex);
2196 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2197 mutex_unlock(&connector->eld_mutex);
2198
2199 return 0;
2200 }
2201
2202 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2203 .get_eld = vc4_hdmi_audio_get_eld,
2204 .prepare = vc4_hdmi_audio_prepare,
2205 .audio_shutdown = vc4_hdmi_audio_shutdown,
2206 .audio_startup = vc4_hdmi_audio_startup,
2207 };
2208
2209 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2210 .ops = &vc4_hdmi_codec_ops,
2211 .max_i2s_channels = 8,
2212 .i2s = 1,
2213 };
2214
vc4_hdmi_audio_codec_release(void * ptr)2215 static void vc4_hdmi_audio_codec_release(void *ptr)
2216 {
2217 struct vc4_hdmi *vc4_hdmi = ptr;
2218
2219 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2220 vc4_hdmi->audio.codec_pdev = NULL;
2221 }
2222
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)2223 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2224 {
2225 const struct vc4_hdmi_register *mai_data =
2226 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2227 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2228 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2229 struct device *dev = &vc4_hdmi->pdev->dev;
2230 struct platform_device *codec_pdev;
2231 const __be32 *addr;
2232 int index, len;
2233 int ret;
2234
2235 /*
2236 * ASoC makes it a bit hard to retrieve a pointer to the
2237 * vc4_hdmi structure. Registering the card will overwrite our
2238 * device drvdata with a pointer to the snd_soc_card structure,
2239 * which can then be used to retrieve whatever drvdata we want
2240 * to associate.
2241 *
2242 * However, that doesn't fly in the case where we wouldn't
2243 * register an ASoC card (because of an old DT that is missing
2244 * the dmas properties for example), then the card isn't
2245 * registered and the device drvdata wouldn't be set.
2246 *
2247 * We can deal with both cases by making sure a snd_soc_card
2248 * pointer and a vc4_hdmi structure are pointing to the same
2249 * memory address, so we can treat them indistinctly without any
2250 * issue.
2251 */
2252 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2253 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2254
2255 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2256 dev_warn(dev,
2257 "'dmas' DT property is missing or empty, no HDMI audio\n");
2258 return 0;
2259 }
2260
2261 if (mai_data->reg != VC4_HD) {
2262 WARN_ONCE(true, "MAI isn't in the HD block\n");
2263 return -EINVAL;
2264 }
2265
2266 /*
2267 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2268 * the bus address specified in the DT, because the physical address
2269 * (the one returned by platform_get_resource()) is not appropriate
2270 * for DMA transfers.
2271 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2272 */
2273 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2274 /* Before BCM2711, we don't have a named register range */
2275 if (index < 0)
2276 index = 1;
2277
2278 addr = of_get_address(dev->of_node, index, NULL, NULL);
2279 if (!addr)
2280 return -EINVAL;
2281
2282 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2283 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2284 vc4_hdmi->audio.dma_data.maxburst = 2;
2285
2286 /*
2287 * NOTE: Strictly speaking, we should probably use a DRM-managed
2288 * registration there to avoid removing all the audio components
2289 * by the time the driver doesn't have any user anymore.
2290 *
2291 * However, the ASoC core uses a number of devm_kzalloc calls
2292 * when registering, even when using non-device-managed
2293 * functions (such as in snd_soc_register_component()).
2294 *
2295 * If we call snd_soc_unregister_component() in a DRM-managed
2296 * action, the device-managed actions have already been executed
2297 * and thus we would access memory that has been freed.
2298 *
2299 * Using device-managed hooks here probably leaves us open to a
2300 * bunch of issues if userspace still has a handle on the ALSA
2301 * device when the device is removed. However, this is mitigated
2302 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2303 * path to prevent the access to the device resources if it
2304 * isn't there anymore.
2305 *
2306 * Then, the vc4_hdmi structure is DRM-managed and thus only
2307 * freed whenever the last user has closed the DRM device file.
2308 * It should thus outlive ALSA in most situations.
2309 */
2310 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2311 if (ret) {
2312 dev_err(dev, "Could not register PCM component: %d\n", ret);
2313 return ret;
2314 }
2315
2316 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2317 &vc4_hdmi_audio_cpu_dai_drv, 1);
2318 if (ret) {
2319 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2320 return ret;
2321 }
2322
2323 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2324 PLATFORM_DEVID_AUTO,
2325 &vc4_hdmi_codec_pdata,
2326 sizeof(vc4_hdmi_codec_pdata));
2327 if (IS_ERR(codec_pdev)) {
2328 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2329 return PTR_ERR(codec_pdev);
2330 }
2331 vc4_hdmi->audio.codec_pdev = codec_pdev;
2332
2333 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2334 if (ret)
2335 return ret;
2336
2337 dai_link->cpus = &vc4_hdmi->audio.cpu;
2338 dai_link->codecs = &vc4_hdmi->audio.codec;
2339 dai_link->platforms = &vc4_hdmi->audio.platform;
2340
2341 dai_link->num_cpus = 1;
2342 dai_link->num_codecs = 1;
2343 dai_link->num_platforms = 1;
2344
2345 dai_link->name = "MAI";
2346 dai_link->stream_name = "MAI PCM";
2347 dai_link->codecs->dai_name = "i2s-hifi";
2348 dai_link->cpus->dai_name = dev_name(dev);
2349 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2350 dai_link->platforms->name = dev_name(dev);
2351
2352 card->dai_link = dai_link;
2353 card->num_links = 1;
2354 card->name = vc4_hdmi->variant->card_name;
2355 card->driver_name = "vc4-hdmi";
2356 card->dev = dev;
2357 card->owner = THIS_MODULE;
2358
2359 /*
2360 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2361 * stores a pointer to the snd card object in dev->driver_data. This
2362 * means we cannot use it for something else. The hdmi back-pointer is
2363 * now stored in card->drvdata and should be retrieved with
2364 * snd_soc_card_get_drvdata() if needed.
2365 */
2366 snd_soc_card_set_drvdata(card, vc4_hdmi);
2367 ret = devm_snd_soc_register_card(dev, card);
2368 if (ret)
2369 dev_err_probe(dev, ret, "Could not register sound card\n");
2370
2371 return ret;
2372
2373 }
2374
vc4_hdmi_hpd_irq_thread(int irq,void * priv)2375 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2376 {
2377 struct vc4_hdmi *vc4_hdmi = priv;
2378 struct drm_connector *connector = &vc4_hdmi->connector;
2379 struct drm_device *dev = connector->dev;
2380
2381 if (dev && dev->registered)
2382 drm_connector_helper_hpd_irq_event(connector);
2383
2384 return IRQ_HANDLED;
2385 }
2386
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)2387 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2388 {
2389 struct drm_connector *connector = &vc4_hdmi->connector;
2390 struct platform_device *pdev = vc4_hdmi->pdev;
2391 int ret;
2392
2393 if (vc4_hdmi->variant->external_irq_controller) {
2394 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2395 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2396
2397 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2398 NULL,
2399 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2400 "vc4 hdmi hpd connected", vc4_hdmi);
2401 if (ret)
2402 return ret;
2403
2404 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2405 NULL,
2406 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2407 "vc4 hdmi hpd disconnected", vc4_hdmi);
2408 if (ret)
2409 return ret;
2410
2411 connector->polled = DRM_CONNECTOR_POLL_HPD;
2412 }
2413
2414 return 0;
2415 }
2416
2417 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)2418 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2419 {
2420 struct vc4_hdmi *vc4_hdmi = priv;
2421
2422 if (vc4_hdmi->cec_rx_msg.len)
2423 cec_received_msg(vc4_hdmi->cec_adap,
2424 &vc4_hdmi->cec_rx_msg);
2425
2426 return IRQ_HANDLED;
2427 }
2428
vc4_cec_irq_handler_tx_thread(int irq,void * priv)2429 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2430 {
2431 struct vc4_hdmi *vc4_hdmi = priv;
2432
2433 if (vc4_hdmi->cec_tx_ok) {
2434 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2435 0, 0, 0, 0);
2436 } else {
2437 /*
2438 * This CEC implementation makes 1 retry, so if we
2439 * get a NACK, then that means it made 2 attempts.
2440 */
2441 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2442 0, 2, 0, 0);
2443 }
2444 return IRQ_HANDLED;
2445 }
2446
vc4_cec_irq_handler_thread(int irq,void * priv)2447 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2448 {
2449 struct vc4_hdmi *vc4_hdmi = priv;
2450 irqreturn_t ret;
2451
2452 if (vc4_hdmi->cec_irq_was_rx)
2453 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2454 else
2455 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2456
2457 return ret;
2458 }
2459
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)2460 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2461 {
2462 struct drm_device *dev = vc4_hdmi->connector.dev;
2463 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2464 unsigned int i;
2465
2466 lockdep_assert_held(&vc4_hdmi->hw_lock);
2467
2468 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2469 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2470
2471 if (msg->len > 16) {
2472 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2473 return;
2474 }
2475
2476 for (i = 0; i < msg->len; i += 4) {
2477 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2478
2479 msg->msg[i] = val & 0xff;
2480 msg->msg[i + 1] = (val >> 8) & 0xff;
2481 msg->msg[i + 2] = (val >> 16) & 0xff;
2482 msg->msg[i + 3] = (val >> 24) & 0xff;
2483 }
2484 }
2485
vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi * vc4_hdmi)2486 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2487 {
2488 u32 cntrl1;
2489
2490 /*
2491 * We don't need to protect the register access using
2492 * drm_dev_enter() there because the interrupt handler lifetime
2493 * is tied to the device itself, and not to the DRM device.
2494 *
2495 * So when the device will be gone, one of the first thing we
2496 * will be doing will be to unregister the interrupt handler,
2497 * and then unregister the DRM device. drm_dev_enter() would
2498 * thus always succeed if we are here.
2499 */
2500
2501 lockdep_assert_held(&vc4_hdmi->hw_lock);
2502
2503 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2504 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2505 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2506 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2507
2508 return IRQ_WAKE_THREAD;
2509 }
2510
vc4_cec_irq_handler_tx_bare(int irq,void * priv)2511 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2512 {
2513 struct vc4_hdmi *vc4_hdmi = priv;
2514 irqreturn_t ret;
2515
2516 spin_lock(&vc4_hdmi->hw_lock);
2517 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2518 spin_unlock(&vc4_hdmi->hw_lock);
2519
2520 return ret;
2521 }
2522
vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi * vc4_hdmi)2523 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2524 {
2525 u32 cntrl1;
2526
2527 lockdep_assert_held(&vc4_hdmi->hw_lock);
2528
2529 /*
2530 * We don't need to protect the register access using
2531 * drm_dev_enter() there because the interrupt handler lifetime
2532 * is tied to the device itself, and not to the DRM device.
2533 *
2534 * So when the device will be gone, one of the first thing we
2535 * will be doing will be to unregister the interrupt handler,
2536 * and then unregister the DRM device. drm_dev_enter() would
2537 * thus always succeed if we are here.
2538 */
2539
2540 vc4_hdmi->cec_rx_msg.len = 0;
2541 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2542 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2543 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2544 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2545 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2546
2547 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2548
2549 return IRQ_WAKE_THREAD;
2550 }
2551
vc4_cec_irq_handler_rx_bare(int irq,void * priv)2552 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2553 {
2554 struct vc4_hdmi *vc4_hdmi = priv;
2555 irqreturn_t ret;
2556
2557 spin_lock(&vc4_hdmi->hw_lock);
2558 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2559 spin_unlock(&vc4_hdmi->hw_lock);
2560
2561 return ret;
2562 }
2563
vc4_cec_irq_handler(int irq,void * priv)2564 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2565 {
2566 struct vc4_hdmi *vc4_hdmi = priv;
2567 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2568 irqreturn_t ret;
2569 u32 cntrl5;
2570
2571 /*
2572 * We don't need to protect the register access using
2573 * drm_dev_enter() there because the interrupt handler lifetime
2574 * is tied to the device itself, and not to the DRM device.
2575 *
2576 * So when the device will be gone, one of the first thing we
2577 * will be doing will be to unregister the interrupt handler,
2578 * and then unregister the DRM device. drm_dev_enter() would
2579 * thus always succeed if we are here.
2580 */
2581
2582 if (!(stat & VC4_HDMI_CPU_CEC))
2583 return IRQ_NONE;
2584
2585 spin_lock(&vc4_hdmi->hw_lock);
2586 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2587 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2588 if (vc4_hdmi->cec_irq_was_rx)
2589 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2590 else
2591 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2592
2593 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2594 spin_unlock(&vc4_hdmi->hw_lock);
2595
2596 return ret;
2597 }
2598
vc4_hdmi_cec_enable(struct cec_adapter * adap)2599 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2600 {
2601 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2602 struct drm_device *drm = vc4_hdmi->connector.dev;
2603 /* clock period in microseconds */
2604 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2605 unsigned long flags;
2606 u32 val;
2607 int ret;
2608 int idx;
2609
2610 if (!drm_dev_enter(drm, &idx))
2611 /*
2612 * We can't return an error code, because the CEC
2613 * framework will emit WARN_ON messages at unbind
2614 * otherwise.
2615 */
2616 return 0;
2617
2618 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2619 if (ret) {
2620 drm_dev_exit(idx);
2621 return ret;
2622 }
2623
2624 mutex_lock(&vc4_hdmi->mutex);
2625
2626 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2627
2628 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2629 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2630 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2631 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2632 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2633 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2634
2635 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2636 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2637 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2638 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2639 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2640 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2641 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2642 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2643 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2644 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2645 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2646 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2647 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2648 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2649 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2650 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2651 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2652 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2653 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2654
2655 if (!vc4_hdmi->variant->external_irq_controller)
2656 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2657
2658 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2659
2660 mutex_unlock(&vc4_hdmi->mutex);
2661 drm_dev_exit(idx);
2662
2663 return 0;
2664 }
2665
vc4_hdmi_cec_disable(struct cec_adapter * adap)2666 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2667 {
2668 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2669 struct drm_device *drm = vc4_hdmi->connector.dev;
2670 unsigned long flags;
2671 int idx;
2672
2673 if (!drm_dev_enter(drm, &idx))
2674 /*
2675 * We can't return an error code, because the CEC
2676 * framework will emit WARN_ON messages at unbind
2677 * otherwise.
2678 */
2679 return 0;
2680
2681 mutex_lock(&vc4_hdmi->mutex);
2682
2683 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2684
2685 if (!vc4_hdmi->variant->external_irq_controller)
2686 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2687
2688 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2689 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2690
2691 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2692
2693 mutex_unlock(&vc4_hdmi->mutex);
2694
2695 pm_runtime_put(&vc4_hdmi->pdev->dev);
2696
2697 drm_dev_exit(idx);
2698
2699 return 0;
2700 }
2701
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)2702 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2703 {
2704 if (enable)
2705 return vc4_hdmi_cec_enable(adap);
2706 else
2707 return vc4_hdmi_cec_disable(adap);
2708 }
2709
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)2710 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2711 {
2712 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2713 struct drm_device *drm = vc4_hdmi->connector.dev;
2714 unsigned long flags;
2715 int idx;
2716
2717 if (!drm_dev_enter(drm, &idx))
2718 /*
2719 * We can't return an error code, because the CEC
2720 * framework will emit WARN_ON messages at unbind
2721 * otherwise.
2722 */
2723 return 0;
2724
2725 mutex_lock(&vc4_hdmi->mutex);
2726 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2727 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2728 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2729 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2730 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2731 mutex_unlock(&vc4_hdmi->mutex);
2732
2733 drm_dev_exit(idx);
2734
2735 return 0;
2736 }
2737
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2738 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2739 u32 signal_free_time, struct cec_msg *msg)
2740 {
2741 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2742 struct drm_device *dev = vc4_hdmi->connector.dev;
2743 unsigned long flags;
2744 u32 val;
2745 unsigned int i;
2746 int idx;
2747
2748 if (!drm_dev_enter(dev, &idx))
2749 return -ENODEV;
2750
2751 if (msg->len > 16) {
2752 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2753 drm_dev_exit(idx);
2754 return -ENOMEM;
2755 }
2756
2757 mutex_lock(&vc4_hdmi->mutex);
2758
2759 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2760
2761 for (i = 0; i < msg->len; i += 4)
2762 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2763 (msg->msg[i]) |
2764 (msg->msg[i + 1] << 8) |
2765 (msg->msg[i + 2] << 16) |
2766 (msg->msg[i + 3] << 24));
2767
2768 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2769 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2770 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2771 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2772 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2773 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2774
2775 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2776
2777 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2778 mutex_unlock(&vc4_hdmi->mutex);
2779 drm_dev_exit(idx);
2780
2781 return 0;
2782 }
2783
2784 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2785 .adap_enable = vc4_hdmi_cec_adap_enable,
2786 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2787 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2788 };
2789
vc4_hdmi_cec_release(void * ptr)2790 static void vc4_hdmi_cec_release(void *ptr)
2791 {
2792 struct vc4_hdmi *vc4_hdmi = ptr;
2793
2794 cec_unregister_adapter(vc4_hdmi->cec_adap);
2795 vc4_hdmi->cec_adap = NULL;
2796 }
2797
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2798 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2799 {
2800 struct cec_connector_info conn_info;
2801 struct platform_device *pdev = vc4_hdmi->pdev;
2802 struct device *dev = &pdev->dev;
2803 int ret;
2804
2805 if (!of_property_present(dev->of_node, "interrupts")) {
2806 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2807 return 0;
2808 }
2809
2810 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2811 vc4_hdmi,
2812 vc4_hdmi->variant->card_name,
2813 CEC_CAP_DEFAULTS |
2814 CEC_CAP_CONNECTOR_INFO, 1);
2815 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2816 if (ret < 0)
2817 return ret;
2818
2819 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2820 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2821
2822 if (vc4_hdmi->variant->external_irq_controller) {
2823 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2824 vc4_cec_irq_handler_rx_bare,
2825 vc4_cec_irq_handler_rx_thread, 0,
2826 "vc4 hdmi cec rx", vc4_hdmi);
2827 if (ret)
2828 goto err_delete_cec_adap;
2829
2830 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2831 vc4_cec_irq_handler_tx_bare,
2832 vc4_cec_irq_handler_tx_thread, 0,
2833 "vc4 hdmi cec tx", vc4_hdmi);
2834 if (ret)
2835 goto err_delete_cec_adap;
2836 } else {
2837 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2838 vc4_cec_irq_handler,
2839 vc4_cec_irq_handler_thread, 0,
2840 "vc4 hdmi cec", vc4_hdmi);
2841 if (ret)
2842 goto err_delete_cec_adap;
2843 }
2844
2845 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2846 if (ret < 0)
2847 goto err_delete_cec_adap;
2848
2849 /*
2850 * NOTE: Strictly speaking, we should probably use a DRM-managed
2851 * registration there to avoid removing the CEC adapter by the
2852 * time the DRM driver doesn't have any user anymore.
2853 *
2854 * However, the CEC framework already cleans up the CEC adapter
2855 * only when the last user has closed its file descriptor, so we
2856 * don't need to handle it in DRM.
2857 *
2858 * By the time the device-managed hook is executed, we will give
2859 * up our reference to the CEC adapter and therefore don't
2860 * really care when it's actually freed.
2861 *
2862 * There's still a problematic sequence: if we unregister our
2863 * CEC adapter, but the userspace keeps a handle on the CEC
2864 * adapter but not the DRM device for some reason. In such a
2865 * case, our vc4_hdmi structure will be freed, but the
2866 * cec_adapter structure will have a dangling pointer to what
2867 * used to be our HDMI controller. If we get a CEC call at that
2868 * moment, we could end up with a use-after-free. Fortunately,
2869 * the CEC framework already handles this too, by calling
2870 * cec_is_registered() in cec_ioctl() and cec_poll().
2871 */
2872 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2873 if (ret)
2874 return ret;
2875
2876 return 0;
2877
2878 err_delete_cec_adap:
2879 cec_delete_adapter(vc4_hdmi->cec_adap);
2880
2881 return ret;
2882 }
2883 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2884 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2885 {
2886 return 0;
2887 }
2888 #endif
2889
vc4_hdmi_free_regset(struct drm_device * drm,void * ptr)2890 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2891 {
2892 struct debugfs_reg32 *regs = ptr;
2893
2894 kfree(regs);
2895 }
2896
vc4_hdmi_build_regset(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)2897 static int vc4_hdmi_build_regset(struct drm_device *drm,
2898 struct vc4_hdmi *vc4_hdmi,
2899 struct debugfs_regset32 *regset,
2900 enum vc4_hdmi_regs reg)
2901 {
2902 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2903 struct debugfs_reg32 *regs, *new_regs;
2904 unsigned int count = 0;
2905 unsigned int i;
2906 int ret;
2907
2908 regs = kcalloc(variant->num_registers, sizeof(*regs),
2909 GFP_KERNEL);
2910 if (!regs)
2911 return -ENOMEM;
2912
2913 for (i = 0; i < variant->num_registers; i++) {
2914 const struct vc4_hdmi_register *field = &variant->registers[i];
2915
2916 if (field->reg != reg)
2917 continue;
2918
2919 regs[count].name = field->name;
2920 regs[count].offset = field->offset;
2921 count++;
2922 }
2923
2924 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2925 if (!new_regs)
2926 return -ENOMEM;
2927
2928 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2929 regset->regs = new_regs;
2930 regset->nregs = count;
2931
2932 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2933 if (ret)
2934 return ret;
2935
2936 return 0;
2937 }
2938
vc4_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2939 static int vc4_hdmi_init_resources(struct drm_device *drm,
2940 struct vc4_hdmi *vc4_hdmi)
2941 {
2942 struct platform_device *pdev = vc4_hdmi->pdev;
2943 struct device *dev = &pdev->dev;
2944 int ret;
2945
2946 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2947 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2948 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2949
2950 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2951 if (IS_ERR(vc4_hdmi->hd_regs))
2952 return PTR_ERR(vc4_hdmi->hd_regs);
2953
2954 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2955 if (ret)
2956 return ret;
2957
2958 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2959 if (ret)
2960 return ret;
2961
2962 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2963 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2964 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2965 if (ret != -EPROBE_DEFER)
2966 drm_err(drm, "Failed to get pixel clock\n");
2967 return ret;
2968 }
2969
2970 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2971 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2972 drm_err(drm, "Failed to get HDMI state machine clock\n");
2973 return PTR_ERR(vc4_hdmi->hsm_clock);
2974 }
2975 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2976 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2977
2978 return 0;
2979 }
2980
vc5_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2981 static int vc5_hdmi_init_resources(struct drm_device *drm,
2982 struct vc4_hdmi *vc4_hdmi)
2983 {
2984 struct platform_device *pdev = vc4_hdmi->pdev;
2985 struct device *dev = &pdev->dev;
2986 struct resource *res;
2987 int ret;
2988
2989 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2990 if (!res)
2991 return -ENODEV;
2992
2993 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2994 resource_size(res));
2995 if (!vc4_hdmi->hdmicore_regs)
2996 return -ENOMEM;
2997
2998 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2999 if (!res)
3000 return -ENODEV;
3001
3002 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3003 if (!vc4_hdmi->hd_regs)
3004 return -ENOMEM;
3005
3006 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3007 if (!res)
3008 return -ENODEV;
3009
3010 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3011 if (!vc4_hdmi->cec_regs)
3012 return -ENOMEM;
3013
3014 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3015 if (!res)
3016 return -ENODEV;
3017
3018 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3019 if (!vc4_hdmi->csc_regs)
3020 return -ENOMEM;
3021
3022 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3023 if (!res)
3024 return -ENODEV;
3025
3026 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3027 if (!vc4_hdmi->dvp_regs)
3028 return -ENOMEM;
3029
3030 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3031 if (!res)
3032 return -ENODEV;
3033
3034 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3035 if (!vc4_hdmi->phy_regs)
3036 return -ENOMEM;
3037
3038 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3039 if (!res)
3040 return -ENODEV;
3041
3042 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3043 if (!vc4_hdmi->ram_regs)
3044 return -ENOMEM;
3045
3046 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3047 if (!res)
3048 return -ENODEV;
3049
3050 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3051 if (!vc4_hdmi->rm_regs)
3052 return -ENOMEM;
3053
3054 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3055 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3056 drm_err(drm, "Failed to get HDMI state machine clock\n");
3057 return PTR_ERR(vc4_hdmi->hsm_clock);
3058 }
3059
3060 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3061 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3062 drm_err(drm, "Failed to get pixel bvb clock\n");
3063 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3064 }
3065
3066 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3067 if (IS_ERR(vc4_hdmi->audio_clock)) {
3068 drm_err(drm, "Failed to get audio clock\n");
3069 return PTR_ERR(vc4_hdmi->audio_clock);
3070 }
3071
3072 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3073 if (IS_ERR(vc4_hdmi->cec_clock)) {
3074 drm_err(drm, "Failed to get CEC clock\n");
3075 return PTR_ERR(vc4_hdmi->cec_clock);
3076 }
3077
3078 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3079 if (IS_ERR(vc4_hdmi->reset)) {
3080 drm_err(drm, "Failed to get HDMI reset line\n");
3081 return PTR_ERR(vc4_hdmi->reset);
3082 }
3083
3084 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3085 if (ret)
3086 return ret;
3087
3088 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3089 if (ret)
3090 return ret;
3091
3092 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3093 if (ret)
3094 return ret;
3095
3096 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3097 if (ret)
3098 return ret;
3099
3100 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3101 if (ret)
3102 return ret;
3103
3104 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3105 if (ret)
3106 return ret;
3107
3108 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3109 if (ret)
3110 return ret;
3111
3112 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3113 if (ret)
3114 return ret;
3115
3116 return 0;
3117 }
3118
vc4_hdmi_runtime_suspend(struct device * dev)3119 static int vc4_hdmi_runtime_suspend(struct device *dev)
3120 {
3121 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3122
3123 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3124
3125 return 0;
3126 }
3127
vc4_hdmi_runtime_resume(struct device * dev)3128 static int vc4_hdmi_runtime_resume(struct device *dev)
3129 {
3130 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3131 unsigned long __maybe_unused flags;
3132 u32 __maybe_unused value;
3133 unsigned long rate;
3134 int ret;
3135
3136 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3137 if (ret)
3138 return ret;
3139
3140 /*
3141 * Whenever the RaspberryPi boots without an HDMI monitor
3142 * plugged in, the firmware won't have initialized the HSM clock
3143 * rate and it will be reported as 0.
3144 *
3145 * If we try to access a register of the controller in such a
3146 * case, it will lead to a silent CPU stall. Let's make sure we
3147 * prevent such a case.
3148 */
3149 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3150 if (!rate) {
3151 ret = -EINVAL;
3152 goto err_disable_clk;
3153 }
3154
3155 if (vc4_hdmi->variant->reset)
3156 vc4_hdmi->variant->reset(vc4_hdmi);
3157
3158 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3159 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3160 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3161 /* Set the logical address to Unregistered */
3162 value |= VC4_HDMI_CEC_ADDR_MASK;
3163 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3164 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3165
3166 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3167
3168 if (!vc4_hdmi->variant->external_irq_controller) {
3169 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3170 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3171 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3172 }
3173 #endif
3174
3175 return 0;
3176
3177 err_disable_clk:
3178 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3179 return ret;
3180 }
3181
vc4_hdmi_put_ddc_device(void * ptr)3182 static void vc4_hdmi_put_ddc_device(void *ptr)
3183 {
3184 struct vc4_hdmi *vc4_hdmi = ptr;
3185
3186 put_device(&vc4_hdmi->ddc->dev);
3187 }
3188
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)3189 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3190 {
3191 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3192 struct platform_device *pdev = to_platform_device(dev);
3193 struct drm_device *drm = dev_get_drvdata(master);
3194 struct vc4_hdmi *vc4_hdmi;
3195 struct drm_encoder *encoder;
3196 struct device_node *ddc_node;
3197 int ret;
3198
3199 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3200 if (!vc4_hdmi)
3201 return -ENOMEM;
3202
3203 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3204 if (ret)
3205 return ret;
3206
3207 spin_lock_init(&vc4_hdmi->hw_lock);
3208 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3209
3210 dev_set_drvdata(dev, vc4_hdmi);
3211 encoder = &vc4_hdmi->encoder.base;
3212 vc4_hdmi->encoder.type = variant->encoder_type;
3213 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3214 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3215 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3216 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3217 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3218 vc4_hdmi->pdev = pdev;
3219 vc4_hdmi->variant = variant;
3220
3221 /*
3222 * Since we don't know the state of the controller and its
3223 * display (if any), let's assume it's always enabled.
3224 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3225 * sure it's disabled, and avoid any inconsistency.
3226 */
3227 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3228 vc4_hdmi->scdc_enabled = true;
3229
3230 ret = variant->init_resources(drm, vc4_hdmi);
3231 if (ret)
3232 return ret;
3233
3234 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3235 if (!ddc_node) {
3236 drm_err(drm, "Failed to find ddc node in device tree\n");
3237 return -ENODEV;
3238 }
3239
3240 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3241 of_node_put(ddc_node);
3242 if (!vc4_hdmi->ddc) {
3243 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3244 return -EPROBE_DEFER;
3245 }
3246
3247 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3248 if (ret)
3249 return ret;
3250
3251 /* Only use the GPIO HPD pin if present in the DT, otherwise
3252 * we'll use the HDMI core's register.
3253 */
3254 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3255 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3256 return PTR_ERR(vc4_hdmi->hpd_gpio);
3257 }
3258
3259 vc4_hdmi->disable_wifi_frequencies =
3260 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3261
3262 ret = devm_pm_runtime_enable(dev);
3263 if (ret)
3264 return ret;
3265
3266 /*
3267 * We need to have the device powered up at this point to call
3268 * our reset hook and for the CEC init.
3269 */
3270 ret = pm_runtime_resume_and_get(dev);
3271 if (ret)
3272 return ret;
3273
3274 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3275 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3276 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3277 clk_prepare_enable(vc4_hdmi->pixel_clock);
3278 clk_prepare_enable(vc4_hdmi->hsm_clock);
3279 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3280 }
3281
3282 ret = drmm_encoder_init(drm, encoder,
3283 &vc4_hdmi_encoder_funcs,
3284 DRM_MODE_ENCODER_TMDS,
3285 NULL);
3286 if (ret)
3287 goto err_put_runtime_pm;
3288
3289 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3290
3291 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3292 if (ret)
3293 goto err_put_runtime_pm;
3294
3295 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3296 if (ret)
3297 goto err_put_runtime_pm;
3298
3299 ret = vc4_hdmi_cec_init(vc4_hdmi);
3300 if (ret)
3301 goto err_put_runtime_pm;
3302
3303 ret = vc4_hdmi_audio_init(vc4_hdmi);
3304 if (ret)
3305 goto err_put_runtime_pm;
3306
3307 pm_runtime_put_sync(dev);
3308
3309 return 0;
3310
3311 err_put_runtime_pm:
3312 pm_runtime_put_sync(dev);
3313
3314 return ret;
3315 }
3316
3317 static const struct component_ops vc4_hdmi_ops = {
3318 .bind = vc4_hdmi_bind,
3319 };
3320
vc4_hdmi_dev_probe(struct platform_device * pdev)3321 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3322 {
3323 return component_add(&pdev->dev, &vc4_hdmi_ops);
3324 }
3325
vc4_hdmi_dev_remove(struct platform_device * pdev)3326 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3327 {
3328 component_del(&pdev->dev, &vc4_hdmi_ops);
3329 }
3330
3331 static const struct vc4_hdmi_variant bcm2835_variant = {
3332 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3333 .debugfs_name = "hdmi_regs",
3334 .card_name = "vc4-hdmi",
3335 .max_pixel_clock = 162000000,
3336 .registers = vc4_hdmi_fields,
3337 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3338
3339 .init_resources = vc4_hdmi_init_resources,
3340 .csc_setup = vc4_hdmi_csc_setup,
3341 .reset = vc4_hdmi_reset,
3342 .set_timings = vc4_hdmi_set_timings,
3343 .phy_init = vc4_hdmi_phy_init,
3344 .phy_disable = vc4_hdmi_phy_disable,
3345 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3346 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3347 .channel_map = vc4_hdmi_channel_map,
3348 .supports_hdr = false,
3349 };
3350
3351 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3352 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3353 .debugfs_name = "hdmi0_regs",
3354 .card_name = "vc4-hdmi-0",
3355 .max_pixel_clock = 600000000,
3356 .registers = vc5_hdmi_hdmi0_fields,
3357 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3358 .phy_lane_mapping = {
3359 PHY_LANE_0,
3360 PHY_LANE_1,
3361 PHY_LANE_2,
3362 PHY_LANE_CK,
3363 },
3364 .unsupported_odd_h_timings = true,
3365 .external_irq_controller = true,
3366
3367 .init_resources = vc5_hdmi_init_resources,
3368 .csc_setup = vc5_hdmi_csc_setup,
3369 .reset = vc5_hdmi_reset,
3370 .set_timings = vc5_hdmi_set_timings,
3371 .phy_init = vc5_hdmi_phy_init,
3372 .phy_disable = vc5_hdmi_phy_disable,
3373 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3374 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3375 .channel_map = vc5_hdmi_channel_map,
3376 .supports_hdr = true,
3377 .hp_detect = vc5_hdmi_hp_detect,
3378 };
3379
3380 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3381 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3382 .debugfs_name = "hdmi1_regs",
3383 .card_name = "vc4-hdmi-1",
3384 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3385 .registers = vc5_hdmi_hdmi1_fields,
3386 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3387 .phy_lane_mapping = {
3388 PHY_LANE_1,
3389 PHY_LANE_0,
3390 PHY_LANE_CK,
3391 PHY_LANE_2,
3392 },
3393 .unsupported_odd_h_timings = true,
3394 .external_irq_controller = true,
3395
3396 .init_resources = vc5_hdmi_init_resources,
3397 .csc_setup = vc5_hdmi_csc_setup,
3398 .reset = vc5_hdmi_reset,
3399 .set_timings = vc5_hdmi_set_timings,
3400 .phy_init = vc5_hdmi_phy_init,
3401 .phy_disable = vc5_hdmi_phy_disable,
3402 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3403 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3404 .channel_map = vc5_hdmi_channel_map,
3405 .supports_hdr = true,
3406 .hp_detect = vc5_hdmi_hp_detect,
3407 };
3408
3409 static const struct of_device_id vc4_hdmi_dt_match[] = {
3410 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3411 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3412 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3413 {}
3414 };
3415
3416 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3417 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3418 vc4_hdmi_runtime_resume,
3419 NULL)
3420 };
3421
3422 struct platform_driver vc4_hdmi_driver = {
3423 .probe = vc4_hdmi_dev_probe,
3424 .remove_new = vc4_hdmi_dev_remove,
3425 .driver = {
3426 .name = "vc4_hdmi",
3427 .of_match_table = vc4_hdmi_dt_match,
3428 .pm = &vc4_hdmi_pm_ops,
3429 },
3430 };
3431