1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 */
5
6 /**
7 * DOC: VC4 HVS module.
8 *
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
10 * translation, scaling, colorspace conversion, and compositing of
11 * pixels stored in framebuffers into a FIFO of pixels going out to
12 * the Pixel Valve (CRTC). It operates at the system clock rate (the
13 * system audio clock gate, specifically), which is much higher than
14 * the pixel clock rate.
15 *
16 * There is a single global HVS, with multiple output FIFOs that can
17 * be consumed by the PVs. This file just manages the resources for
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
19 * each CRTC.
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/clk.h>
24 #include <linux/component.h>
25 #include <linux/platform_device.h>
26
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_drv.h>
29 #include <drm/drm_vblank.h>
30
31 #include <soc/bcm2835/raspberrypi-firmware.h>
32
33 #include "vc4_drv.h"
34 #include "vc4_regs.h"
35
36 static const struct debugfs_reg32 hvs_regs[] = {
37 VC4_REG32(SCALER_DISPCTRL),
38 VC4_REG32(SCALER_DISPSTAT),
39 VC4_REG32(SCALER_DISPID),
40 VC4_REG32(SCALER_DISPECTRL),
41 VC4_REG32(SCALER_DISPPROF),
42 VC4_REG32(SCALER_DISPDITHER),
43 VC4_REG32(SCALER_DISPEOLN),
44 VC4_REG32(SCALER_DISPLIST0),
45 VC4_REG32(SCALER_DISPLIST1),
46 VC4_REG32(SCALER_DISPLIST2),
47 VC4_REG32(SCALER_DISPLSTAT),
48 VC4_REG32(SCALER_DISPLACT0),
49 VC4_REG32(SCALER_DISPLACT1),
50 VC4_REG32(SCALER_DISPLACT2),
51 VC4_REG32(SCALER_DISPCTRL0),
52 VC4_REG32(SCALER_DISPBKGND0),
53 VC4_REG32(SCALER_DISPSTAT0),
54 VC4_REG32(SCALER_DISPBASE0),
55 VC4_REG32(SCALER_DISPCTRL1),
56 VC4_REG32(SCALER_DISPBKGND1),
57 VC4_REG32(SCALER_DISPSTAT1),
58 VC4_REG32(SCALER_DISPBASE1),
59 VC4_REG32(SCALER_DISPCTRL2),
60 VC4_REG32(SCALER_DISPBKGND2),
61 VC4_REG32(SCALER_DISPSTAT2),
62 VC4_REG32(SCALER_DISPBASE2),
63 VC4_REG32(SCALER_DISPALPHA2),
64 VC4_REG32(SCALER_OLEDOFFS),
65 VC4_REG32(SCALER_OLEDCOEF0),
66 VC4_REG32(SCALER_OLEDCOEF1),
67 VC4_REG32(SCALER_OLEDCOEF2),
68 };
69
vc4_hvs_dump_state(struct vc4_hvs * hvs)70 void vc4_hvs_dump_state(struct vc4_hvs *hvs)
71 {
72 struct drm_device *drm = &hvs->vc4->base;
73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev);
74 int idx, i;
75
76 if (!drm_dev_enter(drm, &idx))
77 return;
78
79 drm_print_regset32(&p, &hvs->regset);
80
81 DRM_INFO("HVS ctx:\n");
82 for (i = 0; i < 64; i += 4) {
83 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
84 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
85 readl((u32 __iomem *)hvs->dlist + i + 0),
86 readl((u32 __iomem *)hvs->dlist + i + 1),
87 readl((u32 __iomem *)hvs->dlist + i + 2),
88 readl((u32 __iomem *)hvs->dlist + i + 3));
89 }
90
91 drm_dev_exit(idx);
92 }
93
vc4_hvs_debugfs_underrun(struct seq_file * m,void * data)94 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
95 {
96 struct drm_debugfs_entry *entry = m->private;
97 struct drm_device *dev = entry->dev;
98 struct vc4_dev *vc4 = to_vc4_dev(dev);
99 struct drm_printer p = drm_seq_file_printer(m);
100
101 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
102
103 return 0;
104 }
105
vc4_hvs_debugfs_dlist(struct seq_file * m,void * data)106 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data)
107 {
108 struct drm_debugfs_entry *entry = m->private;
109 struct drm_device *dev = entry->dev;
110 struct vc4_dev *vc4 = to_vc4_dev(dev);
111 struct vc4_hvs *hvs = vc4->hvs;
112 struct drm_printer p = drm_seq_file_printer(m);
113 unsigned int dlist_mem_size = hvs->dlist_mem_size;
114 unsigned int next_entry_start;
115 unsigned int i, j;
116 u32 dlist_word, dispstat;
117
118 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) {
119 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)),
120 SCALER_DISPSTATX_MODE);
121 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED ||
122 dispstat == SCALER_DISPSTATX_MODE_EOF) {
123 drm_printf(&p, "HVS chan %u disabled\n", i);
124 continue;
125 }
126
127 drm_printf(&p, "HVS chan %u:\n", i);
128 next_entry_start = 0;
129
130 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < dlist_mem_size; j++) {
131 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j);
132 drm_printf(&p, "dlist: %02d: 0x%08x\n", j,
133 dlist_word);
134 if (!next_entry_start ||
135 next_entry_start == j) {
136 if (dlist_word & SCALER_CTL0_END)
137 break;
138 next_entry_start = j +
139 VC4_GET_FIELD(dlist_word,
140 SCALER_CTL0_SIZE);
141 }
142 }
143 }
144
145 return 0;
146 }
147
148 /* The filter kernel is composed of dwords each containing 3 9-bit
149 * signed integers packed next to each other.
150 */
151 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
152 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \
153 ((((c0) & 0x1ff) << 0) | \
154 (((c1) & 0x1ff) << 9) | \
155 (((c2) & 0x1ff) << 18))
156
157 /* The whole filter kernel is arranged as the coefficients 0-16 going
158 * up, then a pad, then 17-31 going down and reversed within the
159 * dwords. This means that a linear phase kernel (where it's
160 * symmetrical at the boundary between 15 and 16) has the last 5
161 * dwords matching the first 5, but reversed.
162 */
163 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
164 c9, c10, c11, c12, c13, c14, c15) \
165 {VC4_PPF_FILTER_WORD(c0, c1, c2), \
166 VC4_PPF_FILTER_WORD(c3, c4, c5), \
167 VC4_PPF_FILTER_WORD(c6, c7, c8), \
168 VC4_PPF_FILTER_WORD(c9, c10, c11), \
169 VC4_PPF_FILTER_WORD(c12, c13, c14), \
170 VC4_PPF_FILTER_WORD(c15, c15, 0)}
171
172 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
173 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
174
175 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
176 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
177 */
178 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
179 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
180 50, 82, 119, 155, 187, 213, 227);
181
vc4_hvs_upload_linear_kernel(struct vc4_hvs * hvs,struct drm_mm_node * space,const u32 * kernel)182 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
183 struct drm_mm_node *space,
184 const u32 *kernel)
185 {
186 int ret, i;
187 u32 __iomem *dst_kernel;
188
189 /*
190 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit()
191 * here since that function is only called from vc4_hvs_bind().
192 */
193
194 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
195 if (ret) {
196 drm_err(&hvs->vc4->base, "Failed to allocate space for filter kernel: %d\n",
197 ret);
198 return ret;
199 }
200
201 dst_kernel = hvs->dlist + space->start;
202
203 for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
204 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
205 writel(kernel[i], &dst_kernel[i]);
206 else {
207 writel(kernel[VC4_KERNEL_DWORDS - i - 1],
208 &dst_kernel[i]);
209 }
210 }
211
212 return 0;
213 }
214
vc4_hvs_lut_load(struct vc4_hvs * hvs,struct vc4_crtc * vc4_crtc)215 static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
216 struct vc4_crtc *vc4_crtc)
217 {
218 struct drm_device *drm = &hvs->vc4->base;
219 struct drm_crtc *crtc = &vc4_crtc->base;
220 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
221 int idx;
222 u32 i;
223
224 if (!drm_dev_enter(drm, &idx))
225 return;
226
227 if (hvs->vc4->gen != VC4_GEN_4)
228 goto exit;
229
230 /* The LUT memory is laid out with each HVS channel in order,
231 * each of which takes 256 writes for R, 256 for G, then 256
232 * for B.
233 */
234 HVS_WRITE(SCALER_GAMADDR,
235 SCALER_GAMADDR_AUTOINC |
236 (vc4_state->assigned_channel * 3 * crtc->gamma_size));
237
238 for (i = 0; i < crtc->gamma_size; i++)
239 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
240 for (i = 0; i < crtc->gamma_size; i++)
241 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
242 for (i = 0; i < crtc->gamma_size; i++)
243 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
244
245 exit:
246 drm_dev_exit(idx);
247 }
248
vc4_hvs_update_gamma_lut(struct vc4_hvs * hvs,struct vc4_crtc * vc4_crtc)249 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
250 struct vc4_crtc *vc4_crtc)
251 {
252 struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
253 struct drm_color_lut *lut = crtc_state->gamma_lut->data;
254 u32 length = drm_color_lut_size(crtc_state->gamma_lut);
255 u32 i;
256
257 for (i = 0; i < length; i++) {
258 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
259 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
260 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
261 }
262
263 vc4_hvs_lut_load(hvs, vc4_crtc);
264 }
265
vc4_hvs_get_fifo_frame_count(struct vc4_hvs * hvs,unsigned int fifo)266 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
267 {
268 struct drm_device *drm = &hvs->vc4->base;
269 u8 field = 0;
270 int idx;
271
272 if (!drm_dev_enter(drm, &idx))
273 return 0;
274
275 switch (fifo) {
276 case 0:
277 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
278 SCALER_DISPSTAT1_FRCNT0);
279 break;
280 case 1:
281 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
282 SCALER_DISPSTAT1_FRCNT1);
283 break;
284 case 2:
285 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
286 SCALER_DISPSTAT2_FRCNT2);
287 break;
288 }
289
290 drm_dev_exit(idx);
291 return field;
292 }
293
vc4_hvs_get_fifo_from_output(struct vc4_hvs * hvs,unsigned int output)294 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
295 {
296 struct vc4_dev *vc4 = hvs->vc4;
297 u32 reg;
298 int ret;
299
300 if (vc4->gen == VC4_GEN_4)
301 return output;
302
303 /*
304 * NOTE: We should probably use drm_dev_enter()/drm_dev_exit()
305 * here, but this function is only used during the DRM device
306 * initialization, so we should be fine.
307 */
308
309 switch (output) {
310 case 0:
311 return 0;
312
313 case 1:
314 return 1;
315
316 case 2:
317 reg = HVS_READ(SCALER_DISPECTRL);
318 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
319 if (ret == 0)
320 return 2;
321
322 return 0;
323
324 case 3:
325 reg = HVS_READ(SCALER_DISPCTRL);
326 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
327 if (ret == 3)
328 return -EPIPE;
329
330 return ret;
331
332 case 4:
333 reg = HVS_READ(SCALER_DISPEOLN);
334 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
335 if (ret == 3)
336 return -EPIPE;
337
338 return ret;
339
340 case 5:
341 reg = HVS_READ(SCALER_DISPDITHER);
342 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
343 if (ret == 3)
344 return -EPIPE;
345
346 return ret;
347
348 default:
349 return -EPIPE;
350 }
351 }
352
vc4_hvs_init_channel(struct vc4_hvs * hvs,struct drm_crtc * crtc,struct drm_display_mode * mode,bool oneshot)353 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
354 struct drm_display_mode *mode, bool oneshot)
355 {
356 struct vc4_dev *vc4 = hvs->vc4;
357 struct drm_device *drm = &vc4->base;
358 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
359 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
360 unsigned int chan = vc4_crtc_state->assigned_channel;
361 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
362 u32 dispbkgndx;
363 u32 dispctrl;
364 int idx;
365
366 if (!drm_dev_enter(drm, &idx))
367 return -ENODEV;
368
369 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
370 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
371 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
372
373 /* Turn on the scaler, which will wait for vstart to start
374 * compositing.
375 * When feeding the transposer, we should operate in oneshot
376 * mode.
377 */
378 dispctrl = SCALER_DISPCTRLX_ENABLE;
379 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
380
381 if (vc4->gen == VC4_GEN_4) {
382 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
383 SCALER_DISPCTRLX_WIDTH) |
384 VC4_SET_FIELD(mode->vdisplay,
385 SCALER_DISPCTRLX_HEIGHT) |
386 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
387 dispbkgndx |= SCALER_DISPBKGND_AUTOHS;
388 } else {
389 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
390 SCALER5_DISPCTRLX_WIDTH) |
391 VC4_SET_FIELD(mode->vdisplay,
392 SCALER5_DISPCTRLX_HEIGHT) |
393 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
394 dispbkgndx &= ~SCALER5_DISPBKGND_BCK2BCK;
395 }
396
397 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
398
399 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
400 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
401
402 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
403 ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) |
404 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
405
406 /* Reload the LUT, since the SRAMs would have been disabled if
407 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
408 */
409 vc4_hvs_lut_load(hvs, vc4_crtc);
410
411 drm_dev_exit(idx);
412
413 return 0;
414 }
415
vc4_hvs_stop_channel(struct vc4_hvs * hvs,unsigned int chan)416 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
417 {
418 struct drm_device *drm = &hvs->vc4->base;
419 int idx;
420
421 if (!drm_dev_enter(drm, &idx))
422 return;
423
424 if (!(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE))
425 goto out;
426
427 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
428 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
429
430 /* Once we leave, the scaler should be disabled and its fifo empty. */
431 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
432
433 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
434 SCALER_DISPSTATX_MODE) !=
435 SCALER_DISPSTATX_MODE_DISABLED);
436
437 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
438 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
439 SCALER_DISPSTATX_EMPTY);
440
441 out:
442 drm_dev_exit(idx);
443 }
444
vc4_hvs_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)445 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
446 {
447 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
448 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
449 struct drm_device *dev = crtc->dev;
450 struct vc4_dev *vc4 = to_vc4_dev(dev);
451 struct drm_plane *plane;
452 unsigned long flags;
453 const struct drm_plane_state *plane_state;
454 u32 dlist_count = 0;
455 int ret;
456
457 /* The pixelvalve can only feed one encoder (and encoders are
458 * 1:1 with connectors.)
459 */
460 if (hweight32(crtc_state->connector_mask) > 1)
461 return -EINVAL;
462
463 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
464 dlist_count += vc4_plane_dlist_size(plane_state);
465
466 dlist_count++; /* Account for SCALER_CTL0_END. */
467
468 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
469 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
470 dlist_count);
471 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
472 if (ret)
473 return ret;
474
475 return 0;
476 }
477
vc4_hvs_install_dlist(struct drm_crtc * crtc)478 static void vc4_hvs_install_dlist(struct drm_crtc *crtc)
479 {
480 struct drm_device *dev = crtc->dev;
481 struct vc4_dev *vc4 = to_vc4_dev(dev);
482 struct vc4_hvs *hvs = vc4->hvs;
483 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
484 int idx;
485
486 if (!drm_dev_enter(dev, &idx))
487 return;
488
489 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
490 vc4_state->mm.start);
491
492 drm_dev_exit(idx);
493 }
494
vc4_hvs_update_dlist(struct drm_crtc * crtc)495 static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
496 {
497 struct drm_device *dev = crtc->dev;
498 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
499 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
500 unsigned long flags;
501
502 if (crtc->state->event) {
503 crtc->state->event->pipe = drm_crtc_index(crtc);
504
505 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
506
507 spin_lock_irqsave(&dev->event_lock, flags);
508
509 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) {
510 vc4_crtc->event = crtc->state->event;
511 crtc->state->event = NULL;
512 }
513
514 spin_unlock_irqrestore(&dev->event_lock, flags);
515 }
516
517 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
518 vc4_crtc->current_dlist = vc4_state->mm.start;
519 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
520 }
521
vc4_hvs_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)522 void vc4_hvs_atomic_begin(struct drm_crtc *crtc,
523 struct drm_atomic_state *state)
524 {
525 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
526 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
527 unsigned long flags;
528
529 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
530 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel;
531 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
532 }
533
vc4_hvs_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)534 void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
535 struct drm_atomic_state *state)
536 {
537 struct drm_device *dev = crtc->dev;
538 struct vc4_dev *vc4 = to_vc4_dev(dev);
539 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
540 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
541 bool oneshot = vc4_crtc->feeds_txp;
542
543 vc4_hvs_install_dlist(crtc);
544 vc4_hvs_update_dlist(crtc);
545 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot);
546 }
547
vc4_hvs_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)548 void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
549 struct drm_atomic_state *state)
550 {
551 struct drm_device *dev = crtc->dev;
552 struct vc4_dev *vc4 = to_vc4_dev(dev);
553 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
554 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
555 unsigned int chan = vc4_state->assigned_channel;
556
557 vc4_hvs_stop_channel(vc4->hvs, chan);
558 }
559
vc4_hvs_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)560 void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
561 struct drm_atomic_state *state)
562 {
563 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
564 crtc);
565 struct drm_device *dev = crtc->dev;
566 struct vc4_dev *vc4 = to_vc4_dev(dev);
567 struct vc4_hvs *hvs = vc4->hvs;
568 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
569 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
570 unsigned int channel = vc4_state->assigned_channel;
571 struct drm_plane *plane;
572 struct vc4_plane_state *vc4_plane_state;
573 bool debug_dump_regs = false;
574 bool enable_bg_fill = false;
575 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
576 u32 __iomem *dlist_next = dlist_start;
577 unsigned int zpos = 0;
578 bool found = false;
579 int idx;
580
581 if (!drm_dev_enter(dev, &idx)) {
582 vc4_crtc_send_vblank(crtc);
583 return;
584 }
585
586 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
587 goto exit;
588
589 if (debug_dump_regs) {
590 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
591 vc4_hvs_dump_state(hvs);
592 }
593
594 /* Copy all the active planes' dlist contents to the hardware dlist. */
595 do {
596 found = false;
597
598 drm_atomic_crtc_for_each_plane(plane, crtc) {
599 if (plane->state->normalized_zpos != zpos)
600 continue;
601
602 /* Is this the first active plane? */
603 if (dlist_next == dlist_start) {
604 /* We need to enable background fill when a plane
605 * could be alpha blending from the background, i.e.
606 * where no other plane is underneath. It suffices to
607 * consider the first active plane here since we set
608 * needs_bg_fill such that either the first plane
609 * already needs it or all planes on top blend from
610 * the first or a lower plane.
611 */
612 vc4_plane_state = to_vc4_plane_state(plane->state);
613 enable_bg_fill = vc4_plane_state->needs_bg_fill;
614 }
615
616 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
617
618 found = true;
619 }
620
621 zpos++;
622 } while (found);
623
624 writel(SCALER_CTL0_END, dlist_next);
625 dlist_next++;
626
627 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
628
629 if (enable_bg_fill)
630 /* This sets a black background color fill, as is the case
631 * with other DRM drivers.
632 */
633 HVS_WRITE(SCALER_DISPBKGNDX(channel),
634 HVS_READ(SCALER_DISPBKGNDX(channel)) |
635 SCALER_DISPBKGND_FILL);
636
637 /* Only update DISPLIST if the CRTC was already running and is not
638 * being disabled.
639 * vc4_crtc_enable() takes care of updating the dlist just after
640 * re-enabling VBLANK interrupts and before enabling the engine.
641 * If the CRTC is being disabled, there's no point in updating this
642 * information.
643 */
644 if (crtc->state->active && old_state->active) {
645 vc4_hvs_install_dlist(crtc);
646 vc4_hvs_update_dlist(crtc);
647 }
648
649 if (crtc->state->color_mgmt_changed) {
650 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
651
652 if (crtc->state->gamma_lut) {
653 vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
654 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
655 } else {
656 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
657 * in hardware, which is the same as a linear lut that
658 * DRM expects us to use in absence of a user lut.
659 */
660 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
661 }
662 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
663 }
664
665 if (debug_dump_regs) {
666 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
667 vc4_hvs_dump_state(hvs);
668 }
669
670 exit:
671 drm_dev_exit(idx);
672 }
673
vc4_hvs_mask_underrun(struct vc4_hvs * hvs,int channel)674 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
675 {
676 struct vc4_dev *vc4 = hvs->vc4;
677 struct drm_device *drm = &vc4->base;
678 u32 dispctrl;
679 int idx;
680
681 if (!drm_dev_enter(drm, &idx))
682 return;
683
684 dispctrl = HVS_READ(SCALER_DISPCTRL);
685 dispctrl &= ~((vc4->gen == VC4_GEN_5) ?
686 SCALER5_DISPCTRL_DSPEISLUR(channel) :
687 SCALER_DISPCTRL_DSPEISLUR(channel));
688
689 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
690
691 drm_dev_exit(idx);
692 }
693
vc4_hvs_unmask_underrun(struct vc4_hvs * hvs,int channel)694 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
695 {
696 struct vc4_dev *vc4 = hvs->vc4;
697 struct drm_device *drm = &vc4->base;
698 u32 dispctrl;
699 int idx;
700
701 if (!drm_dev_enter(drm, &idx))
702 return;
703
704 dispctrl = HVS_READ(SCALER_DISPCTRL);
705 dispctrl |= ((vc4->gen == VC4_GEN_5) ?
706 SCALER5_DISPCTRL_DSPEISLUR(channel) :
707 SCALER_DISPCTRL_DSPEISLUR(channel));
708
709 HVS_WRITE(SCALER_DISPSTAT,
710 SCALER_DISPSTAT_EUFLOW(channel));
711 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
712
713 drm_dev_exit(idx);
714 }
715
vc4_hvs_report_underrun(struct drm_device * dev)716 static void vc4_hvs_report_underrun(struct drm_device *dev)
717 {
718 struct vc4_dev *vc4 = to_vc4_dev(dev);
719
720 atomic_inc(&vc4->underrun);
721 DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
722 }
723
vc4_hvs_irq_handler(int irq,void * data)724 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
725 {
726 struct drm_device *dev = data;
727 struct vc4_dev *vc4 = to_vc4_dev(dev);
728 struct vc4_hvs *hvs = vc4->hvs;
729 irqreturn_t irqret = IRQ_NONE;
730 int channel;
731 u32 control;
732 u32 status;
733 u32 dspeislur;
734
735 /*
736 * NOTE: We don't need to protect the register access using
737 * drm_dev_enter() there because the interrupt handler lifetime
738 * is tied to the device itself, and not to the DRM device.
739 *
740 * So when the device will be gone, one of the first thing we
741 * will be doing will be to unregister the interrupt handler,
742 * and then unregister the DRM device. drm_dev_enter() would
743 * thus always succeed if we are here.
744 */
745
746 status = HVS_READ(SCALER_DISPSTAT);
747 control = HVS_READ(SCALER_DISPCTRL);
748
749 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
750 dspeislur = (vc4->gen == VC4_GEN_5) ?
751 SCALER5_DISPCTRL_DSPEISLUR(channel) :
752 SCALER_DISPCTRL_DSPEISLUR(channel);
753
754 /* Interrupt masking is not always honored, so check it here. */
755 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
756 control & dspeislur) {
757 vc4_hvs_mask_underrun(hvs, channel);
758 vc4_hvs_report_underrun(dev);
759
760 irqret = IRQ_HANDLED;
761 }
762 }
763
764 /* Clear every per-channel interrupt flag. */
765 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
766 SCALER_DISPSTAT_IRQMASK(1) |
767 SCALER_DISPSTAT_IRQMASK(2));
768
769 return irqret;
770 }
771
vc4_hvs_debugfs_init(struct drm_minor * minor)772 int vc4_hvs_debugfs_init(struct drm_minor *minor)
773 {
774 struct drm_device *drm = minor->dev;
775 struct vc4_dev *vc4 = to_vc4_dev(drm);
776 struct vc4_hvs *hvs = vc4->hvs;
777
778 if (!vc4->hvs)
779 return -ENODEV;
780
781 if (vc4->gen == VC4_GEN_4)
782 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR,
783 minor->debugfs_root,
784 &vc4->load_tracker_enabled);
785
786 drm_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, NULL);
787
788 drm_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, NULL);
789
790 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
791
792 return 0;
793 }
794
__vc4_hvs_alloc(struct vc4_dev * vc4,struct platform_device * pdev)795 struct vc4_hvs *__vc4_hvs_alloc(struct vc4_dev *vc4, struct platform_device *pdev)
796 {
797 struct drm_device *drm = &vc4->base;
798 struct vc4_hvs *hvs;
799
800 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL);
801 if (!hvs)
802 return ERR_PTR(-ENOMEM);
803
804 hvs->vc4 = vc4;
805 hvs->pdev = pdev;
806
807 spin_lock_init(&hvs->mm_lock);
808
809 /* Set up the HVS display list memory manager. We never
810 * overwrite the setup from the bootloader (just 128b out of
811 * our 16K), since we don't want to scramble the screen when
812 * transitioning from the firmware's boot setup to runtime.
813 */
814 hvs->dlist_mem_size = (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END;
815 drm_mm_init(&hvs->dlist_mm,
816 HVS_BOOTLOADER_DLIST_END,
817 hvs->dlist_mem_size);
818
819 /* Set up the HVS LBM memory manager. We could have some more
820 * complicated data structure that allowed reuse of LBM areas
821 * between planes when they don't overlap on the screen, but
822 * for now we just allocate globally.
823 */
824 if (vc4->gen == VC4_GEN_4)
825 /* 48k words of 2x12-bit pixels */
826 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
827 else
828 /* 60k words of 4x12-bit pixels */
829 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
830
831 vc4->hvs = hvs;
832
833 return hvs;
834 }
835
vc4_hvs_bind(struct device * dev,struct device * master,void * data)836 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
837 {
838 struct platform_device *pdev = to_platform_device(dev);
839 struct drm_device *drm = dev_get_drvdata(master);
840 struct vc4_dev *vc4 = to_vc4_dev(drm);
841 struct vc4_hvs *hvs = NULL;
842 int ret;
843 u32 dispctrl;
844 u32 reg, top;
845
846 hvs = __vc4_hvs_alloc(vc4, NULL);
847 if (IS_ERR(hvs))
848 return PTR_ERR(hvs);
849
850 hvs->regs = vc4_ioremap_regs(pdev, 0);
851 if (IS_ERR(hvs->regs))
852 return PTR_ERR(hvs->regs);
853
854 hvs->regset.base = hvs->regs;
855 hvs->regset.regs = hvs_regs;
856 hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
857
858 if (vc4->gen == VC4_GEN_5) {
859 struct rpi_firmware *firmware;
860 struct device_node *node;
861 unsigned int max_rate;
862
863 node = rpi_firmware_find_node();
864 if (!node)
865 return -EINVAL;
866
867 firmware = rpi_firmware_get(node);
868 of_node_put(node);
869 if (!firmware)
870 return -EPROBE_DEFER;
871
872 hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
873 if (IS_ERR(hvs->core_clk)) {
874 dev_err(&pdev->dev, "Couldn't get core clock\n");
875 return PTR_ERR(hvs->core_clk);
876 }
877
878 max_rate = rpi_firmware_clk_get_max_rate(firmware,
879 RPI_FIRMWARE_CORE_CLK_ID);
880 rpi_firmware_put(firmware);
881 if (max_rate >= 550000000)
882 hvs->vc5_hdmi_enable_hdmi_20 = true;
883
884 if (max_rate >= 600000000)
885 hvs->vc5_hdmi_enable_4096by2160 = true;
886
887 hvs->max_core_rate = max_rate;
888
889 ret = clk_prepare_enable(hvs->core_clk);
890 if (ret) {
891 dev_err(&pdev->dev, "Couldn't enable the core clock\n");
892 return ret;
893 }
894 }
895
896 if (vc4->gen == VC4_GEN_4)
897 hvs->dlist = hvs->regs + SCALER_DLIST_START;
898 else
899 hvs->dlist = hvs->regs + SCALER5_DLIST_START;
900
901 /* Upload filter kernels. We only have the one for now, so we
902 * keep it around for the lifetime of the driver.
903 */
904 ret = vc4_hvs_upload_linear_kernel(hvs,
905 &hvs->mitchell_netravali_filter,
906 mitchell_netravali_1_3_1_3_kernel);
907 if (ret)
908 return ret;
909
910 reg = HVS_READ(SCALER_DISPECTRL);
911 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
912 HVS_WRITE(SCALER_DISPECTRL,
913 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
914
915 reg = HVS_READ(SCALER_DISPCTRL);
916 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
917 HVS_WRITE(SCALER_DISPCTRL,
918 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
919
920 reg = HVS_READ(SCALER_DISPEOLN);
921 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
922 HVS_WRITE(SCALER_DISPEOLN,
923 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
924
925 reg = HVS_READ(SCALER_DISPDITHER);
926 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK;
927 HVS_WRITE(SCALER_DISPDITHER,
928 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
929
930 dispctrl = HVS_READ(SCALER_DISPCTRL);
931
932 dispctrl |= SCALER_DISPCTRL_ENABLE;
933 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
934 SCALER_DISPCTRL_DISPEIRQ(1) |
935 SCALER_DISPCTRL_DISPEIRQ(2);
936
937 if (vc4->gen == VC4_GEN_4)
938 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
939 SCALER_DISPCTRL_SLVWREIRQ |
940 SCALER_DISPCTRL_SLVRDEIRQ |
941 SCALER_DISPCTRL_DSPEIEOF(0) |
942 SCALER_DISPCTRL_DSPEIEOF(1) |
943 SCALER_DISPCTRL_DSPEIEOF(2) |
944 SCALER_DISPCTRL_DSPEIEOLN(0) |
945 SCALER_DISPCTRL_DSPEIEOLN(1) |
946 SCALER_DISPCTRL_DSPEIEOLN(2) |
947 SCALER_DISPCTRL_DSPEISLUR(0) |
948 SCALER_DISPCTRL_DSPEISLUR(1) |
949 SCALER_DISPCTRL_DSPEISLUR(2) |
950 SCALER_DISPCTRL_SCLEIRQ);
951 else
952 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
953 SCALER5_DISPCTRL_SLVEIRQ |
954 SCALER5_DISPCTRL_DSPEIEOF(0) |
955 SCALER5_DISPCTRL_DSPEIEOF(1) |
956 SCALER5_DISPCTRL_DSPEIEOF(2) |
957 SCALER5_DISPCTRL_DSPEIEOLN(0) |
958 SCALER5_DISPCTRL_DSPEIEOLN(1) |
959 SCALER5_DISPCTRL_DSPEIEOLN(2) |
960 SCALER5_DISPCTRL_DSPEISLUR(0) |
961 SCALER5_DISPCTRL_DSPEISLUR(1) |
962 SCALER5_DISPCTRL_DSPEISLUR(2) |
963 SCALER_DISPCTRL_SCLEIRQ);
964
965
966 /* Set AXI panic mode.
967 * VC4 panics when < 2 lines in FIFO.
968 * VC5 panics when less than 1 line in the FIFO.
969 */
970 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
971 SCALER_DISPCTRL_PANIC1_MASK |
972 SCALER_DISPCTRL_PANIC2_MASK);
973 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
974 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
975 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
976
977 /* Set AXI panic mode.
978 * VC4 panics when < 2 lines in FIFO.
979 * VC5 panics when less than 1 line in the FIFO.
980 */
981 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK |
982 SCALER_DISPCTRL_PANIC1_MASK |
983 SCALER_DISPCTRL_PANIC2_MASK);
984 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);
985 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);
986 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);
987
988 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
989
990 /* Recompute Composite Output Buffer (COB) allocations for the displays
991 */
992 if (vc4->gen == VC4_GEN_4) {
993 /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
994 * The bottom 2048 pixels are full 32bpp RGBA (intended for the
995 * TXP composing RGBA to memory), whilst the remainder are only
996 * 24bpp RGB.
997 *
998 * Assign 3 lines to channels 1 & 2, and just over 4 lines to
999 * channel 0.
1000 */
1001 #define VC4_COB_SIZE 20736
1002 #define VC4_COB_LINE_WIDTH 2048
1003 #define VC4_COB_NUM_LINES 3
1004 reg = 0;
1005 top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
1006 reg |= (top - 1) << 16;
1007 HVS_WRITE(SCALER_DISPBASE2, reg);
1008 reg = top;
1009 top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
1010 reg |= (top - 1) << 16;
1011 HVS_WRITE(SCALER_DISPBASE1, reg);
1012 reg = top;
1013 top = VC4_COB_SIZE;
1014 reg |= (top - 1) << 16;
1015 HVS_WRITE(SCALER_DISPBASE0, reg);
1016 } else {
1017 /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
1018 * The bottom 4096 pixels are full RGBA (intended for the TXP
1019 * composing RGBA to memory), whilst the remainder are only
1020 * RGB. Addressing is always pixel wide.
1021 *
1022 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
1023 * lines. to channel 0.
1024 */
1025 #define VC5_COB_SIZE 44416
1026 #define VC5_COB_LINE_WIDTH 4096
1027 #define VC5_COB_NUM_LINES 3
1028 reg = 0;
1029 top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
1030 reg |= top << 16;
1031 HVS_WRITE(SCALER_DISPBASE2, reg);
1032 top += 16;
1033 reg = top;
1034 top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
1035 reg |= top << 16;
1036 HVS_WRITE(SCALER_DISPBASE1, reg);
1037 top += 16;
1038 reg = top;
1039 top = VC5_COB_SIZE;
1040 reg |= top << 16;
1041 HVS_WRITE(SCALER_DISPBASE0, reg);
1042 }
1043
1044 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1045 vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
1046 if (ret)
1047 return ret;
1048
1049 return 0;
1050 }
1051
vc4_hvs_unbind(struct device * dev,struct device * master,void * data)1052 static void vc4_hvs_unbind(struct device *dev, struct device *master,
1053 void *data)
1054 {
1055 struct drm_device *drm = dev_get_drvdata(master);
1056 struct vc4_dev *vc4 = to_vc4_dev(drm);
1057 struct vc4_hvs *hvs = vc4->hvs;
1058 struct drm_mm_node *node, *next;
1059
1060 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
1061 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
1062
1063 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm)
1064 drm_mm_remove_node(node);
1065
1066 drm_mm_takedown(&vc4->hvs->dlist_mm);
1067
1068 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm)
1069 drm_mm_remove_node(node);
1070 drm_mm_takedown(&vc4->hvs->lbm_mm);
1071
1072 clk_disable_unprepare(hvs->core_clk);
1073
1074 vc4->hvs = NULL;
1075 }
1076
1077 static const struct component_ops vc4_hvs_ops = {
1078 .bind = vc4_hvs_bind,
1079 .unbind = vc4_hvs_unbind,
1080 };
1081
vc4_hvs_dev_probe(struct platform_device * pdev)1082 static int vc4_hvs_dev_probe(struct platform_device *pdev)
1083 {
1084 return component_add(&pdev->dev, &vc4_hvs_ops);
1085 }
1086
vc4_hvs_dev_remove(struct platform_device * pdev)1087 static void vc4_hvs_dev_remove(struct platform_device *pdev)
1088 {
1089 component_del(&pdev->dev, &vc4_hvs_ops);
1090 }
1091
1092 static const struct of_device_id vc4_hvs_dt_match[] = {
1093 { .compatible = "brcm,bcm2711-hvs" },
1094 { .compatible = "brcm,bcm2835-hvs" },
1095 {}
1096 };
1097
1098 struct platform_driver vc4_hvs_driver = {
1099 .probe = vc4_hvs_dev_probe,
1100 .remove_new = vc4_hvs_dev_remove,
1101 .driver = {
1102 .name = "vc4_hvs",
1103 .of_match_table = vc4_hvs_dt_match,
1104 },
1105 };
1106