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Searched refs:assert (Results 1 – 25 of 208) sorted by relevance

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/drivers/staging/media/atomisp/pci/
Disp2400_input_system_private.h30 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_store()
31 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_store()
41 assert(ID < N_INPUT_SYSTEM_ID); in input_system_reg_load()
42 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); in input_system_reg_load()
52 assert(ID < N_RX_ID); in receiver_reg_store()
53 assert(RX_BASE[ID] != (hrt_address)-1); in receiver_reg_store()
62 assert(ID < N_RX_ID); in receiver_reg_load()
63 assert(RX_BASE[ID] != (hrt_address)-1); in receiver_reg_load()
73 assert(ID < N_RX_ID); in receiver_port_reg_store()
74 assert(port_ID < N_MIPI_PORT_ID); in receiver_port_reg_store()
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Dia_css_isp_params.c95 assert(params); in ia_css_process_anr()
130 assert(params); in ia_css_process_anr2()
165 assert(params); in ia_css_process_bh()
212 assert(params); in ia_css_process_cnr()
247 assert(params); in ia_css_process_crop()
282 assert(params); in ia_css_process_csc()
317 assert(params); in ia_css_process_dp()
350 assert(params); in ia_css_process_bnr()
385 assert(params); in ia_css_process_de()
418 assert(params); in ia_css_process_ecd()
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Dsh_css_param_dvs.c175 assert(frame_res); in generate_dvs_6axis_table()
176 assert(dvs_offset); in generate_dvs_6axis_table()
192 assert(dvs_config_src); in generate_dvs_6axis_table_from_config()
242 assert(dvs_config_src); in copy_dvs_6axis_table()
243 assert(dvs_config_dst); in copy_dvs_6axis_table()
244 assert(dvs_config_src->xcoords_y); in copy_dvs_6axis_table()
245 assert(dvs_config_src->xcoords_uv); in copy_dvs_6axis_table()
246 assert(dvs_config_src->ycoords_y); in copy_dvs_6axis_table()
247 assert(dvs_config_src->ycoords_uv); in copy_dvs_6axis_table()
248 assert(dvs_config_src->width_y == dvs_config_dst->width_y); in copy_dvs_6axis_table()
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Dsh_css_params.c786 assert(params); in convert_allocate_fpntbl()
818 assert(params); in store_fpntbl()
819 assert(ptr != mmgr_NULL); in store_fpntbl()
838 assert(params); in convert_raw_to_fpn()
945 assert(stream); in sh_css_set_black_frame()
946 assert(raw_black_frame); in sh_css_set_black_frame()
1017 assert(stream); in sh_css_params_set_binning_factor()
1039 assert(stream); in sh_css_set_shading_table()
1063 assert(data); in ia_css_params_store_ia_css_host_data()
1064 assert(data->address); in ia_css_params_store_ia_css_host_data()
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Dsh_css_sp.c138 assert(fw); in store_sp_per_frame_data()
181 assert(state); in sh_css_sp_get_debug_state()
200 assert(out_frame); in sh_css_sp_start_binary_copy()
252 assert(out_frame); in sh_css_sp_start_raw_copy()
323 assert(out_frame); in sh_css_sp_start_isys_copy()
401 assert(buf_type < IA_CSS_NUM_BUFFER_TYPE); in sh_css_copy_buffer_attr_to_spbuffer()
407 assert(queue_id < SH_CSS_MAX_NUM_QUEUES); in sh_css_copy_buffer_attr_to_spbuffer()
422 assert(xmem_addr != mmgr_EXCEPTION); in sh_css_copy_buffer_attr_to_spbuffer()
432 assert(frame_in); in sh_css_copy_frame_to_spframe()
630 assert(if_config_index < SH_CSS_MAX_IF_CONFIGS); in sh_css_sp_set_if_configs()
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/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
Dsp_private.h30 assert(ID < N_SP_ID); in sp_ctrl_store()
31 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_store()
40 assert(ID < N_SP_ID); in sp_ctrl_load()
41 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_load()
83 assert(ID < N_SP_ID); in sp_dmem_store()
84 assert(SP_DMEM_BASE[ID] != (hrt_address)-1); in sp_dmem_store()
95 assert(ID < N_SP_ID); in sp_dmem_load()
96 assert(SP_DMEM_BASE[ID] != (hrt_address)-1); in sp_dmem_load()
106 assert(ID < N_SP_ID); in sp_dmem_store_uint8()
107 assert(SP_DMEM_BASE[ID] != (hrt_address)-1); in sp_dmem_store_uint8()
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Dfifo_monitor_private.h37 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_set()
38 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_set()
39 assert(switch_id < N_FIFO_SWITCH); in fifo_switch_set()
51 assert(ID == FIFO_MONITOR0_ID); in fifo_switch_get()
52 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_switch_get()
53 assert(switch_id < N_FIFO_SWITCH); in fifo_switch_get()
64 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_reg_store()
65 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_monitor_reg_store()
75 assert(ID < N_FIFO_MONITOR_ID); in fifo_monitor_reg_load()
76 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); in fifo_monitor_reg_load()
Devent_fifo_private.h29 assert(ID < N_EVENT_ID); in event_wait_for()
30 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_wait_for()
45 assert(ID < N_EVENT_ID); in event_receive_token()
46 assert(event_source_addr[ID] != ((hrt_address) - 1)); in event_receive_token()
53 assert(ID < N_EVENT_ID); in event_send_token()
54 assert(event_sink_addr[ID] != ((hrt_address) - 1)); in event_send_token()
62 assert(ID < N_EVENT_ID); in is_event_pending()
63 assert(event_source_query_addr[ID] != ((hrt_address) - 1)); in is_event_pending()
72 assert(ID < N_EVENT_ID); in can_event_send_token()
73 assert(event_sink_query_addr[ID] != ((hrt_address) - 1)); in can_event_send_token()
Disp_private.h35 assert(ID < N_ISP_ID); in isp_ctrl_store()
36 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_store()
49 assert(ID < N_ISP_ID); in isp_ctrl_load()
50 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); in isp_ctrl_load()
96 assert(ID < N_ISP_ID); in isp_dmem_store()
97 assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); in isp_dmem_store()
112 assert(ID < N_ISP_ID); in isp_dmem_load()
113 assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); in isp_dmem_load()
127 assert(ID < N_ISP_ID); in isp_dmem_store_uint32()
128 assert(ISP_DMEM_BASE[ID] != (hrt_address) - 1); in isp_dmem_store_uint32()
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Dirq.c64 assert(ID < N_IRQ_ID); in irq_clear_all()
65 assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); in irq_clear_all()
91 assert(ID < N_IRQ_ID); in irq_enable_channel()
92 assert(irq_id < IRQ_N_CHANNEL[ID]); in irq_enable_channel()
146 assert(ID < N_IRQ_ID); in irq_disable_channel()
147 assert(irq_id < IRQ_N_CHANNEL[ID]); in irq_disable_channel()
176 assert(ID < N_IRQ_ID); in irq_get_channel_id()
177 assert(irq_id); in irq_get_channel_id()
244 assert(ID < N_IRQ_ID); in cnd_virq_enable_channel()
248 assert(irq_ID != IRQ_NESTING_ID[i]); in cnd_virq_enable_channel()
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Dvmem.c152 assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1); in load_vector()
183 assert(ISP_BAMEM_BASE[ID] != (hrt_address) - 1); in store_vector()
202 assert(ID < N_ISP_ID); in isp_vmem_load()
203 assert((unsigned long)from % ISP_VEC_ALIGN == 0); in isp_vmem_load()
204 assert(elems % ISP_NWAY == 0); in isp_vmem_load()
220 assert(ID < N_ISP_ID); in isp_vmem_store()
221 assert((unsigned long)to % ISP_VEC_ALIGN == 0); in isp_vmem_store()
222 assert(elems % ISP_NWAY == 0); in isp_vmem_store()
241 assert(ID < N_ISP_ID); in isp_vmem_2d_load()
242 assert((unsigned long)from % ISP_VEC_ALIGN == 0); in isp_vmem_2d_load()
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Dgp_device_private.h30 assert(ID < N_GP_DEVICE_ID); in gp_device_reg_store()
31 assert(GP_DEVICE_BASE[ID] != (hrt_address) - 1); in gp_device_reg_store()
32 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_store()
41 assert(ID < N_GP_DEVICE_ID); in gp_device_reg_load()
42 assert(GP_DEVICE_BASE[ID] != (hrt_address)-1); in gp_device_reg_load()
43 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_load()
Dinput_formatter_private.h30 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_reg_store()
31 assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); in input_formatter_reg_store()
32 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_store()
41 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_reg_load()
42 assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); in input_formatter_reg_load()
43 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_load()
Dinput_system.c105 assert(ID < N_RX_ID); in receiver_set_compression()
106 assert(cfg_ID < N_MIPI_COMPRESSOR_CONTEXT); in receiver_set_compression()
107 assert(field_id < N_MIPI_FORMAT_CUSTOM); in receiver_set_compression()
108 assert(ch_id < N_RX_CHANNEL_ID); in receiver_set_compression()
109 assert(comp < N_MIPI_COMPRESSOR_METHODS); in receiver_set_compression()
110 assert(pred < N_MIPI_PREDICTOR_TYPES); in receiver_set_compression()
133 assert(false); in receiver_set_compression()
203 assert(ID < N_RX_ID); in receiver_rst()
216 assert(ID < N_GP_DEVICE_ID); in gp_device_rst()
263 assert(ID < N_GP_DEVICE_ID); in input_selector_cfg_for_sensor()
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Dinput_formatter.c65 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_rst()
84 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_alignment()
93 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_set_fifo_blocking_mode()
107 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_switch_state()
108 assert(state); in input_formatter_get_switch_state()
141 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_state()
142 assert(state); in input_formatter_get_state()
222 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_bin_get_state()
223 assert(state); in input_formatter_bin_get_state()
/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/
Dia_css_dvs.host.c92 assert(config); in convert_coords_to_ispparams()
93 assert(gdc_warp_table); in convert_coords_to_ispparams()
94 assert(gdc_warp_table->address); in convert_coords_to_ispparams()
117 assert(width == num_blocks_x + in convert_coords_to_ispparams()
119 assert(height == num_blocks_y + 1); in convert_coords_to_ispparams()
139 assert(x01 >= xmin); in convert_coords_to_ispparams()
140 assert(x11 >= xmin); in convert_coords_to_ispparams()
142 assert(y10 >= ymin); in convert_coords_to_ispparams()
143 assert(y11 >= ymin); in convert_coords_to_ispparams()
173 assert(s.p0_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); in convert_coords_to_ispparams()
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/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/
Dia_css_sdis2.host.c51 assert(padding >= 0); in ia_css_sdis2_horicoef_vmem_encode()
52 assert(total_bytes <= size); in ia_css_sdis2_horicoef_vmem_encode()
53 assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( in ia_css_sdis2_horicoef_vmem_encode()
76 assert(padding >= 0); in ia_css_sdis2_vertcoef_vmem_encode()
77 assert(total_bytes <= size); in ia_css_sdis2_vertcoef_vmem_encode()
78 assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( in ia_css_sdis2_vertcoef_vmem_encode()
123 assert(stream); in ia_css_get_isp_dvs2_coefficients()
124 assert(hor_coefs_odd_real); in ia_css_get_isp_dvs2_coefficients()
125 assert(hor_coefs_odd_imag); in ia_css_get_isp_dvs2_coefficients()
126 assert(hor_coefs_even_real); in ia_css_get_isp_dvs2_coefficients()
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/drivers/staging/media/atomisp/pci/camera/pipe/src/
Dpipe_binarydesc.c46 assert(pipe); in pipe_binarydesc_get_offline()
47 assert(descr); in pipe_binarydesc_get_offline()
89 assert(pipe); in ia_css_pipe_get_copy_binarydesc()
90 assert(in_info); in ia_css_pipe_get_copy_binarydesc()
116 assert(pipe); in ia_css_pipe_get_vfpp_binarydesc()
117 assert(in_info); in ia_css_pipe_get_vfpp_binarydesc()
172 assert(in_w != 0 && in_h != 0); in binarydesc_calculate_bds_factor()
173 assert(out_w != 0 && out_h != 0); in binarydesc_calculate_bds_factor()
210 assert(pipe); in ia_css_pipe_get_preview_binarydesc()
211 assert(in_info); in ia_css_pipe_get_preview_binarydesc()
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/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_1.0/
Dia_css_sdis.host.c34 assert((int)width >= 0); in fill_row()
35 assert((int)padding >= 0); in fill_row()
57 assert(padding >= 0); in ia_css_sdis_horicoef_vmem_encode()
58 assert(total_bytes <= size); in ia_css_sdis_horicoef_vmem_encode()
59 assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( in ia_css_sdis_horicoef_vmem_encode()
84 assert(padding >= 0); in ia_css_sdis_vertcoef_vmem_encode()
85 assert(total_bytes <= size); in ia_css_sdis_vertcoef_vmem_encode()
86 assert(size % (IA_CSS_DVS_NUM_COEF_TYPES * ISP_VEC_NELEMS * sizeof( in ia_css_sdis_vertcoef_vmem_encode()
127 assert(horizontal_coefficients); in ia_css_get_isp_dis_coefficients()
128 assert(vertical_coefficients); in ia_css_get_isp_dis_coefficients()
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/drivers/staging/media/atomisp/pci/isp/kernels/dpc2/
Dia_css_dpc2.host.c27 assert((from->metric1 >= 0) && (from->metric1 <= METRIC1_ONE_FP)); in ia_css_dpc2_encode()
28 assert((from->metric3 >= 0) && (from->metric3 <= METRIC3_ONE_FP)); in ia_css_dpc2_encode()
29 assert((from->metric2 >= METRIC2_ONE_FP) && in ia_css_dpc2_encode()
31 assert((from->wb_gain_gr > 0) && (from->wb_gain_gr < 16 * WBGAIN_ONE_FP)); in ia_css_dpc2_encode()
32 assert((from->wb_gain_r > 0) && (from->wb_gain_r < 16 * WBGAIN_ONE_FP)); in ia_css_dpc2_encode()
33 assert((from->wb_gain_b > 0) && (from->wb_gain_b < 16 * WBGAIN_ONE_FP)); in ia_css_dpc2_encode()
34 assert((from->wb_gain_gb > 0) && (from->wb_gain_gb < 16 * WBGAIN_ONE_FP)); in ia_css_dpc2_encode()
/drivers/staging/media/atomisp/pci/runtime/rmgr/src/
Drmgr_vbuf.c134 assert(pool); in ia_css_rmgr_init_vbuf()
203 assert(pool); in rmgr_push_handle()
204 assert(pool->recycle); in rmgr_push_handle()
205 assert(pool->handles); in rmgr_push_handle()
206 assert(handle); in rmgr_push_handle()
215 assert(success); in rmgr_push_handle()
230 assert(pool); in rmgr_pop_handle()
231 assert(pool->recycle); in rmgr_pop_handle()
232 assert(pool->handles); in rmgr_pop_handle()
233 assert(handle); in rmgr_pop_handle()
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/drivers/reset/starfive/
Dreset-starfive-jh71x0.c21 void __iomem *assert; member
33 unsigned long id, bool assert) in jh71x0_reset_update() argument
38 void __iomem *reg_assert = data->assert + offset * sizeof(u32); in jh71x0_reset_update()
45 if (!assert) in jh71x0_reset_update()
51 if (assert) in jh71x0_reset_update()
104 .assert = jh71x0_reset_assert,
111 void __iomem *assert, void __iomem *status, in reset_starfive_jh71x0_register() argument
128 data->assert = assert; in reset_starfive_jh71x0_register()
/drivers/reset/
Dreset-imx7.c92 unsigned long id, bool assert) in imx7_reset_set() argument
96 unsigned int value = assert ? bit : 0; in imx7_reset_set()
104 if (!assert) in imx7_reset_set()
109 value = assert ? 0 : bit; in imx7_reset_set()
132 .assert = imx7_reset_assert,
220 unsigned long id, bool assert) in imx8mq_reset_set() argument
224 unsigned int value = assert ? bit : 0; in imx8mq_reset_set()
233 if (!assert) in imx8mq_reset_set()
245 value = assert ? 0 : bit; in imx8mq_reset_set()
268 .assert = imx8mq_reset_assert,
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/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c71 assert(pipeline); in ia_css_pipeline_create()
87 assert(pipe_num < IA_CSS_PIPELINE_NUM_MAX); in ia_css_pipeline_map()
110 assert(pipeline); in ia_css_pipeline_destroy()
134 assert(pipeline); in ia_css_pipeline_start()
202 assert(pipeline); in ia_css_pipeline_request_stop()
238 assert(pipeline); in ia_css_pipeline_clean()
280 assert(pipeline); in ia_css_pipeline_create_and_add_stage()
281 assert(stage_desc); in ia_css_pipeline_create_and_add_stage()
341 assert(pipeline); in ia_css_pipeline_finalize_stages()
358 assert(pipeline); in ia_css_pipeline_get_stage()
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/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/
Dia_css_eed1_8.host.c131 assert(from->dew_enhance_seg_x[j] > -1); in ia_css_eed1_8_vmem_encode()
132 assert(from->dew_enhance_seg_y[j] > -1); in ia_css_eed1_8_vmem_encode()
136 assert(from->dew_enhance_seg_x[j] > from->dew_enhance_seg_x[j - 1]); in ia_css_eed1_8_vmem_encode()
137 assert(from->dew_enhance_seg_y[j] > from->dew_enhance_seg_y[j - 1]); in ia_css_eed1_8_vmem_encode()
140 assert(from->dew_enhance_seg_x[0] == 0); in ia_css_eed1_8_vmem_encode()
141 assert(from->dew_enhance_seg_y[0] == 0); in ia_css_eed1_8_vmem_encode()
148 assert(chgrinv_x[0] == 0); in ia_css_eed1_8_vmem_encode()
149 assert(tcinv_x[0] == 0); in ia_css_eed1_8_vmem_encode()
150 assert(fcinv_x[0] == 0); in ia_css_eed1_8_vmem_encode()
153 assert(chgrinv_x[j] > chgrinv_x[j - 1]); in ia_css_eed1_8_vmem_encode()
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