| /drivers/misc/vmw_vmci/ |
| D | vmci_context.c | 44 static void ctx_signal_notify(struct vmci_ctx *context) in ctx_signal_notify() argument
46 *context->notify = true; in ctx_signal_notify()
49 static void ctx_clear_notify(struct vmci_ctx *context) in ctx_clear_notify() argument
51 *context->notify = false; in ctx_clear_notify()
58 static void ctx_clear_notify_call(struct vmci_ctx *context) in ctx_clear_notify_call() argument
60 if (context->pending_datagrams == 0 && in ctx_clear_notify_call()
61 vmci_handle_arr_get_size(context->pending_doorbell_array) == 0) in ctx_clear_notify_call()
62 ctx_clear_notify(context); in ctx_clear_notify_call()
69 void vmci_ctx_check_signal_notify(struct vmci_ctx *context) in vmci_ctx_check_signal_notify() argument
71 spin_lock(&context->lock); in vmci_ctx_check_signal_notify()
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| D | vmci_route.c | 42 if (VMCI_INVALID_ID == dst->context) in vmci_route()
46 if (VMCI_HYPERVISOR_CONTEXT_ID == dst->context) { in vmci_route()
64 if (VMCI_HOST_CONTEXT_ID == src->context) in vmci_route()
75 if (VMCI_INVALID_ID == src->context && in vmci_route()
77 src->context = vmci_get_context_id(); in vmci_route()
85 if (VMCI_HOST_CONTEXT_ID == dst->context) { in vmci_route()
94 if (src->context == VMCI_HYPERVISOR_CONTEXT_ID) { in vmci_route()
113 if (VMCI_INVALID_ID == src->context) in vmci_route()
114 src->context = vmci_get_context_id(); in vmci_route()
130 if (VMCI_INVALID_ID == src->context) { in vmci_route()
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| /drivers/accel/qaic/ |
| D | sahara.c | 108 static int sahara_find_image(struct sahara_context *context, u32 image_id) in sahara_find_image() argument
112 if (image_id == context->active_image_id) in sahara_find_image()
115 if (context->active_image_id != SAHARA_IMAGE_ID_NONE) { in sahara_find_image()
116 dev_err(&context->mhi_dev->dev, "image id %d is not valid as %d is active\n", in sahara_find_image()
117 image_id, context->active_image_id); in sahara_find_image()
121 if (image_id >= context->table_size || !context->image_table[image_id]) { in sahara_find_image()
122 dev_err(&context->mhi_dev->dev, "request for unknown image: %d\n", image_id); in sahara_find_image()
131 ret = firmware_request_nowarn(&context->firmware, in sahara_find_image()
132 context->image_table[image_id], in sahara_find_image()
133 &context->mhi_dev->dev); in sahara_find_image()
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| /drivers/gpu/drm/etnaviv/ |
| D | etnaviv_mmu.c | 16 static void etnaviv_context_unmap(struct etnaviv_iommu_context *context, in etnaviv_context_unmap() argument
29 unmapped_page = context->global->ops->unmap(context, iova, in etnaviv_context_unmap()
39 static int etnaviv_context_map(struct etnaviv_iommu_context *context, in etnaviv_context_map() argument
55 ret = context->global->ops->map(context, iova, paddr, pgsize, in etnaviv_context_map()
67 etnaviv_context_unmap(context, orig_iova, orig_size - size); in etnaviv_context_map()
72 static int etnaviv_iommu_map(struct etnaviv_iommu_context *context, u32 iova, in etnaviv_iommu_map() argument
79 if (!context || !sgt) in etnaviv_iommu_map()
88 ret = etnaviv_context_map(context, da, pa, bytes, prot); in etnaviv_iommu_map()
95 context->flush_seq++; in etnaviv_iommu_map()
100 etnaviv_context_unmap(context, iova, da - iova); in etnaviv_iommu_map()
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| D | etnaviv_iommu.c | 28 to_v1_context(struct etnaviv_iommu_context *context) in to_v1_context() argument
30 return container_of(context, struct etnaviv_iommuv1_context, base); in to_v1_context()
33 static void etnaviv_iommuv1_free(struct etnaviv_iommu_context *context) in etnaviv_iommuv1_free() argument
35 struct etnaviv_iommuv1_context *v1_context = to_v1_context(context); in etnaviv_iommuv1_free()
37 drm_mm_takedown(&context->mm); in etnaviv_iommuv1_free()
39 dma_free_wc(context->global->dev, PT_SIZE, v1_context->pgtable_cpu, in etnaviv_iommuv1_free()
42 context->global->v1.shared_context = NULL; in etnaviv_iommuv1_free()
47 static int etnaviv_iommuv1_map(struct etnaviv_iommu_context *context, in etnaviv_iommuv1_map() argument
51 struct etnaviv_iommuv1_context *v1_context = to_v1_context(context); in etnaviv_iommuv1_map()
62 static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_context *context, in etnaviv_iommuv1_unmap() argument
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| D | etnaviv_iommu_v2.c | 42 to_v2_context(struct etnaviv_iommu_context *context) in to_v2_context() argument
44 return container_of(context, struct etnaviv_iommuv2_context, base); in to_v2_context()
47 static void etnaviv_iommuv2_free(struct etnaviv_iommu_context *context) in etnaviv_iommuv2_free() argument
49 struct etnaviv_iommuv2_context *v2_context = to_v2_context(context); in etnaviv_iommuv2_free()
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
64 clear_bit(v2_context->id, context->global->v2.pta_alloc); in etnaviv_iommuv2_free()
92 static int etnaviv_iommuv2_map(struct etnaviv_iommu_context *context, in etnaviv_iommuv2_map() argument
96 struct etnaviv_iommuv2_context *v2_context = to_v2_context(context); in etnaviv_iommuv2_map()
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| /drivers/gpu/drm/tegra/ |
| D | uapi.c | 31 static void tegra_drm_channel_context_close(struct tegra_drm_context *context) in tegra_drm_channel_context_close() argument
36 if (context->memory_context) in tegra_drm_channel_context_close()
37 host1x_memory_context_put(context->memory_context); in tegra_drm_channel_context_close()
39 xa_for_each(&context->mappings, id, mapping) in tegra_drm_channel_context_close()
42 xa_destroy(&context->mappings); in tegra_drm_channel_context_close()
44 host1x_channel_put(context->channel); in tegra_drm_channel_context_close()
46 kfree(context); in tegra_drm_channel_context_close()
51 struct tegra_drm_context *context; in tegra_drm_uapi_close_file() local
55 xa_for_each(&file->contexts, id, context) in tegra_drm_uapi_close_file()
56 tegra_drm_channel_context_close(context); in tegra_drm_uapi_close_file()
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| D | submit.c | 26 #define SUBMIT_ERR(context, fmt, ...) \ argument
27 dev_err_ratelimited(context->client->base.dev, \
146 tegra_drm_mapping_get(struct tegra_drm_context *context, u32 id) in tegra_drm_mapping_get() argument
150 xa_lock(&context->mappings); in tegra_drm_mapping_get()
152 mapping = xa_load(&context->mappings, id); in tegra_drm_mapping_get()
156 xa_unlock(&context->mappings); in tegra_drm_mapping_get()
180 struct tegra_drm_context *context, in submit_copy_gather_data() argument
187 SUBMIT_ERR(context, "gather_data_words cannot be zero"); in submit_copy_gather_data()
192 SUBMIT_ERR(context, "gather_data_words is too large"); in submit_copy_gather_data()
198 SUBMIT_ERR(context, "failed to allocate memory for bo info"); in submit_copy_gather_data()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 183 static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
276 struct dc_state *context, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
284 …enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context-… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
291 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
293 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
297 dcn32_subvp_in_use(dc, context)) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
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| /drivers/platform/x86/intel/int1092/ |
| D | intel_sar.c | 38 static void update_sar_data(struct wwan_sar_context *context) in update_sar_data() argument
41 &context->config_data[context->reg_value]; in update_sar_data()
44 context->sar_data.device_mode < config->total_dev_mode) { in update_sar_data()
48 if (context->sar_data.device_mode == in update_sar_data()
53 context->sar_data.antennatable_index = dev_mode->antennatable_index; in update_sar_data()
54 context->sar_data.bandtable_index = dev_mode->bandtable_index; in update_sar_data()
55 context->sar_data.sartable_index = dev_mode->sartable_index; in update_sar_data()
77 static acpi_status parse_package(struct wwan_sar_context *context, union acpi_object *item) in parse_package() argument
89 data = &context->config_data[reg]; in parse_package()
130 struct wwan_sar_context *context = dev_get_drvdata(&device->dev); in sar_get_device_mode() local
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | en_resources.c | 42 int user_prio, struct mlx4_qp_context *context) in mlx4_en_fill_qp_context() argument
47 memset(context, 0, sizeof(*context)); in mlx4_en_fill_qp_context()
48 context->flags = cpu_to_be32(7 << 16 | rss << MLX4_RSS_QPC_FLAG_OFFSET); in mlx4_en_fill_qp_context()
49 context->pd = cpu_to_be32(mdev->priv_pdn); in mlx4_en_fill_qp_context()
50 context->mtu_msgmax = 0xff; in mlx4_en_fill_qp_context()
52 context->rq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); in mlx4_en_fill_qp_context()
54 context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); in mlx4_en_fill_qp_context()
56 context->params2 |= cpu_to_be32(MLX4_QP_BIT_FPP); in mlx4_en_fill_qp_context()
59 context->sq_size_stride = ilog2(TXBB_SIZE) - 4; in mlx4_en_fill_qp_context()
61 context->usr_page = cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, in mlx4_en_fill_qp_context()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 365 void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) in dcn30_fpu_update_soc_for_wm_a() argument
371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
380 struct dc *dc, struct dc_state *context, in dcn30_fpu_calculate_wm_and_dlg() argument
385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
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| /drivers/net/ethernet/qlogic/qed/ |
| D | qed_nvmetcp_fw_funcs.c | 129 init_nvmetcp_task_params(struct e5_nvmetcp_task_context *context, in init_nvmetcp_task_params() argument
133 context->ystorm_st_context.state.cccid = task_params->host_cccid; in init_nvmetcp_task_params()
134 SET_FIELD(context->ustorm_st_context.error_flags, USTORM_NVMETCP_TASK_ST_CTX_NVME_TCP, 1); in init_nvmetcp_task_params()
135 context->ustorm_st_context.nvme_tcp_opaque_lo = cpu_to_le32(task_params->opq.lo); in init_nvmetcp_task_params()
136 context->ustorm_st_context.nvme_tcp_opaque_hi = cpu_to_le32(task_params->opq.hi); in init_nvmetcp_task_params()
145 struct e5_nvmetcp_task_context *context = task_params->context; in init_default_nvmetcp_task() local
146 const u8 val_byte = context->mstorm_ag_context.cdu_validation; in init_default_nvmetcp_task()
149 memset(context, 0, sizeof(*context)); in init_default_nvmetcp_task()
150 init_nvmetcp_task_params(context, task_params, in init_default_nvmetcp_task()
159 context->ystorm_st_context.pdu_hdr.task_hdr.reg[dw_index] = in init_default_nvmetcp_task()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource_helpers.c | 92 struct dc_state *context) in dcn32_helper_calculate_num_ways_for_subvp() argument
94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
108 struct dc_state *context) in dcn32_merge_pipes_for_subvp() argument
114 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
154 struct dc_state *context) in dcn32_all_pipes_have_stream_and_plane() argument
159 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
171 struct dc_state *context) in dcn32_subvp_in_use() argument
176 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
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| /drivers/usb/image/ |
| D | microtek.c | 191 MTS_DEBUG("transfer = 0x%x context = 0x%x\n",(int)transfer,(int)context ); \
192 …MTS_DEBUG("status = 0x%x data-length = 0x%x sent = 0x%x\n",transfer->status,(int)context->data_len…
193 mts_debug_dump(context->instance);\
208 struct mts_transfer_context* context = (struct mts_transfer_context*)transfer->context; \
379 context->instance->usb_dev, in mts_int_submit_urb()
384 context in mts_int_submit_urb()
390 set_host_byte(context->srb, DID_ERROR); in mts_int_submit_urb()
401 if ( likely(context->final_callback != NULL) ) in mts_transfer_cleanup()
402 context->final_callback(context->srb); in mts_transfer_cleanup()
409 context->srb->result &= MTS_SCSI_ERR_MASK; in mts_transfer_done()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_wrapper.c | 124 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct… in dml21_calculate_rq_and_dlg_params() argument
134 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
137 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
140 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
142 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
143 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
144 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
158 …num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dm… in dml21_calculate_rq_and_dlg_params()
165 dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); in dml21_calculate_rq_and_dlg_params()
168 dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); in dml21_calculate_rq_and_dlg_params()
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| /drivers/infiniband/hw/hns/ |
| D | hns_roce_cmd.c | 93 struct hns_roce_cmd_context *context = in hns_roce_cmd_event() local
94 &hr_dev->cmd.context[token % hr_dev->cmd.max_cmds]; in hns_roce_cmd_event()
96 if (unlikely(token != context->token)) { in hns_roce_cmd_event()
99 token, context->token); in hns_roce_cmd_event()
103 context->result = (status == HNS_ROCE_CMD_SUCCESS) ? 0 : (-EIO); in hns_roce_cmd_event()
104 context->out_param = out_param; in hns_roce_cmd_event()
105 complete(&context->done); in hns_roce_cmd_event()
113 struct hns_roce_cmd_context *context; in __hns_roce_cmd_mbox_wait() local
120 context = &cmd->context[cmd->free_head]; in __hns_roce_cmd_mbox_wait()
121 cmd->free_head = context->next; in __hns_roce_cmd_mbox_wait()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 454 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) in dcn31_update_soc_for_wm_a() argument
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
465 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) in dcn315_update_soc_for_wm_a() argument
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
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| /drivers/pci/hotplug/ |
| D | acpiphp_glue.c | 50 static void hotplug_event(u32 type, struct acpiphp_context *context);
61 struct acpiphp_context *context; in acpiphp_init_context() local
63 context = kzalloc(sizeof(*context), GFP_KERNEL); in acpiphp_init_context()
64 if (!context) in acpiphp_init_context()
67 context->refcount = 1; in acpiphp_init_context()
68 context->hp.notify = acpiphp_hotplug_notify; in acpiphp_init_context()
69 context->hp.fixup = acpiphp_post_dock_fixup; in acpiphp_init_context()
70 acpi_set_hp_context(adev, &context->hp); in acpiphp_init_context()
71 return context; in acpiphp_init_context()
82 struct acpiphp_context *context; in acpiphp_get_context() local
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| /drivers/gpu/drm/i915/selftests/ |
| D | i915_syncmap.c | 163 static int check_one(struct i915_syncmap **sync, u64 context, u32 seqno) in check_one() argument
167 err = i915_syncmap_set(sync, context, seqno); in check_one()
173 context, (*sync)->height, (*sync)->prefix); in check_one()
179 context); in check_one()
193 if (!i915_syncmap_is_later(sync, context, seqno)) { in check_one()
195 context, seqno); in check_one()
217 u64 context = i915_prandom_u64_state(&prng); in igt_syncmap_one() local
225 err = check_one(&sync, context, in igt_syncmap_one()
238 static int check_leaf(struct i915_syncmap **sync, u64 context, u32 seqno) in check_leaf() argument
242 err = i915_syncmap_set(sync, context, seqno); in check_leaf()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1031 struct dc_state *context, in dcn20_fpu_set_wb_arb_params() argument
1040 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_fpu_set_wb_arb_params()
1041 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipe… in dcn20_fpu_set_wb_arb_params()
1043 …wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / … in dcn20_fpu_set_wb_arb_params()
1046 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) in is_dtbclk_required() argument
1050 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
1052 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
1058 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context) in decide_zstate_support() argument
1065 if (context->res_ctx.pipe_ctx[i].plane_state) in decide_zstate_support()
1082 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { in decide_zstate_support()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_psp_ta.c | 78 *pcontext = &psp->ras_context.context; in set_ta_context_funcs()
154 struct ta_context *context = NULL; in ta_if_load_debugfs_write() local
183 set_ta_context_funcs(psp, ta_type, &context); in ta_if_load_debugfs_write()
195 if (!context->mem_context.shared_buf) { in ta_if_load_debugfs_write()
196 ret = psp_ta_init_shared_buf(psp, &context->mem_context); in ta_if_load_debugfs_write()
204 if (ret || context->resp_status) { in ta_if_load_debugfs_write()
207 ret, context->resp_status); in ta_if_load_debugfs_write()
214 context->ta_type = ta_type; in ta_if_load_debugfs_write()
215 context->bin_desc.fw_version = get_bin_version(ta_bin); in ta_if_load_debugfs_write()
216 context->bin_desc.size_bytes = ta_bin_len; in ta_if_load_debugfs_write()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_utils.c | 169 bool is_dtbclk_required(const struct dc *dc, struct dc_state *context) in is_dtbclk_required() argument
174 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
176 if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
182 void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context) in dml2_copy_clocks_to_dc_state() argument
184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
186 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
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| /drivers/comedi/drivers/ |
| D | comedi_8255.c | 36 unsigned long context; member
38 unsigned long context);
71 unsigned long context = spriv->context; in subdev_8255_insn() local
79 s->state & 0xff, context); in subdev_8255_insn()
82 (s->state >> 8) & 0xff, context); in subdev_8255_insn()
85 (s->state >> 16) & 0xff, context); in subdev_8255_insn()
88 v = spriv->io(dev, 0, I8255_DATA_A_REG, 0, context); in subdev_8255_insn()
89 v |= (spriv->io(dev, 0, I8255_DATA_B_REG, 0, context) << 8); in subdev_8255_insn()
90 v |= (spriv->io(dev, 0, I8255_DATA_C_REG, 0, context) << 16); in subdev_8255_insn()
101 unsigned long context = spriv->context; in subdev_8255_do_config() local
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 92 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) in dce110_get_min_vblank_time_us() argument
97 for (j = 0; j < context->stream_count; j++) { in dce110_get_min_vblank_time_us()
98 struct dc_stream_state *stream = context->streams[j]; in dce110_get_min_vblank_time_us()
120 const struct dc_state *context, in dce110_fill_display_configs() argument
123 struct dc *dc = context->clk_mgr->ctx->dc; in dce110_fill_display_configs()
127 pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); in dce110_fill_display_configs()
132 for (j = 0; j < context->stream_count; j++) { in dce110_fill_display_configs()
135 const struct dc_stream_state *stream = context->streams[j]; in dce110_fill_display_configs()
141 if (stream == context->res_ctx.pipe_ctx[k].stream) { in dce110_fill_display_configs()
142 pipe_ctx = &context->res_ctx.pipe_ctx[k]; in dce110_fill_display_configs()
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