| /drivers/greybus/ |
| D | control.c | 18 static int gb_control_get_version(struct gb_control *control) in gb_control_get_version() argument
20 struct gb_interface *intf = control->connection->intf; in gb_control_get_version()
28 ret = gb_operation_sync(control->connection, in gb_control_get_version()
46 control->protocol_major = response.major; in gb_control_get_version()
47 control->protocol_minor = response.minor; in gb_control_get_version()
55 static int gb_control_get_bundle_version(struct gb_control *control, in gb_control_get_bundle_version() argument
58 struct gb_interface *intf = control->connection->intf; in gb_control_get_bundle_version()
65 ret = gb_operation_sync(control->connection, in gb_control_get_bundle_version()
85 int gb_control_get_bundle_versions(struct gb_control *control) in gb_control_get_bundle_versions() argument
87 struct gb_interface *intf = control->connection->intf; in gb_control_get_bundle_versions()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ras_eeprom.c | 172 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
177 if (!control) in __get_eeprom_i2c_addr()
190 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
199 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
203 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
205 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
208 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
213 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
215 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
220 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
[all …]
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| D | smu_v11_0_i2c.c | 47 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) in smu_v11_0_i2c_set_clock_gating() argument
49 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_set_clock_gating()
76 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) in smu_v11_0_i2c_enable() argument
78 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_enable()
102 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) in smu_v11_0_i2c_clear_status() argument
104 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_clear_status()
113 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) in smu_v11_0_i2c_configure() argument
115 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_configure()
135 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) in smu_v11_0_i2c_set_clock() argument
137 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); in smu_v11_0_i2c_set_clock()
[all …]
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| /drivers/tty/vt/ |
| D | defkeymap.map | 7 # altgr control keycode 83 = Boot
8 # altgr control keycode 111 = Boot
20 control keycode 3 = nul
21 shift control keycode 3 = nul
24 control keycode 4 = Escape
27 control keycode 5 = Control_backslash
30 control keycode 6 = Control_bracketright
33 control keycode 7 = Control_asciicircum
36 control keycode 8 = Control_underscore
39 control keycode 9 = Delete
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| /drivers/pinctrl/renesas/ |
| D | Kconfig | 9 bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
59 This enables pin control drivers for Renesas SuperH and ARM platforms
67 This enables common pin control functionality for EMMA Mobile, R-Car,
75 This enables pin control and GPIO drivers for SH/SH Mobile platforms
84 bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
88 bool "pin control support for R-Car D3" if COMPILE_TEST
92 bool "pin control support for R-Car E2" if COMPILE_TEST
96 bool "pin control support for R-Car E3" if COMPILE_TEST
100 bool "pin control support for R-Car H1" if COMPILE_TEST
104 bool "pin control support for R-Car H2" if COMPILE_TEST
[all …]
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| /drivers/reset/ |
| D | reset-ti-sci.c | 68 struct ti_sci_reset_control *control; in ti_sci_reset_set() local
72 control = idr_find(&data->idr, id); in ti_sci_reset_set()
73 if (!control) in ti_sci_reset_set()
76 mutex_lock(&control->lock); in ti_sci_reset_set()
78 ret = dev_ops->get_device_resets(sci, control->dev_id, &reset_state); in ti_sci_reset_set()
83 reset_state |= control->reset_mask; in ti_sci_reset_set()
85 reset_state &= ~control->reset_mask; in ti_sci_reset_set()
87 ret = dev_ops->set_device_resets(sci, control->dev_id, reset_state); in ti_sci_reset_set()
89 mutex_unlock(&control->lock); in ti_sci_reset_set()
149 struct ti_sci_reset_control *control; in ti_sci_reset_status() local
[all …]
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| D | reset-ti-syscon.c | 70 struct ti_syscon_reset_control *control; in ti_syscon_reset_assert() local
76 control = &data->controls[id]; in ti_syscon_reset_assert()
78 if (control->flags & ASSERT_NONE) in ti_syscon_reset_assert()
81 mask = BIT(control->assert_bit); in ti_syscon_reset_assert()
82 value = (control->flags & ASSERT_SET) ? mask : 0x0; in ti_syscon_reset_assert()
84 return regmap_write_bits(data->regmap, control->assert_offset, mask, value); in ti_syscon_reset_assert()
101 struct ti_syscon_reset_control *control; in ti_syscon_reset_deassert() local
107 control = &data->controls[id]; in ti_syscon_reset_deassert()
109 if (control->flags & DEASSERT_NONE) in ti_syscon_reset_deassert()
112 mask = BIT(control->deassert_bit); in ti_syscon_reset_deassert()
[all …]
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| /drivers/spi/ |
| D | spi-microchip-core.c | 128 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable() local
130 control &= ~CONTROL_ENABLE; in mchp_corespi_disable()
132 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable()
163 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_enable_ints() local
165 control |= INT_ENABLE_MASK; in mchp_corespi_enable_ints()
166 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_enable_ints()
171 u32 control = mchp_corespi_read(spi, REG_CONTROL); in mchp_corespi_disable_ints() local
173 control &= ~INT_ENABLE_MASK; in mchp_corespi_disable_ints()
174 mchp_corespi_write(spi, REG_CONTROL, control); in mchp_corespi_disable_ints()
179 u32 control; in mchp_corespi_set_xfer_size() local
[all …]
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| D | spi-microchip-core-qspi.c | 128 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_set_mode() local
142 control &= ~CONTROL_MODE12_MASK; in mchp_coreqspi_set_mode()
144 control |= CONTROL_MODE12_EX_RO; in mchp_coreqspi_set_mode()
146 control |= CONTROL_MODE12_EX_RW; in mchp_coreqspi_set_mode()
148 control |= CONTROL_MODE12_FULL; in mchp_coreqspi_set_mode()
150 control |= CONTROL_MODE0; in mchp_coreqspi_set_mode()
152 control &= ~(CONTROL_MODE12_MASK | in mchp_coreqspi_set_mode()
156 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_set_mode()
163 u32 control, data; in mchp_coreqspi_read_op() local
168 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
[all …]
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| /drivers/s390/char/ |
| D | defkeymap.map | 135 control keycode 74 = F22
136 control keycode 75 = F23
137 control keycode 76 = F24
138 control keycode 107 = Control_z # PA3
139 control keycode 108 = Control_c # PA1
140 control keycode 109 = KeyboardSignal # Clear
141 control keycode 110 = Control_d # PA2
142 control keycode 122 = F10
143 control keycode 123 = F11 # F11
144 control keycode 124 = Last_Console # F12
[all …]
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| /drivers/staging/iio/frequency/ |
| D | ad9834.c | 74 unsigned short control; member
167 if (st->control & AD9834_MODE) { in ad9834_write()
173 st->control |= AD9834_OPBITEN; in ad9834_write()
175 st->control &= ~AD9834_OPBITEN; in ad9834_write()
177 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); in ad9834_write()
182 st->control |= AD9834_PIN_SW; in ad9834_write()
184 st->control &= ~AD9834_PIN_SW; in ad9834_write()
185 st->data = cpu_to_be16(AD9834_REG_CMD | st->control); in ad9834_write()
191 st->control &= ~(this_attr->address | AD9834_PIN_SW); in ad9834_write()
193 st->control |= this_attr->address; in ad9834_write()
[all …]
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| /drivers/pinctrl/mediatek/ |
| D | Kconfig | 51 bool "MediaTek MT7620 pin control"
58 bool "MediaTek MT7621 pin control"
65 bool "MediaTek MT76X8 pin control"
72 bool "Ralink RT2880 pin control"
79 bool "Ralink RT305X pin control"
86 bool "Ralink RT3883 pin control"
94 bool "MediaTek MT2701 pin control"
101 bool "MediaTek MT7623 pin control with generic binding"
108 bool "MediaTek MT7629 pin control"
115 bool "MediaTek MT8135 pin control"
[all …]
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| /drivers/staging/vc04_services/bcm2835-camera/ |
| D | controls.c | 158 struct vchiq_mmal_port *control; in ctrl_set_rational() local
160 control = &dev->component[COMP_CAMERA]->control; in ctrl_set_rational()
165 return vchiq_mmal_port_parameter_set(dev->instance, control, in ctrl_set_rational()
176 struct vchiq_mmal_port *control; in ctrl_set_value() local
178 control = &dev->component[COMP_CAMERA]->control; in ctrl_set_value()
182 return vchiq_mmal_port_parameter_set(dev->instance, control, in ctrl_set_value()
192 struct vchiq_mmal_port *control; in ctrl_set_iso() local
203 control = &dev->component[COMP_CAMERA]->control; in ctrl_set_iso()
210 return vchiq_mmal_port_parameter_set(dev->instance, control, in ctrl_set_iso()
220 struct vchiq_mmal_port *control; in ctrl_set_value_ev() local
[all …]
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| /drivers/rtc/ |
| D | rtc-m48t35.c | 27 u8 control; member
33 u8 control; member
58 u8 control; in m48t35_read_time() local
67 control = readb(&priv->reg->control); in m48t35_read_time()
68 writeb(control | M48T35_RTC_READ, &priv->reg->control); in m48t35_read_time()
75 writeb(control, &priv->reg->control); in m48t35_read_time()
102 u8 control; in m48t35_set_time() local
132 control = readb(&priv->reg->control); in m48t35_set_time()
133 writeb(control | M48T35_RTC_SET, &priv->reg->control); in m48t35_set_time()
140 writeb(control, &priv->reg->control); in m48t35_set_time()
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| /drivers/pci/ |
| D | ats.c | 232 u16 control, status; in pci_enable_pri() local
262 control = PCI_PRI_CTRL_ENABLE; in pci_enable_pri()
263 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); in pci_enable_pri()
278 u16 control; in pci_disable_pri() local
291 pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control); in pci_disable_pri()
292 control &= ~PCI_PRI_CTRL_ENABLE; in pci_disable_pri()
293 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); in pci_disable_pri()
305 u16 control = PCI_PRI_CTRL_ENABLE; in pci_restore_pri_state() local
319 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); in pci_restore_pri_state()
331 u16 control; in pci_reset_pri() local
[all …]
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| /drivers/platform/x86/intel/pmt/ |
| D | crashlog.c | 67 u32 control = readl(entry->disc_table + CONTROL_OFFSET); in pmt_crashlog_complete() local
70 return !!(control & CRASHLOG_FLAG_TRIGGER_COMPLETE); in pmt_crashlog_complete()
75 u32 control = readl(entry->disc_table + CONTROL_OFFSET); in pmt_crashlog_disabled() local
78 return !!(control & CRASHLOG_FLAG_DISABLE); in pmt_crashlog_disabled()
99 u32 control = readl(entry->disc_table + CONTROL_OFFSET); in pmt_crashlog_set_disable() local
102 control &= ~CRASHLOG_FLAG_TRIGGER_MASK; in pmt_crashlog_set_disable()
105 control |= CRASHLOG_FLAG_DISABLE; in pmt_crashlog_set_disable()
107 control &= ~CRASHLOG_FLAG_DISABLE; in pmt_crashlog_set_disable()
109 writel(control, entry->disc_table + CONTROL_OFFSET); in pmt_crashlog_set_disable()
114 u32 control = readl(entry->disc_table + CONTROL_OFFSET); in pmt_crashlog_set_clear() local
[all …]
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| /drivers/dma/ |
| D | ep93xx_dma.c | 369 static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control) in m2p_set_control() argument
371 writel(control, edmac->regs + M2P_CONTROL); in m2p_set_control()
381 u32 control; in m2p_hw_setup() local
385 control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE in m2p_hw_setup()
387 m2p_set_control(edmac, control); in m2p_hw_setup()
402 u32 control; in m2p_hw_synchronize() local
405 control = readl(edmac->regs + M2P_CONTROL); in m2p_hw_synchronize()
406 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT); in m2p_hw_synchronize()
407 m2p_set_control(edmac, control); in m2p_hw_synchronize()
451 u32 control = readl(edmac->regs + M2P_CONTROL); in m2p_hw_submit() local
[all …]
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| /drivers/ata/ |
| D | pata_oldpiix.c | 70 int control = 0; in oldpiix_set_piomode() local
86 control |= 1; /* TIME */ in oldpiix_set_piomode()
88 control |= 2; /* IE */ in oldpiix_set_piomode()
92 control |= 4; /* PPE */ in oldpiix_set_piomode()
102 idetm_data |= control; in oldpiix_set_piomode()
105 idetm_data |= (control << 4); in oldpiix_set_piomode()
146 unsigned int control; in oldpiix_set_dmamode() local
154 control = 3; /* IORDY|TIME0 */ in oldpiix_set_dmamode()
157 control |= 4; /* PPE enable */ in oldpiix_set_dmamode()
164 control |= 8; /* PIO cycles in PIO0 */ in oldpiix_set_dmamode()
[all …]
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| /drivers/thermal/ |
| D | dove_thermal.c | 39 void __iomem *control; member
48 reg = readl_relaxed(priv->control); in dove_init_sensor()
61 writel(reg, priv->control); in dove_init_sensor()
64 reg = readl_relaxed(priv->control); in dove_init_sensor()
65 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); in dove_init_sensor()
66 writel(reg, priv->control); in dove_init_sensor()
93 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); in dove_get_temp()
132 priv->control = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); in dove_thermal_probe()
133 if (IS_ERR(priv->control)) in dove_thermal_probe()
134 return PTR_ERR(priv->control); in dove_thermal_probe()
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| /drivers/leds/ |
| D | leds-sun50i-a100.c | 120 u32 control; in sun50i_a100_ledc_pio_xfer() local
133 control = readl(priv->base + LEDC_INT_CTRL_REG); in sun50i_a100_ledc_pio_xfer()
134 control |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; in sun50i_a100_ledc_pio_xfer()
135 writel(control, priv->base + LEDC_INT_CTRL_REG); in sun50i_a100_ledc_pio_xfer()
139 control = readl(priv->base + LEDC_INT_CTRL_REG); in sun50i_a100_ledc_pio_xfer()
140 control &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; in sun50i_a100_ledc_pio_xfer()
141 writel(control, priv->base + LEDC_INT_CTRL_REG); in sun50i_a100_ledc_pio_xfer()
148 u32 control; in sun50i_a100_ledc_start_xfer() local
161 control = FIELD_PREP(LEDC_DMA_CTRL_REG_DMA_EN, use_dma) | in sun50i_a100_ledc_start_xfer()
163 writel(control, priv->base + LEDC_DMA_CTRL_REG); in sun50i_a100_ledc_start_xfer()
[all …]
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table_helper.c | 175 struct bp_encoder_control *control, in dal_cmd_table_helper_assign_control_parameter() argument
184 if ((control->transmitter == TRANSMITTER_UNIPHY_B) || in dal_cmd_table_helper_assign_control_parameter()
185 (control->transmitter == TRANSMITTER_UNIPHY_D) || in dal_cmd_table_helper_assign_control_parameter()
186 (control->transmitter == TRANSMITTER_UNIPHY_F)) { in dal_cmd_table_helper_assign_control_parameter()
201 (uint8_t)(h->transmitter_bp_to_atom(control->transmitter)); in dal_cmd_table_helper_assign_control_parameter()
204 ctrl_param->ucAction = h->encoder_action_to_atom(control->action); in dal_cmd_table_helper_assign_control_parameter()
205 ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10)); in dal_cmd_table_helper_assign_control_parameter()
208 control->signal, control->enable_dp_audio)); in dal_cmd_table_helper_assign_control_parameter()
209 ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number); in dal_cmd_table_helper_assign_control_parameter()
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| /drivers/staging/greybus/ |
| D | audio_topology.c | 52 struct gbaudio_control *control; in gbaudio_map_controlid() local
57 list_for_each_entry(control, &module->ctl_list, list) { in gbaudio_map_controlid()
58 if (control->id == control_id) { in gbaudio_map_controlid()
60 return control->name; in gbaudio_map_controlid()
61 if (index >= control->items) in gbaudio_map_controlid()
63 return control->texts[index]; in gbaudio_map_controlid()
66 list_for_each_entry(control, &module->widget_ctl_list, list) { in gbaudio_map_controlid()
67 if (control->id == control_id) { in gbaudio_map_controlid()
69 return control->name; in gbaudio_map_controlid()
70 if (index >= control->items) in gbaudio_map_controlid()
[all …]
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| /drivers/platform/x86/intel/uncore-frequency/ |
| D | uncore-frequency-tpmi.c | 89 u64 control; in read_control_freq() local
91 control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX); in read_control_freq()
93 *value = FIELD_GET(UNCORE_MAX_RATIO_MASK, control) * UNCORE_FREQ_KHZ_MULTIPLIER; in read_control_freq()
95 *value = FIELD_GET(UNCORE_MIN_RATIO_MASK, control) * UNCORE_FREQ_KHZ_MULTIPLIER; in read_control_freq()
193 u64 control; in write_eff_lat_ctrl() local
233 control = readq(cluster_info->cluster_base + UNCORE_CONTROL_INDEX); in write_eff_lat_ctrl()
239 control &= ~UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK; in write_eff_lat_ctrl()
240 control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_LOW_THRESHOLD_MASK, val); in write_eff_lat_ctrl()
246 control &= ~UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK; in write_eff_lat_ctrl()
247 control |= FIELD_PREP(UNCORE_EFF_LAT_CTRL_HIGH_THRESHOLD_MASK, val); in write_eff_lat_ctrl()
[all …]
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| /drivers/net/wireless/ti/wl1251/ |
| D | tx.c | 70 struct ieee80211_tx_info *control, u16 fc) in wl1251_tx_control() argument
72 *(u16 *)&tx_hdr->control = 0; in wl1251_tx_control()
74 tx_hdr->control.rate_policy = 0; in wl1251_tx_control()
77 tx_hdr->control.packet_type = 0; in wl1251_tx_control()
80 if ((control->flags & IEEE80211_TX_CTL_NO_ACK) || in wl1251_tx_control()
81 (control->flags & IEEE80211_TX_CTL_INJECTED)) { in wl1251_tx_control()
82 tx_hdr->control.rate_policy = 1; in wl1251_tx_control()
83 tx_hdr->control.ack_policy = 1; in wl1251_tx_control()
86 tx_hdr->control.tx_complete = 1; in wl1251_tx_control()
91 tx_hdr->control.qos = 1; in wl1251_tx_control()
[all …]
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| /drivers/net/phy/ |
| D | dp83848.c | 63 int control, ret; in dp83848_config_intr() local
65 control = phy_read(phydev, DP83848_MICR); in dp83848_config_intr()
66 if (control < 0) in dp83848_config_intr()
67 return control; in dp83848_config_intr()
74 control |= DP83848_MICR_INT_OE; in dp83848_config_intr()
75 control |= DP83848_MICR_INTEN; in dp83848_config_intr()
81 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
83 control &= ~DP83848_MICR_INTEN; in dp83848_config_intr()
84 ret = phy_write(phydev, DP83848_MICR, control); in dp83848_config_intr()
|