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Searched refs:data2 (Results 1 – 25 of 100) sorted by relevance

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/drivers/staging/media/atomisp/pci/runtime/inputfifo/src/
Dinputfifo.c225 const unsigned short *data2, in inputfifo_send_line2() argument
235 assert((data2) || (width2 == 0)); in inputfifo_send_line2()
277 for (i = 0; i < width2; i++, data2++) { in inputfifo_send_line2()
292 data2[0], 0); in inputfifo_send_line2()
295 data2[0], data2[1]); in inputfifo_send_line2()
298 data2++; in inputfifo_send_line2()
301 inputfifo_send_data_b(data2[0]); in inputfifo_send_line2()
303 inputfifo_send_data_a(data2[0]); in inputfifo_send_line2()
472 const unsigned short *data2, in ia_css_inputfifo_send_line() argument
478 assert((data2) || (width2 == 0)); in ia_css_inputfifo_send_line()
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/drivers/net/ethernet/broadcom/bnxt/
Dbnxt_ptp.h40 #define EVENT_DATA2_PPS_EVENT_TYPE(data2) \ argument
41 ((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE)
43 #define EVENT_DATA2_PPS_PIN_NUM(data2) \ argument
44 (((data2) & \
61 #define EVENT_PPS_TS(data2, data1) \ argument
62 (((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\
172 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf117.c201 u32 data[6] = {}, data2[2] = {}; in gf117_grctx_generate_rop_mapping() local
217 data2[0] = (ntpcv << 16); in gf117_grctx_generate_rop_mapping()
218 data2[0] |= (shift << 21); in gf117_grctx_generate_rop_mapping()
219 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); in gf117_grctx_generate_rop_mapping()
221 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); in gf117_grctx_generate_rop_mapping()
231 gr->screen_tile_row_offset | data2[0]); in gf117_grctx_generate_rop_mapping()
232 nvkm_wr32(device, 0x41bfe4, data2[1]); in gf117_grctx_generate_rop_mapping()
Dctxgf100.c1096 u32 data[6] = {}, data2[2] = {}; in gf100_grctx_generate_rop_mapping() local
1112 data2[0] = (ntpcv << 16); in gf100_grctx_generate_rop_mapping()
1113 data2[0] |= (shift << 21); in gf100_grctx_generate_rop_mapping()
1114 data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); in gf100_grctx_generate_rop_mapping()
1116 data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); in gf100_grctx_generate_rop_mapping()
1126 gr->screen_tile_row_offset | data2[0]); in gf100_grctx_generate_rop_mapping()
1127 nvkm_wr32(device, 0x419be4, data2[1]); in gf100_grctx_generate_rop_mapping()
/drivers/gpu/drm/ast/
Dast_post.c510 u32 data, data2, patcnt, loop; in cbr_scan() local
512 data2 = 3; in cbr_scan()
517 data2 &= data; in cbr_scan()
518 if (!data2) in cbr_scan()
526 return data2; in cbr_scan()
545 u32 data, data2, patcnt, loop; in cbr_scan2() local
547 data2 = 0xffff; in cbr_scan2()
552 data2 &= data; in cbr_scan2()
553 if (!data2) in cbr_scan2()
561 return data2; in cbr_scan2()
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/drivers/input/joystick/
Dturbografx.c77 int data1, data2, i; in tgfx_timer() local
86 data2 = parport_read_control(tgfx->pd->port) ^ 0x04; /* CAVEAT parport */ in tgfx_timer()
92 input_report_key(dev, BTN_THUMB, (data2 & TGFX_THUMB )); in tgfx_timer()
93 input_report_key(dev, BTN_THUMB2, (data2 & TGFX_THUMB2 )); in tgfx_timer()
94 input_report_key(dev, BTN_TOP, (data2 & TGFX_TOP )); in tgfx_timer()
95 input_report_key(dev, BTN_TOP2, (data2 & TGFX_TOP2 )); in tgfx_timer()
/drivers/media/usb/gspca/
Dspca508.c1352 int data1, data2; in sd_config() local
1359 data2 = reg_read(gspca_dev, 0x8105); in sd_config()
1361 data2, data1); in sd_config()
1364 data2 = reg_read(gspca_dev, 0x8107); in sd_config()
1366 data2, data1); in sd_config()
Dt613.c87 const u8 data2[9]; member
147 .data2 =
169 .data2 =
191 .data2 =
211 .data2 = {0x40, 0x80, 0xc0, 0x50, 0xa0, 0xf0, 0x53, 0xa6,
643 reg_w_ixbuf(gspca_dev, 0xc7, sensor->data2, sizeof sensor->data2); in sd_init()
665 reg_w_ixbuf(gspca_dev, 0xc7, sensor->data2, sizeof sensor->data2); in sd_init()
Dspca561.c398 __u8 data1, data2; in sd_config() local
407 data2 = gspca_dev->usb_buf[0]; in sd_config()
408 vendor = (data2 << 8) | data1; in sd_config()
412 data2 = gspca_dev->usb_buf[0]; in sd_config()
413 product = (data2 << 8) | data1; in sd_config()
/drivers/gpu/drm/amd/amdgpu/
Dmmhub_v2_3.c529 uint32_t def, data, def1, data1, def2, data2; in mmhub_v2_3_update_medium_grain_light_sleep() local
533 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL); in mmhub_v2_3_update_medium_grain_light_sleep()
542 data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | in mmhub_v2_3_update_medium_grain_light_sleep()
554 data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | in mmhub_v2_3_update_medium_grain_light_sleep()
565 if (def2 != data2) in mmhub_v2_3_update_medium_grain_light_sleep()
566 WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL, data2); in mmhub_v2_3_update_medium_grain_light_sleep()
585 int data, data1, data2, data3; in mmhub_v2_3_get_clockgating() local
592 data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL); in mmhub_v2_3_get_clockgating()
608 && !(data2 & (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | in mmhub_v2_3_get_clockgating()
Damdgpu_vf_error.c54 u32 data1, data2, data3; in amdgpu_vf_error_trans_all() local
79 data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF; in amdgpu_vf_error_trans_all()
82 adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3); in amdgpu_vf_error_trans_all()
Dmxgpu_nv.c124 enum idh_request req, u32 data1, u32 data2, u32 data3) in xgpu_nv_mailbox_trans_msg() argument
147 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2); in xgpu_nv_mailbox_trans_msg()
160 enum idh_request req, u32 data1, u32 data2, u32 data3) in xgpu_nv_send_access_requests_with_param() argument
166 xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3); in xgpu_nv_send_access_requests_with_param()
Dmmhub_v4_1_0.c543 uint32_t def1, data1, def2 = 0, data2 = 0; in mmhub_v4_1_0_update_medium_grain_clock_gating() local
548 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
557 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | in mmhub_v4_1_0_update_medium_grain_clock_gating()
566 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | in mmhub_v4_1_0_update_medium_grain_clock_gating()
577 if (def2 != data2) in mmhub_v4_1_0_update_medium_grain_clock_gating()
578 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
Dmmhub_v3_0.c547 uint32_t def1, data1, def2 = 0, data2 = 0; in mmhub_v3_0_update_medium_grain_clock_gating()
553 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v3_0_update_medium_grain_clock_gating()
566 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | in mmhub_v3_0_update_medium_grain_clock_gating()
583 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | in mmhub_v3_0_update_medium_grain_clock_gating()
598 if (def2 != data2) in mmhub_v3_0_update_medium_grain_clock_gating()
599 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); in mmhub_v3_0_update_medium_grain_clock_gating()
Dmmhub_v1_0.c452 uint32_t def, data, def1, data1, def2 = 0, data2 = 0; in mmhub_v1_0_update_medium_grain_clock_gating() local
458 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); in mmhub_v1_0_update_medium_grain_clock_gating()
473 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | in mmhub_v1_0_update_medium_grain_clock_gating()
490 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | in mmhub_v1_0_update_medium_grain_clock_gating()
508 if (adev->asic_type != CHIP_RAVEN && def2 != data2) in mmhub_v1_0_update_medium_grain_clock_gating()
509 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); in mmhub_v1_0_update_medium_grain_clock_gating()
/drivers/cpufreq/
Dppc_cbe_cpufreq_pmi.c43 pmi_msg.data2 = pmode; in cbe_cpufreq_set_pmode_pmi()
56 ret = pmi_msg.data2; in cbe_cpufreq_set_pmode_pmi()
74 slow_mode = pmi_msg.data2; in cbe_cpufreq_handle_pmi()
/drivers/net/wireless/intel/iwlwifi/fw/
Ddump.c39 u32 data2; /* error-specific data */ member
93 u32 data2; /* error-specific data */ member
161 IWL_ERR(fwrt, "0x%08X | umac data2\n", table.data2); in iwl_fwrt_dump_umac_error_log()
241 IWL_ERR(fwrt, "0x%08X | data2\n", table.data2); in iwl_fwrt_dump_lmac_error_log()
283 u32 data1, data2, data3; member
324 IWL_ERR(fwrt, "0x%08X | tcm data2\n", table.data2); in iwl_fwrt_dump_tcm_error_log()
352 u32 data1, data2, data3; member
397 IWL_ERR(fwrt, "0x%08X | rcm data2\n", table.data2); in iwl_fwrt_dump_rcm_error_log()
/drivers/video/fbdev/sis/
Dinit.c2654 unsigned short data2, data3; in SiS_SetCRT1ModeRegs() local
2723 data2 = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI) >> 1; in SiS_SetCRT1ModeRegs()
2724 if(infoflag & InterlaceMode) data2 >>= 1; in SiS_SetCRT1ModeRegs()
2726 if(data3) data2 /= data3; in SiS_SetCRT1ModeRegs()
2727 if(data2 >= 0x50) { in SiS_SetCRT1ModeRegs()
2748 data2 = SiS_Pr->CSRClock; in SiS_SetCRT1ModeRegs()
2750 data2 = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI); in SiS_SetCRT1ModeRegs()
2751 data2 = SiS_Pr->SiS_VCLKData[data2].CLOCK; in SiS_SetCRT1ModeRegs()
2755 if(data3) data2 *= data3; in SiS_SetCRT1ModeRegs()
2757 data2 = ((unsigned int)(SiS_GetMCLK(SiS_Pr) * 1024)) / data2; in SiS_SetCRT1ModeRegs()
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/drivers/hid/
Dhid-roccat-isku.h70 uint8_t data2; member
84 uint8_t data2; member
Dhid-roccat-koneplus.h73 uint8_t data2; member
109 uint8_t data2; member
Dhid-roccat-kovaplus.h81 uint8_t data2; member
115 uint8_t data2; member
/drivers/net/ethernet/apm/xgene/
Dxgene_enet_sgmac.c334 u32 data, data1, data2, offset; in xgene_sgmac_init() local
391 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); in xgene_sgmac_init()
395 data2 = (data2 & 0xffff0000) | DEF_PAUSE_OFF_THRES; in xgene_sgmac_init()
398 data2 = (data2 & 0xffff) | (DEF_PAUSE_OFF_THRES << 16); in xgene_sgmac_init()
402 xgene_enet_wr_csr(p, pause_off_thres_reg, data2); in xgene_sgmac_init()
/drivers/tee/optee/
Dffa_abi.c325 .data2 = (u32)(global_handle >> 32) in optee_ffa_shm_unregister()
541 u32 w5 = data->data2; in optee_ffa_yielding_call()
568 data->data2 = w5; in optee_ffa_yielding_call()
591 data->data2 = 0; in optee_ffa_yielding_call()
624 .data2 = (u32)(shm->sec_world_id >> 32), in optee_ffa_do_call_with_arg()
691 if (data.data2) in optee_ffa_api_is_compatible()
693 data.data0, data.data1, data.data2); in optee_ffa_api_is_compatible()
722 *sec_caps = data.data2; in optee_ffa_exchange_caps()
/drivers/net/wireless/virtual/
Dmac80211_hwsim.c1758 struct mac80211_hwsim_data *data = hw->priv, *data2; in mac80211_hwsim_tx_frame_no_nl() local
1823 list_for_each_entry(data2, &hwsim_radios, list) { in mac80211_hwsim_tx_frame_no_nl()
1830 if (data == data2) in mac80211_hwsim_tx_frame_no_nl()
1833 if (!data2->started || (data2->idle && !data2->tmp_chan) || in mac80211_hwsim_tx_frame_no_nl()
1834 !hwsim_ps_rx_ok(data2, skb)) in mac80211_hwsim_tx_frame_no_nl()
1837 if (!(data->group & data2->group)) in mac80211_hwsim_tx_frame_no_nl()
1840 if (data->netgroup != data2->netgroup) in mac80211_hwsim_tx_frame_no_nl()
1843 if (!hwsim_chans_compat(chan, data2->tmp_chan) && in mac80211_hwsim_tx_frame_no_nl()
1844 !hwsim_chans_compat(chan, data2->channel)) { in mac80211_hwsim_tx_frame_no_nl()
1846 data2->hw, IEEE80211_IFACE_ITER_NORMAL, in mac80211_hwsim_tx_frame_no_nl()
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/drivers/net/dsa/qca/
Dqca8k-8xxx.c201 __le32 *data2 = (__le32 *)skb->data; in qca8k_rw_reg_ack_handler() local
208 *val = get_unaligned_le32(data2); in qca8k_rw_reg_ack_handler()
210 data2++; in qca8k_rw_reg_ack_handler()
224 __le32 *data2; in qca8k_alloc_mdio_header() local
285 data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN); in qca8k_alloc_mdio_header()
293 put_unaligned_le32(*val, data2); in qca8k_alloc_mdio_header()
294 data2++; in qca8k_alloc_mdio_header()
1651 __le32 *data2; in qca8k_mib_autocast_handler() local
1665 data2 = (__le32 *)skb->data; in qca8k_mib_autocast_handler()
1678 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2); in qca8k_mib_autocast_handler()
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