| /drivers/media/platform/amphion/ |
| D | vpu_dbg.c | 91 inst->out_format.pixfmt, in vpu_dbg_instance()
92 inst->out_format.pixfmt >> 8, in vpu_dbg_instance()
93 inst->out_format.pixfmt >> 16, in vpu_dbg_instance()
94 inst->out_format.pixfmt >> 24, in vpu_dbg_instance()
95 inst->out_format.width, in vpu_dbg_instance()
96 inst->out_format.height, in vpu_dbg_instance()
100 for (i = 0; i < inst->out_format.mem_planes; i++) { in vpu_dbg_instance()
102 vpu_get_fmt_plane_size(&inst->out_format, i), in vpu_dbg_instance()
103 inst->out_format.bytesperline[i]); in vpu_dbg_instance()
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| D | vpu_malone.c | 1279 scode->inst->out_format.width, in vpu_malone_insert_scode_seq()
1280 scode->inst->out_format.height); in vpu_malone_insert_scode_seq()
1299 scode->inst->out_format.width, in vpu_malone_insert_scode_pic()
1300 scode->inst->out_format.height); in vpu_malone_insert_scode_pic()
1363 scode->inst->out_format.width, in vpu_malone_insert_scode_vc1_l_seq()
1364 scode->inst->out_format.height); in vpu_malone_insert_scode_vc1_l_seq()
1411 scode->inst->out_format.width, in vpu_malone_insert_scode_vp8_seq()
1412 scode->inst->out_format.height); in vpu_malone_insert_scode_vp8_seq()
1502 handler = get_scode_handler(scode->inst->out_format.pixfmt); in vpu_malone_insert_scode()
1569 inst->out_format.pixfmt, in vpu_malone_input_frame_data()
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| D | vpu_v4l2.h | 41 return &inst->out_format; in vpu_get_format()
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| D | vpu.h | 260 struct vpu_format out_format; member
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| D | venc.c | 343 s->r.width = inst->out_format.width; in venc_g_selection()
344 s->r.height = inst->out_format.height; in venc_g_selection()
790 src_buf = vpu_find_buf_by_sequence(inst, inst->out_format.type, frame->info.frame_id); in venc_get_one_encoded_frame()
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| D | vpu_v4l2.c | 295 if (!vpu_check_ready(inst, inst->out_format.type)) in vpu_process_output_buffer()
659 inst->out_format.type = src_vq->type; in vpu_m2m_queue_init()
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| D | vpu_msgs.c | 108 info.type = inst->out_format.type; in vpu_session_handle_frame_release()
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| D | vpu_rpc.h | 434 inst->out_format.pixfmt, in vpu_iface_add_scode()
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| D | vdec.c | 908 inst->out_format.width = vdec->codec_info.width; in vdec_init_fmt()
909 inst->out_format.height = vdec->codec_info.height; in vdec_init_fmt()
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| /drivers/gpu/drm/kmb/ |
| D | kmb_plane.c | 355 unsigned int ctrl = 0, val = 0, out_format = 0; in kmb_plane_atomic_update() local
515 out_format |= LCD_OUTF_FORMAT_RGB888; in kmb_plane_atomic_update()
519 out_format |= LCD_OUTF_MIPI_RGB_MODE; in kmb_plane_atomic_update()
520 kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format); in kmb_plane_atomic_update()
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| /drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ |
| D | dcn20_mmhubbub.c | 274 enum dwb_scaler_mode out_format, in mcifwb2_dump_frame() argument
292 dump_info->format = out_format; in mcifwb2_dump_frame()
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| D | dcn20_mmhubbub.h | 501 enum dwb_scaler_mode out_format,
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mcif_wb.h | 99 enum dwb_scaler_mode out_format,
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb.c | 256 REG_UPDATE_2(WBSCL_MODE, WBSCL_MODE, params->out_format, in dwb2_set_scaler()
259 if (params->out_format != dwb_scaler_mode_bypass444) { in dwb2_set_scaler()
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| /drivers/media/i2c/ |
| D | gc0308.c | 422 u8 out_format; member
1072 gc0308->mode.out_format = gc0308_formats[i].regval; in gc0308_set_format()
1136 GENMASK(4, 0), gc0308->mode.out_format, &ret); in gc0308_start_stream()
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| D | ds90ub913.c | 305 static const struct v4l2_mbus_framefmt out_format = { in _ub913_set_routing() local
342 stream_configs->configs[i].fmt = out_format; in _ub913_set_routing()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_types.h | 420 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ member
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| /drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-is-param.h | 628 u32 out_format; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1017 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { in dcn20_populate_dml_writeback_from_context()
2526 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { in dcn201_populate_dml_writeback_from_context_fpu()
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| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| D | dcn20_resource.c | 1668 …if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mod… in dcn20_set_mcif_arb_params()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 9829 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; in dm_set_writeback()
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