| /drivers/staging/media/atomisp/pci/ |
| D | ia_css_isp_params.c | 73 struct ia_css_isp_parameters *params) in ia_css_process_aa() argument
82 … &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; in ia_css_process_aa()
83 t->strength = params->aa_config.strength; in ia_css_process_aa()
93 struct ia_css_isp_parameters *params) in ia_css_process_anr() argument
95 assert(params); in ia_css_process_anr()
109 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], in ia_css_process_anr()
110 ¶ms->anr_config, in ia_css_process_anr()
112 params->isp_params_changed = true; in ia_css_process_anr()
113 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_anr()
128 struct ia_css_isp_parameters *params) in ia_css_process_anr2() argument
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| D | sh_css_params.c | 710 struct ia_css_isp_parameters *params,
721 struct ia_css_isp_parameters *params,
727 struct ia_css_isp_parameters *params,
778 convert_allocate_fpntbl(struct ia_css_isp_parameters *params) in convert_allocate_fpntbl() argument
786 assert(params); in convert_allocate_fpntbl()
788 data_ptr = params->fpn_config.data; in convert_allocate_fpntbl()
789 isp_format_data_size = params->fpn_config.height * params->fpn_config.width * in convert_allocate_fpntbl()
799 for (i = 0; i < params->fpn_config.height; i++) { in convert_allocate_fpntbl()
801 j < params->fpn_config.width; in convert_allocate_fpntbl()
814 store_fpntbl(struct ia_css_isp_parameters *params, ia_css_ptr ptr) in store_fpntbl() argument
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| D | ia_css_isp_params.h | 153 struct ia_css_isp_parameters *params);
158 ia_css_set_dp_config(struct ia_css_isp_parameters *params,
164 ia_css_set_wb_config(struct ia_css_isp_parameters *params,
170 ia_css_set_tnr_config(struct ia_css_isp_parameters *params,
176 ia_css_set_ob_config(struct ia_css_isp_parameters *params,
182 ia_css_set_de_config(struct ia_css_isp_parameters *params,
188 ia_css_set_anr_config(struct ia_css_isp_parameters *params,
194 ia_css_set_anr2_config(struct ia_css_isp_parameters *params,
200 ia_css_set_ce_config(struct ia_css_isp_parameters *params,
206 ia_css_set_ecd_config(struct ia_css_isp_parameters *params,
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| D | dml2_top_optimization.c | 14 …imization_init_function_min_clk_for_latency(const struct optimization_init_function_params *params) in dml2_top_optimization_init_function_min_clk_for_latency() argument
16 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_init_function_min_clk_for_latency()
23 …imization_test_function_min_clk_for_latency(const struct optimization_test_function_params *params) in dml2_top_optimization_test_function_min_clk_for_latency() argument
25 struct dml2_optimization_stage1_state *state = ¶ms->display_config->stage1; in dml2_top_optimization_test_function_min_clk_for_latency()
30 …n_optimize_function_min_clk_for_latency(const struct optimization_optimize_function_params *params) in dml2_top_optimization_optimize_function_min_clk_for_latency() argument
34 if (params->display_config->stage1.min_clk_index_for_latency > 0) { in dml2_top_optimization_optimize_function_min_clk_for_latency()
35 copy_display_configuration_with_meta(params->optimized_display_config, params->display_config); in dml2_top_optimization_optimize_function_min_clk_for_latency()
36 params->optimized_display_config->stage1.min_clk_index_for_latency--; in dml2_top_optimization_optimize_function_min_clk_for_latency()
43 … dml2_top_optimization_test_function_mcache(const struct optimization_test_function_params *params) in dml2_top_optimization_test_function_mcache() argument
45 struct dml2_optimization_test_function_locals *l = params->locals; in dml2_top_optimization_test_function_mcache()
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| D | dml_top_mcache.c | 199 bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissability_in_out *params) in dml2_top_mcache_validate_admissability() argument
201 struct dml2_instance *dml = (struct dml2_instance *)params->dml2_instance; in dml2_top_mcache_validate_admissability()
222 for (plane_index = 0; plane_index < params->display_cfg->num_planes; plane_index++) { in dml2_top_mcache_validate_admissability()
223 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
226 plane = ¶ms->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
227 stream = ¶ms->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
229 …num_dpps = odm_combine_factor = params->cfg_support_info->stream_support_info[plane->stream_index]… in dml2_top_mcache_validate_admissability()
232 …num_dpps = mpc_combine_factor = (unsigned int)params->cfg_support_info->plane_support_info[plane_i… in dml2_top_mcache_validate_admissability()
261 …num_boundaries = params->mcache_allocations[plane_index].num_mcaches_plane0 == 0 ? 0 : params->mca… in dml2_top_mcache_validate_admissability()
262 if ((count_elements_in_span(params->mcache_allocations[plane_index].mcache_x_offsets_plane0, in dml2_top_mcache_validate_admissability()
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| /drivers/media/platform/rockchip/rkisp1/ |
| D | rkisp1-params.c | 93 rkisp1_param_set_bits(struct rkisp1_params *params, u32 reg, u32 bit_mask) in rkisp1_param_set_bits() argument
97 val = rkisp1_read(params->rkisp1, reg); in rkisp1_param_set_bits()
98 rkisp1_write(params->rkisp1, reg, val | bit_mask); in rkisp1_param_set_bits()
102 rkisp1_param_clear_bits(struct rkisp1_params *params, u32 reg, u32 bit_mask) in rkisp1_param_clear_bits() argument
106 val = rkisp1_read(params->rkisp1, reg); in rkisp1_param_clear_bits()
107 rkisp1_write(params->rkisp1, reg, val & ~bit_mask); in rkisp1_param_clear_bits()
111 static void rkisp1_dpcc_config(struct rkisp1_params *params, in rkisp1_dpcc_config() argument
123 mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_DPCC_MODE); in rkisp1_dpcc_config()
126 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_MODE, mode); in rkisp1_dpcc_config()
128 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_OUTPUT_MODE, in rkisp1_dpcc_config()
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| /drivers/media/usb/gspca/ |
| D | cpia1.c | 214 #define FIRMWARE_VERSION(x, y) (sd->params.version.firmwareVersion == (x) && \
215 sd->params.version.firmwareRevision == (y))
355 struct cam_params params; /* camera settings */ member
480 sd->params.version.firmwareVersion = gspca_dev->usb_buf[0]; in do_command()
481 sd->params.version.firmwareRevision = gspca_dev->usb_buf[1]; in do_command()
482 sd->params.version.vcVersion = gspca_dev->usb_buf[2]; in do_command()
483 sd->params.version.vcRevision = gspca_dev->usb_buf[3]; in do_command()
486 sd->params.pnpID.vendor = in do_command()
488 sd->params.pnpID.product = in do_command()
490 sd->params.pnpID.deviceRevision = in do_command()
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table.c | 37 #define EXEC_BIOS_CMD_TABLE(command, params)\ argument
40 (uint32_t *)¶ms, sizeof(params)) == 0)
200 DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0}; in encoder_control_dig1_v1() local
202 bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, ¶ms); in encoder_control_dig1_v1()
204 if (EXEC_BIOS_CMD_TABLE(DIG1EncoderControl, params)) in encoder_control_dig1_v1()
215 DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0}; in encoder_control_dig2_v1() local
217 bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, ¶ms); in encoder_control_dig2_v1()
219 if (EXEC_BIOS_CMD_TABLE(DIG2EncoderControl, params)) in encoder_control_dig2_v1()
230 DIG_ENCODER_CONTROL_PARAMETERS_V3 params = {0}; in encoder_control_digx_v3() local
233 params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */ in encoder_control_digx_v3()
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| /drivers/usb/gadget/function/ |
| D | rndis.c | 70 static rndis_resp_t *rndis_add_response(struct rndis_params *params,
169 static int gen_ndis_query_resp(struct rndis_params *params, u32 OID, u8 *buf, in gen_ndis_query_resp() argument
201 net = params->dev; in gen_ndis_query_resp()
234 *outbuf = cpu_to_le32(params->medium); in gen_ndis_query_resp()
242 *outbuf = cpu_to_le32(params->medium); in gen_ndis_query_resp()
249 if (params->dev) { in gen_ndis_query_resp()
250 *outbuf = cpu_to_le32(params->dev->mtu); in gen_ndis_query_resp()
259 if (params->media_state == RNDIS_MEDIA_STATE_DISCONNECTED) in gen_ndis_query_resp()
262 *outbuf = cpu_to_le32(params->speed); in gen_ndis_query_resp()
269 if (params->dev) { in gen_ndis_query_resp()
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| /drivers/phy/broadcom/ |
| D | phy-brcm-usb-init.c | 141 #define USB_CTRL_MASK_FAMILY(params, reg, field) \ argument
142 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
144 #define USB_CTRL_SET_FAMILY(params, reg, field) \ argument
145 usb_ctrl_set_family(params, USB_CTRL_##reg, \
147 #define USB_CTRL_UNSET_FAMILY(params, reg, field) \ argument
148 usb_ctrl_unset_family(params, USB_CTRL_##reg, \
450 void usb_ctrl_unset_family(struct brcm_usb_init_params *params, in usb_ctrl_unset_family() argument
455 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
456 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
460 void usb_ctrl_set_family(struct brcm_usb_init_params *params, in usb_ctrl_set_family() argument
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| D | phy-brcm-usb-init-synopsys.c | 98 static void usb_mdio_write_7211b0(struct brcm_usb_init_params *params, in usb_mdio_write_7211b0() argument
101 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_write_7211b0()
117 struct brcm_usb_init_params *params, uint8_t addr) in usb_mdio_read_7211b0() argument
119 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_read_7211b0()
134 static void usb2_eye_fix_7211b0(struct brcm_usb_init_params *params) in usb2_eye_fix_7211b0() argument
137 usb_mdio_write_7211b0(params, 0x1f, 0x80a0); in usb2_eye_fix_7211b0()
140 usb_mdio_write_7211b0(params, 0x0a, 0xc6a0); in usb2_eye_fix_7211b0()
143 static void xhci_soft_reset(struct brcm_usb_init_params *params, in xhci_soft_reset() argument
146 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; in xhci_soft_reset()
147 void __iomem *xhci_gbl = params->regs[BRCM_REGS_XHCI_GBL]; in xhci_soft_reset()
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| /drivers/tee/optee/ |
| D | rpc.c | 22 if ((arg->params[0].attr & OPTEE_MSG_ATTR_TYPE_MASK) != in handle_rpc_func_cmd_get_time()
27 arg->params[0].u.value.a = ts.tv_sec; in handle_rpc_func_cmd_get_time()
28 arg->params[0].u.value.b = ts.tv_nsec; in handle_rpc_func_cmd_get_time()
41 struct tee_param *params; in handle_rpc_func_cmd_i2c_transfer() local
58 params = kmalloc_array(arg->num_params, sizeof(struct tee_param), in handle_rpc_func_cmd_i2c_transfer()
60 if (!params) { in handle_rpc_func_cmd_i2c_transfer()
65 if (optee->ops->from_msg_param(optee, params, arg->num_params, in handle_rpc_func_cmd_i2c_transfer()
66 arg->params)) in handle_rpc_func_cmd_i2c_transfer()
70 if (params[i].attr != attr[i]) in handle_rpc_func_cmd_i2c_transfer()
74 adapter = i2c_get_adapter(params[0].u.value.b); in handle_rpc_func_cmd_i2c_transfer()
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| /drivers/net/ethernet/mellanox/mlx5/core/en/ |
| D | params.c | 226 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, in mlx5e_get_linear_rq_headroom() argument
235 if (params->xdp_prog) in mlx5e_get_linear_rq_headroom()
243 static u32 mlx5e_rx_get_linear_sz_xsk(struct mlx5e_params *params, in mlx5e_rx_get_linear_sz_xsk() argument
246 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); in mlx5e_rx_get_linear_sz_xsk()
251 static u32 mlx5e_rx_get_linear_sz_skb(struct mlx5e_params *params, bool no_head_tail_room) in mlx5e_rx_get_linear_sz_skb() argument
253 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); in mlx5e_rx_get_linear_sz_skb()
258 headroom = mlx5e_get_linear_rq_headroom(params, NULL); in mlx5e_rx_get_linear_sz_skb()
264 struct mlx5e_params *params, in mlx5e_rx_get_linear_stride_sz() argument
277 no_head_tail_room = params->xdp_prog && mpwqe && !mlx5e_rx_is_linear_skb(mdev, params, xsk); in mlx5e_rx_get_linear_stride_sz()
283 sz = roundup_pow_of_two(mlx5e_rx_get_linear_sz_skb(params, no_head_tail_room)); in mlx5e_rx_get_linear_stride_sz()
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| D | params.h | 80 int mlx5e_mpwrq_validate_regular(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
81 int mlx5e_mpwrq_validate_xsk(struct mlx5_core_dev *mdev, struct mlx5e_params *params,
83 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
84 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
85 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
87 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params,
90 struct mlx5e_params *params,
93 struct mlx5e_params *params,
96 struct mlx5e_params *params,
99 struct mlx5e_params *params);
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| /drivers/thermal/ |
| D | gov_power_allocator.c | 118 struct power_allocator_params *params = tz->governor_data; in estimate_sustainable_power() local
119 const struct thermal_trip_desc *td = trip_to_trip_desc(params->trip_max); in estimate_sustainable_power()
198 struct power_allocator_params *params, in get_sustainable_power() argument
209 if (sustainable_power != params->sustainable_power) { in get_sustainable_power()
211 params->trip_switch_on, control_temp); in get_sustainable_power()
215 params->sustainable_power = sustainable_power; in get_sustainable_power()
243 struct power_allocator_params *params = tz->governor_data; in pid_controller() local
250 sustainable_power = get_sustainable_power(tz, params, control_temp); in pid_controller()
264 i = mul_frac(tz->tzp->k_i, params->err_integral); in pid_controller()
271 params->err_integral += err; in pid_controller()
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 33 struct link_params *params,
215 static int bnx2x_check_half_open_conn(struct link_params *params,
218 struct link_params *params);
246 static int bnx2x_check_lfa(struct link_params *params) in bnx2x_check_lfa() argument
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
269 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
271 port_mb[params->port].link_status)); in bnx2x_check_lfa()
278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) in bnx2x_check_lfa()
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| /drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/ |
| D | dcn32_mmhubbub.c | 77 struct mcif_warmup_params *params) in mmhubbub32_warmup_mcif() argument
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub32_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub32_warmup_mcif()
91 MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5); in mmhubbub32_warmup_mcif()
104 struct mcif_buf_params *params, in mmhubbub32_config_mcif_buf() argument
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub32_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub32_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub32_config_mcif_buf()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_opp.c | 106 const struct bit_depth_reduction_params *params) in set_truncation() argument
115 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { in set_truncation()
117 if (params->flags.TRUNCATE_DEPTH == 1) in set_truncation()
122 else if (params->flags.TRUNCATE_DEPTH == 2) in set_truncation()
131 if (params->flags.TRUNCATE_ENABLED == 0) in set_truncation()
137 params->flags.TRUNCATE_DEPTH, in set_truncation()
139 params->flags.TRUNCATE_MODE); in set_truncation()
151 const struct bit_depth_reduction_params *params) in dce60_set_truncation() argument
160 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { in dce60_set_truncation()
162 if (params->flags.TRUNCATE_DEPTH == 1) in dce60_set_truncation()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_mmhubbub.c | 77 struct mcif_warmup_params *params) in mmhubbub3_warmup_mcif() argument
80 union large_integer start_address_shift = {.quad_part = params->start_address.quad_part >> 5}; in mmhubbub3_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub3_warmup_mcif()
91 MMHUBBUB_WARMUP_INC_ADDR, params->address_increment >> 5); in mmhubbub3_warmup_mcif()
104 struct mcif_buf_params *params, in mmhubbub3_config_mcif_buf() argument
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
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| /drivers/media/platform/ti/omap3isp/ |
| D | isppreview.c | 150 const struct prev_params *params) in preview_config_luma_enhancement() argument
153 const struct omap3isp_prev_luma *yt = ¶ms->luma; in preview_config_luma_enhancement()
199 const struct prev_params *params) in preview_config_hmed() argument
202 const struct omap3isp_prev_hmed *hmed = ¶ms->hmed; in preview_config_hmed()
234 const struct prev_params *params) in preview_config_cfa() argument
242 const unsigned int *order = cfa_coef_order[prev->params.cfa_order]; in preview_config_cfa()
243 const struct omap3isp_prev_cfa *cfa = ¶ms->cfa; in preview_config_cfa()
270 const struct prev_params *params) in preview_config_chroma_suppression() argument
273 const struct omap3isp_prev_csup *cs = ¶ms->csup; in preview_config_chroma_suppression()
304 const struct prev_params *params) in preview_config_whitebalance() argument
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| /drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ |
| D | dcn20_mmhubbub.c | 77 struct mcif_buf_params *params, in mmhubbub2_config_mcif_buf() argument
83 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
86 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub2_config_mcif_buf()
87 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub2_config_mcif_buf()
93 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
98 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub2_config_mcif_buf()
99 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
104 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub2_config_mcif_buf()
105 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb.c | 72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
78 REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width, in dwb2_config_dwb_cnv()
79 CNV_SOURCE_HEIGHT, params->cnv_params.src_height); in dwb2_config_dwb_cnv()
82 if (params->cnv_params.crop_en) { in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
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| /drivers/staging/media/atomisp/pci/runtime/isp_param/src/ |
| D | isp_param.c | 30 mem_init->params[pclass][mem].address = address; in ia_css_isp_param_set_mem_init()
31 mem_init->params[pclass][mem].size = (uint32_t)size; in ia_css_isp_param_set_mem_init()
41 mem_init->params[pclass][mem].address = address; in ia_css_isp_param_set_css_mem_init()
42 mem_init->params[pclass][mem].size = (uint32_t)size; in ia_css_isp_param_set_css_mem_init()
52 mem_init->params[pclass][mem].address = address; in ia_css_isp_param_set_isp_mem_init()
53 mem_init->params[pclass][mem].size = (uint32_t)size; in ia_css_isp_param_set_isp_mem_init()
63 return &mem_init->params[pclass][mem]; in ia_css_isp_param_get_mem_init()
72 return &mem_init->params[pclass][mem]; in ia_css_isp_param_get_css_mem_init()
81 return &mem_init->params[pclass][mem]; in ia_css_isp_param_get_isp_mem_init()
93 memset(isp_mem_if->params[pclass], 0, sizeof(isp_mem_if->params[pclass])); in ia_css_init_memory_interface()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_hw_sequencer.c | 562 struct drr_params *params) in set_drr_and_clear_adjust_pending() argument
568 pipe_ctx->stream_res.tg, params); in set_drr_and_clear_adjust_pending()
616 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; in hwss_build_fast_sequence()
617 …block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_… in hwss_build_fast_sequence()
622 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
623 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
624 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = in hwss_build_fast_sequence()
630 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()
631 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()
632 …block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_… in hwss_build_fast_sequence()
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| /drivers/soundwire/ |
| D | generic_bandwidth_allocation.c | 40 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
45 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
46 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
47 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
85 struct sdw_group_params *params, in sdw_compute_master_ports() argument
91 struct sdw_bus_params *b_params = &bus->params; in sdw_compute_master_ports()
95 rate = m_rt->stream->params.rate; in sdw_compute_master_ports()
96 bps = m_rt->stream->params.bps; in sdw_compute_master_ports()
98 sample_int = (bus->params.curr_dr_freq / rate); in sdw_compute_master_ports()
100 if (rate != params->rate) in sdw_compute_master_ports()
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