| /drivers/bus/ |
| D | omap_l3_smx.h | 29 static const u64 shift = 1; variable
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
32 #define L3_STATUS_0_MPUIA_RSP (shift << 1)
33 #define L3_STATUS_0_MPUIA_INBAND (shift << 2)
34 #define L3_STATUS_0_IVAIA_BRST (shift << 6)
35 #define L3_STATUS_0_IVAIA_RSP (shift << 7)
36 #define L3_STATUS_0_IVAIA_INBAND (shift << 8)
37 #define L3_STATUS_0_SGXIA_BRST (shift << 9)
38 #define L3_STATUS_0_SGXIA_RSP (shift << 10)
39 #define L3_STATUS_0_SGXIA_MERROR (shift << 11)
[all …]
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| D | da8xx-mstpri.c | 55 int shift; member
62 .shift = 0,
67 .shift = 4,
72 .shift = 16,
77 .shift = 20,
82 .shift = 0,
87 .shift = 4,
92 .shift = 8,
97 .shift = 12,
102 .shift = 16,
[all …]
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| /drivers/clk/imx/ |
| D | clk.h | 118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
133 #define imx_clk_gate(name, parent, reg, shift) \ argument
134 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
136 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
[all …]
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| /drivers/memory/tegra/ |
| D | tegra114.c | 21 .shift = 0,
37 .shift = 0,
53 .shift = 0,
69 .shift = 16,
85 .shift = 16,
101 .shift = 0,
117 .shift = 0,
133 .shift = 0,
149 .shift = 0,
165 .shift = 16,
[all …]
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| D | tegra210.c | 26 .shift = 0,
42 .shift = 0,
58 .shift = 16,
74 .shift = 16,
90 .shift = 0,
106 .shift = 0,
122 .shift = 0,
138 .shift = 0,
154 .shift = 0,
170 .shift = 0,
[all …]
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| D | tegra124.c | 22 .shift = 0,
38 .shift = 0,
54 .shift = 0,
70 .shift = 16,
86 .shift = 16,
102 .shift = 0,
118 .shift = 0,
134 .shift = 0,
150 .shift = 0,
166 .shift = 0,
[all …]
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| D | tegra30.c | 43 .shift = 0,
60 .shift = 0,
77 .shift = 0,
94 .shift = 16,
111 .shift = 16,
128 .shift = 0,
145 .shift = 0,
162 .shift = 16,
179 .shift = 16,
196 .shift = 0,
[all …]
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| /drivers/mfd/ |
| D | atmel-smc.c | 94 unsigned int shift, unsigned int ncycles) in atmel_smc_cs_conf_set_timing() argument
99 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT && in atmel_smc_cs_conf_set_timing()
100 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT && in atmel_smc_cs_conf_set_timing()
101 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT && in atmel_smc_cs_conf_set_timing()
102 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT && in atmel_smc_cs_conf_set_timing()
103 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT) in atmel_smc_cs_conf_set_timing()
113 conf->timings &= ~GENMASK(shift + 3, shift); in atmel_smc_cs_conf_set_timing()
114 conf->timings |= val << shift; in atmel_smc_cs_conf_set_timing()
136 unsigned int shift, unsigned int ncycles) in atmel_smc_cs_conf_set_setup() argument
141 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && in atmel_smc_cs_conf_set_setup()
[all …]
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| /drivers/clk/meson/ |
| D | parm.h | 14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
26 u8 shift; member
35 return PARM_GET(p->width, p->shift, val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
42 val << p->shift); in meson_parm_write()
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| D | s4-pll.c | 33 .shift = 28,
38 .shift = 0,
43 .shift = 0,
48 .shift = 10,
53 .shift = 31,
58 .shift = 29,
75 .shift = 16,
272 .shift = 28,
277 .shift = 0,
282 .shift = 10,
[all …]
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| D | axg.c | 32 .shift = 30,
37 .shift = 0,
42 .shift = 9,
47 .shift = 0,
52 .shift = 31,
57 .shift = 29,
74 .shift = 16,
96 .shift = 30,
101 .shift = 0,
106 .shift = 9,
[all …]
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| /drivers/mtd/maps/ |
| D | physmap-bt1-rom.c | 33 unsigned int shift; in bt1_rom_map_read() local
38 shift = (uintptr_t)src & 0x3; in bt1_rom_map_read()
39 data = readl_relaxed(src - shift); in bt1_rom_map_read()
40 if (!shift) { in bt1_rom_map_read()
44 ret.x[0] = data >> (shift * BITS_PER_BYTE); in bt1_rom_map_read()
47 shift = 4 - shift; in bt1_rom_map_read()
48 if (ofs + shift >= map->size) in bt1_rom_map_read()
51 data = readl_relaxed(src + shift); in bt1_rom_map_read()
52 ret.x[0] |= data << (shift * BITS_PER_BYTE); in bt1_rom_map_read()
62 unsigned int shift, chunk; in bt1_rom_map_copy_from() local
[all …]
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| /drivers/soc/fsl/qe/ |
| D | ucc.c | 89 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
95 *shift = 16 - 8 * (ucc_num & 2); in get_cmxucr_reg()
102 unsigned int shift; in ucc_mux_set_grant_tsa_bkpt() local
108 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
111 qe_setbits_be32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
113 qe_clrbits_be32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
124 unsigned int shift; in ucc_set_qe_mux_rxtx() local
135 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_set_qe_mux_rxtx()
208 shift += 4; in ucc_set_qe_mux_rxtx()
210 qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, in ucc_set_qe_mux_rxtx()
[all …]
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_qmath.c | 98 s32 qm_shl32(s32 op, int shift) in qm_shl32() argument
103 if (shift > 31) in qm_shl32()
104 shift = 31; in qm_shl32()
105 else if (shift < -31) in qm_shl32()
106 shift = -31; in qm_shl32()
107 if (shift >= 0) { in qm_shl32()
108 for (i = 0; i < shift; i++) in qm_shl32()
111 result = result >> (-shift); in qm_shl32()
123 s16 qm_shl16(s16 op, int shift) in qm_shl16() argument
128 if (shift > 15) in qm_shl16()
[all …]
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| /drivers/gpio/ |
| D | gpio-tangier.c | 77 u8 shift = offset % 32; in gpio_reg_and_bit() local
79 *bit = shift; in gpio_reg_and_bit()
86 u8 shift; in tng_gpio_get() local
88 gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); in tng_gpio_get()
90 return !!(readl(gplr) & BIT(shift)); in tng_gpio_get()
97 u8 shift; in tng_gpio_set() local
99 reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); in tng_gpio_set()
103 writel(BIT(shift), reg); in tng_gpio_set()
111 u8 shift; in tng_gpio_direction_input() local
113 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); in tng_gpio_direction_input()
[all …]
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| /drivers/video/fbdev/core/ |
| D | cfbimgblt.c | 82 u32 color = 0, val, shift; in color_imageblit() local
93 shift = 0; in color_imageblit()
100 shift = start_index; in color_imageblit()
109 val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask); in color_imageblit()
110 if (shift >= null_bits) { in color_imageblit()
113 val = (shift == null_bits) ? 0 : in color_imageblit()
114 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
116 shift += bpp; in color_imageblit()
117 shift &= (32 - 1); in color_imageblit()
120 if (shift) { in color_imageblit()
[all …]
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| D | sysimgblt.c | 57 u32 color = 0, val, shift; in color_imageblit() local
67 shift = 0; in color_imageblit()
74 shift = start_index; in color_imageblit()
83 val |= FB_SHIFT_HIGH(p, color, shift); in color_imageblit()
84 if (shift >= null_bits) { in color_imageblit()
87 val = (shift == null_bits) ? 0 : in color_imageblit()
88 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
90 shift += bpp; in color_imageblit()
91 shift &= (32 - 1); in color_imageblit()
94 if (shift) { in color_imageblit()
[all …]
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| /drivers/md/persistent-data/ |
| D | dm-btree-remove.c | 60 static void node_shift(struct btree_node *n, int shift) in node_shift() argument
65 if (shift < 0) { in node_shift()
66 shift = -shift; in node_shift()
67 BUG_ON(shift > nr_entries); in node_shift()
68 BUG_ON((void *) key_ptr(n, shift) >= value_ptr(n, shift)); in node_shift()
70 key_ptr(n, shift), in node_shift()
71 (nr_entries - shift) * sizeof(__le64)); in node_shift()
73 value_ptr(n, shift), in node_shift()
74 (nr_entries - shift) * value_size); in node_shift()
76 BUG_ON(nr_entries + shift > le32_to_cpu(n->header.max_entries)); in node_shift()
[all …]
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| /drivers/clk/at91/ |
| D | clk-peripheral.c | 142 int shift = 0; in clk_sam9x5_peripheral_autodiv() local
153 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { in clk_sam9x5_peripheral_autodiv()
154 if (parent_rate >> shift <= periph->range.max) in clk_sam9x5_peripheral_autodiv()
160 periph->div = shift; in clk_sam9x5_peripheral_autodiv()
257 u32 shift, long *best_diff, in clk_sam9x5_peripheral_best_diff() argument
260 unsigned long tmp_rate = parent_rate >> shift; in clk_sam9x5_peripheral_best_diff()
280 u32 shift; in clk_sam9x5_peripheral_determine_rate() local
286 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { in clk_sam9x5_peripheral_determine_rate()
287 tmp_rate = parent_rate >> shift; in clk_sam9x5_peripheral_determine_rate()
293 shift, &best_diff, &best_rate); in clk_sam9x5_peripheral_determine_rate()
[all …]
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| /drivers/infiniband/core/ |
| D | packer.c | 71 int shift; in ib_pack() local
76 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
80 structure) << shift; in ib_pack()
84 mask = cpu_to_be32(((1ull << desc[i].size_bits) - 1) << shift); in ib_pack()
88 int shift; in ib_pack() local
93 shift = 64 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
97 structure) << shift; in ib_pack()
101 mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); in ib_pack()
160 int shift; in ib_unpack() local
165 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_unpack()
[all …]
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| /drivers/net/ethernet/mellanox/mlxbf_gige/ |
| D | mlxbf_gige_mdio.c | 35 .shift = MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT,
39 .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
43 .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
47 .shift = MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT,
51 .shift = MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT,
55 .shift = MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT,
59 .shift = MLXBF2_GIGE_MDIO_GW_ST1_SHIFT,
67 .shift = MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT,
71 .shift = MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT,
75 .shift = MLXBF3_GIGE_MDIO_GW_DATA_SHIFT,
[all …]
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| /drivers/clk/ |
| D | clk-axm5516.c | 78 u32 shift; member
94 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); in axxia_divclk_recalc_rate()
113 u32 shift; member
128 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); in axxia_clkmux_get_parent()
216 .shift = 0,
230 .shift = 4,
244 .shift = 8,
258 .shift = 12,
272 .shift = 0,
286 .shift = 4,
[all …]
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| /drivers/regulator/ |
| D | max8998.c | 44 int *reg, int *shift) in max8998_get_enable_register() argument
51 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
55 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
59 *shift = 7 - (ldo - MAX8998_LDO14); in max8998_get_enable_register()
63 *shift = 7 - (ldo - MAX8998_BUCK1); in max8998_get_enable_register()
67 *shift = 7 - (ldo - MAX8998_EN32KHZ_AP); in max8998_get_enable_register()
71 *shift = 7 - (ldo - MAX8998_ESAFEOUT1); in max8998_get_enable_register()
75 *shift = 0; in max8998_get_enable_register()
88 int ret, reg, shift = 8; in max8998_ldo_is_enabled() local
91 ret = max8998_get_enable_register(rdev, ®, &shift); in max8998_ldo_is_enabled()
[all …]
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| /drivers/soc/aspeed/ |
| D | aspeed-uart-routing.c | 43 uint8_t shift; member
69 .shift = 8,
89 .shift = 28,
109 .shift = 25,
127 .shift = 22,
145 .shift = 19,
163 .shift = 16,
181 .shift = 12,
199 .shift = 9,
217 .shift = 6,
[all …]
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| /drivers/media/platform/nvidia/tegra-vde/ |
| D | iommu.c | 25 unsigned long shift; in tegra_vde_iommu_map() local
31 shift = iova_shift(&vde->iova); in tegra_vde_iommu_map()
33 iova = alloc_iova(&vde->iova, size >> shift, end >> shift, true); in tegra_vde_iommu_map()
53 unsigned long shift = iova_shift(&vde->iova); in tegra_vde_iommu_unmap() local
54 unsigned long size = iova_size(iova) << shift; in tegra_vde_iommu_unmap()
66 unsigned long shift; in tegra_vde_iommu_init() local
102 shift = iova_shift(&vde->iova); in tegra_vde_iommu_init()
103 iova = reserve_iova(&vde->iova, 0x60000000 >> shift, in tegra_vde_iommu_init()
104 0x70000000 >> shift); in tegra_vde_iommu_init()
118 iova = reserve_iova(&vde->iova, 0xffffffff >> shift, in tegra_vde_iommu_init()
[all …]
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