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/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
Ddcn20_dccg.h116 #define DCCG_REG_FIELD_LIST(type) \ argument
117 type DPPCLK0_DTO_PHASE;\
118 type DPPCLK0_DTO_MODULO;\
119 type DPPCLK_DTO_ENABLE[6];\
120 type DPPCLK_DTO_DB_EN[6];\
121 type REFCLK_CLOCK_EN;\
122 type REFCLK_SRC_SEL;\
123 type DISPCLK_STEP_DELAY;\
124 type DISPCLK_STEP_SIZE;\
125 type DISPCLK_FREQ_RAMP_DONE;\
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
Ddcn10_link_encoder.h228 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \ argument
229 type DIG_ENABLE;\
230 type DIG_HPD_SELECT;\
231 type DIG_MODE;\
232 type DIG_FE_SOURCE_SELECT;\
233 type DIG_CLOCK_PATTERN;\
234 type DPHY_BYPASS;\
235 type DPHY_ATEST_SEL_LANE0;\
236 type DPHY_ATEST_SEL_LANE1;\
237 type DPHY_ATEST_SEL_LANE2;\
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Ddcn10_stream_encoder.h355 #define SE_REG_FIELD_LIST_DCN1_0(type) \ argument
356 type AFMT_GENERIC_INDEX;\
357 type AFMT_GENERIC_HB0;\
358 type AFMT_GENERIC_HB1;\
359 type AFMT_GENERIC_HB2;\
360 type AFMT_GENERIC_HB3;\
361 type AFMT_GENERIC_LOCK_STATUS;\
362 type AFMT_GENERIC_CONFLICT;\
363 type AFMT_GENERIC_CONFLICT_CLR;\
364 type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
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/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
Ddcn10_dpp.h479 #define TF_REG_FIELD_LIST(type) \ argument
480 type EXT_OVERSCAN_LEFT; \
481 type EXT_OVERSCAN_RIGHT; \
482 type EXT_OVERSCAN_BOTTOM; \
483 type EXT_OVERSCAN_TOP; \
484 type OTG_H_BLANK_START; \
485 type OTG_H_BLANK_END; \
486 type OTG_V_BLANK_START; \
487 type OTG_V_BLANK_END; \
488 type PIXEL_DEPTH; \
[all …]
/drivers/net/ethernet/microchip/vcap/
Dvcap_model_kunit.c19 .type = VCAP_FIELD_U32,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U32,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_U32,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
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/drivers/net/ethernet/microchip/sparx5/
Dsparx5_vcap_ag_api.c19 .type = VCAP_FIELD_BIT,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U72,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_BIT,
59 .type = VCAP_FIELD_U32,
64 .type = VCAP_FIELD_U32,
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/drivers/net/ethernet/microchip/lan966x/
Dlan966x_vcap_ag_api.c11 .type = VCAP_FIELD_BIT,
16 .type = VCAP_FIELD_U32,
21 .type = VCAP_FIELD_U32,
26 .type = VCAP_FIELD_BIT,
31 .type = VCAP_FIELD_BIT,
36 .type = VCAP_FIELD_BIT,
41 .type = VCAP_FIELD_BIT,
46 .type = VCAP_FIELD_BIT,
51 .type = VCAP_FIELD_BIT,
56 .type = VCAP_FIELD_BIT,
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/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/
Ddcn10_hubbub.h203 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ argument
204 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\
205 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\
206 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\
207 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\
208 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\
209 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\
210 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\
211 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\
212 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\
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/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.h350 #define TG_REG_FIELD_LIST_DCN1_0(type) \ argument
351 type VSTARTUP_START;\
352 type VUPDATE_OFFSET;\
353 type VUPDATE_WIDTH;\
354 type VREADY_OFFSET;\
355 type OTG_BLANK_DATA_EN;\
356 type OTG_BLANK_DE_MODE;\
357 type OTG_CURRENT_BLANK_STATE;\
358 type OTG_MASTER_UPDATE_LOCK;\
359 type UPDATE_LOCK_STATUS;\
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/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
Ddcn30_dwb.h409 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \ argument
410 type DWB_ENABLE;\
411 type DISPCLK_R_DWB_GATE_DIS;\
412 type DISPCLK_G_DWB_GATE_DIS;\
413 type DWB_TEST_CLK_SEL;\
414 type DWBSCL_LUT_MEM_PWR_FORCE;\
415 type DWBSCL_LUT_MEM_PWR_DIS;\
416 type DWBSCL_LUT_MEM_PWR_STATE;\
417 type DWBSCL_LB_MEM_PWR_FORCE;\
418 type DWBSCL_LB_MEM_PWR_DIS;\
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/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
Ddcn20_dsc.h269 #define DSC_FIELD_LIST_DCN20(type)\ argument
270 type DSC_CLOCK_EN; \
271 type DSC_DISPCLK_R_GATE_DIS; \
272 type DSC_DSCCLK_R_GATE_DIS; \
273 type DSC_DBG_EN; \
274 type DSC_TEST_CLOCK_MUX_SEL; \
275 type ICH_RESET_AT_END_OF_LINE; \
276 type NUMBER_OF_SLICES_PER_LINE; \
277 type ALTERNATE_ICH_ENCODING_EN; \
278 type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
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/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/
Ddcn20_mmhubbub.h252 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \ argument
253 type MCIF_WB_BUFMGR_ENABLE;\
254 type MCIF_WB_BUFMGR_SW_INT_EN;\
255 type MCIF_WB_BUFMGR_SW_INT_ACK;\
256 type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
257 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
258 type MCIF_WB_BUFMGR_SW_LOCK;\
259 type MCIF_WB_P_VMID;\
260 type MCIF_WB_BUF_ADDR_FENCE_EN;\
261 type MCIF_WB_BUFMGR_CUR_LINE_R;\
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/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
Ddcn20_hubp.h181 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ argument
182 DCN_HUBP_REG_FIELD_BASE_LIST(type); \
183 type DMDATA_ADDRESS_HIGH;\
184 type DMDATA_MODE;\
185 type DMDATA_UPDATED;\
186 type DMDATA_REPEAT;\
187 type DMDATA_SIZE;\
188 type DMDATA_SW_UPDATED;\
189 type DMDATA_SW_REPEAT;\
190 type DMDATA_SW_SIZE;\
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dwb.h202 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \ argument
203 type WB_ENABLE;\
204 type DISPCLK_R_WB_GATE_DIS;\
205 type DISPCLK_G_WB_GATE_DIS;\
206 type DISPCLK_G_WBSCL_GATE_DIS;\
207 type WB_TEST_CLK_SEL;\
208 type WB_LB_LS_DIS;\
209 type WB_LB_SD_DIS;\
210 type WB_LUT_LS_DIS;\
211 type WBSCL_LB_MEM_PWR_MODE_SEL;\
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/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
Ddcn10_hubp.h457 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ argument
458 type HUBP_BLANK_EN;\
459 type HUBP_DISABLE;\
460 type HUBP_TTU_DISABLE;\
461 type HUBP_NO_OUTSTANDING_REQ;\
462 type HUBP_VTG_SEL;\
463 type HUBP_UNDERFLOW_STATUS;\
464 type HUBP_UNDERFLOW_CLEAR;\
465 type HUBP_IN_BLANK;\
466 type NUM_PIPES;\
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/drivers/media/pci/saa7134/
Dsaa7134-cards.c65 .type = SAA7134_INPUT_COMPOSITE,
80 .type = SAA7134_INPUT_COMPOSITE1,
84 .type = SAA7134_INPUT_TV,
88 .type = SAA7134_INPUT_TV_MONO,
93 .type = SAA7134_INPUT_RADIO,
108 .type = SAA7134_INPUT_TV,
113 .type = SAA7134_INPUT_TV_MONO,
118 .type = SAA7134_INPUT_COMPOSITE1,
123 .type = SAA7134_INPUT_COMPOSITE2,
128 .type = SAA7134_INPUT_SVIDEO,
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/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
Ddcn401_dpp.h382 #define DPP_REG_FIELD_LIST_DCN401(type) \ argument
383 DPP_REG_FIELD_LIST_DCN3(type); \
384 type CUR0_FP_BIAS_G_Y; \
385 type CUR0_FP_SCALE_G_Y; \
386 type CUR0_FP_BIAS_RB_CRCB; \
387 type CUR0_FP_SCALE_RB_CRCB; \
388 type CUR0_MATRIX_MODE; \
389 type CUR0_MATRIX_MODE_CURRENT; \
390 type CUR0_MATRIX_COEF_FORMAT; \
391 type CUR0_MATRIX_C11_A; \
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h148 #define DWBC_REG_FIELD_LIST(type) \ argument
149 type WB_ENABLE;\
150 type DISPCLK_R_WB_GATE_DIS;\
151 type DISPCLK_G_WB_GATE_DIS;\
152 type DISPCLK_G_WBSCL_GATE_DIS;\
153 type WB_LB_LS_DIS;\
154 type WB_LB_SD_DIS;\
155 type WB_LUT_LS_DIS;\
156 type CNV_WINDOW_CROP_EN;\
157 type CNV_STEREO_TYPE;\
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/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
Ddcn30_mpc.h645 #define MPC_REG_FIELD_LIST_DCN3_0(type) \ argument
646 MPC_REG_FIELD_LIST_DCN2_0(type) \
647 type MPC_DWB0_MUX;\
648 type MPC_DWB0_MUX_STATUS;\
649 type MPC_OUT_RATE_CONTROL;\
650 type MPC_OUT_RATE_CONTROL_DISABLE;\
651 type MPC_OUT_FLOW_CONTROL_MODE;\
652 type MPC_OUT_FLOW_CONTROL_COUNT; \
653 type MPCC_GAMUT_REMAP_MODE; \
654 type MPCC_GAMUT_REMAP_MODE_CURRENT;\
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/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_vpg.h93 #define VPG_DCN31_REG_FIELD_LIST(type) \ argument
94 type VPG_GENERIC_CONFLICT_OCCURED;\
95 type VPG_GENERIC_CONFLICT_CLR;\
96 type VPG_GENERIC_DATA_INDEX;\
97 type VPG_GENERIC_DATA_BYTE0;\
98 type VPG_GENERIC_DATA_BYTE1;\
99 type VPG_GENERIC_DATA_BYTE2;\
100 type VPG_GENERIC_DATA_BYTE3;\
101 type VPG_GENERIC0_FRAME_UPDATE;\
102 type VPG_GENERIC1_FRAME_UPDATE;\
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/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_vpg.h88 #define VPG_DCN3_REG_FIELD_LIST(type) \ argument
89 type VPG_GENERIC_CONFLICT_OCCURED;\
90 type VPG_GENERIC_CONFLICT_CLR;\
91 type VPG_GENERIC_DATA_INDEX;\
92 type VPG_GENERIC_DATA_BYTE0;\
93 type VPG_GENERIC_DATA_BYTE1;\
94 type VPG_GENERIC_DATA_BYTE2;\
95 type VPG_GENERIC_DATA_BYTE3;\
96 type VPG_GENERIC0_FRAME_UPDATE;\
97 type VPG_GENERIC1_FRAME_UPDATE;\
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/drivers/net/wireless/intel/iwlwifi/mvm/
Drs.h150 enum iwl_table_type type; member
160 #define is_type_legacy(type) (((type) == LQ_LEGACY_G) || \ argument
161 ((type) == LQ_LEGACY_A))
162 #define is_type_ht_siso(type) ((type) == LQ_HT_SISO) argument
163 #define is_type_ht_mimo2(type) ((type) == LQ_HT_MIMO2) argument
164 #define is_type_vht_siso(type) ((type) == LQ_VHT_SISO) argument
165 #define is_type_vht_mimo2(type) ((type) == LQ_VHT_MIMO2) argument
166 #define is_type_he_siso(type) ((type) == LQ_HE_SISO) argument
167 #define is_type_he_mimo2(type) ((type) == LQ_HE_MIMO2) argument
168 #define is_type_siso(type) (is_type_ht_siso(type) || is_type_vht_siso(type) || \ argument
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/drivers/media/pci/cx88/
Dcx88-cards.c59 .type = CX88_VMUX_COMPOSITE1,
62 .type = CX88_VMUX_COMPOSITE2,
65 .type = CX88_VMUX_COMPOSITE3,
68 .type = CX88_VMUX_COMPOSITE4,
80 .type = CX88_VMUX_TELEVISION,
84 .type = CX88_VMUX_DEBUG,
88 .type = CX88_VMUX_COMPOSITE1,
92 .type = CX88_VMUX_SVIDEO,
97 .type = CX88_RADIO,
108 .type = CX88_VMUX_TELEVISION,
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/drivers/md/
Ddm-exception-store.c25 struct dm_exception_store_type *type; in __find_exception_store_type() local
27 list_for_each_entry(type, &_exception_store_types, list) in __find_exception_store_type()
28 if (!strcmp(name, type->name)) in __find_exception_store_type()
29 return type; in __find_exception_store_type()
36 struct dm_exception_store_type *type; in _get_exception_store_type() local
40 type = __find_exception_store_type(name); in _get_exception_store_type()
42 if (type && !try_module_get(type->module)) in _get_exception_store_type()
43 type = NULL; in _get_exception_store_type()
47 return type; in _get_exception_store_type()
76 struct dm_exception_store_type *type; in get_type() local
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/drivers/hwmon/
Dibmpowernv.c77 enum sensors type; member
114 if (sdata->type == TEMP) in show_sensor()
117 else if (sdata->type == POWER_INPUT) in show_sensor()
248 static const char *convert_opal_attr_name(enum sensors type, in convert_opal_attr_name() argument
258 if (type == TEMP) in convert_opal_attr_name()
260 else if (type == FAN) in convert_opal_attr_name()
274 enum sensors type, u32 *index) in parse_opal_node_name() argument
284 attr_name = convert_opal_attr_name(type, attr_suffix); in parse_opal_node_name()
293 enum sensors type; in get_sensor_type() local
296 for (type = 0; type < ARRAY_SIZE(legacy_compatibles); type++) { in get_sensor_type()
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