Searched refs:uint32_t (Results 1 – 25 of 2113) sorted by relevance
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| /drivers/gpu/drm/amd/include/ |
| D | v11_structs.h | 28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2)
31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
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| D | v12_structs.h | 28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
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| D | v10_structs.h | 28 uint32_t reserved_0; // offset: 0 (0x0)
29 uint32_t reserved_1; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t reserved_4; // offset: 4 (0x4)
33 uint32_t reserved_5; // offset: 5 (0x5)
34 uint32_t reserved_6; // offset: 6 (0x6)
35 uint32_t reserved_7; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
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| D | v9_structs.h | 28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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| D | vi_structs.h | 28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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| D | cik_structs.h | 28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
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| D | discovery.h | 59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
76 uint32_t signature; /* Table Signature */
79 uint32_t id; /* Table ID */
107 uint32_t base_address[]; /* variable number of Addresses */
125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/
143 …DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_ba…
170 uint32_t table_id; /* table ID */
173 uint32_t size; /* size of the entire header+data in bytes */
179 uint32_t gc_num_se;
180 uint32_t gc_num_wgp0_per_sa;
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| D | mes_v12_api_def.h | 75 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
76 uint32_t opcode : 8;
77 uint32_t dwsize : 8; /* including header */
78 uint32_t reserved : 12;
81 uint32_t u32All;
220 uint32_t first_free_entry_index;
221 uint32_t wraparound_count;
228 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
229 uint32_t reserved_operation_type_bits;
252 uint32_t vmid_mask_mmhub;
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| D | mes_v11_api_def.h | 73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
74 uint32_t opcode : 8;
75 uint32_t dwsize : 8; /* including header */
76 uint32_t reserved : 12;
79 uint32_t u32All;
174 uint32_t first_free_entry_index;
175 uint32_t wraparound_count;
182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
183 uint32_t reserved_operation_type_bits;
206 uint32_t vmid_mask_mmhub;
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| D | kgd_kfd_interface.h | 51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
64 uint32_t vram_width;
65 uint32_t mem_clk_max;
111 uint32_t num_pipe_per_mec;
114 uint32_t num_queue_per_pipe;
123 uint32_t *sdma_doorbell_idx;
128 uint32_t non_cp_doorbells_start;
129 uint32_t non_cp_doorbells_end;
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| /drivers/scsi/arcmsr/ |
| D | arcmsr.h | 104 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
105 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
113 uint32_t HeaderLength;
115 uint32_t Timeout;
116 uint32_t ControlCode;
117 uint32_t ReturnCode;
118 uint32_t Length;
196 uint32_t data_len;
206 uint32_t signature; /*0, 00-03*/
207 uint32_t request_len; /*1, 04-07*/
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| /drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_pm4_headers_ai.h | 32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < number of DWORDs - 1 in the
37 uint32_t type : 2; /* < packet identifier.
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
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| D | kfd_pm4_headers_vi.h | 32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < Number of DWORDS - 1 in the
37 uint32_t type : 2; /* < packet identifier
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
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| D | kfd_pm4_headers.h | 33 uint32_t reserved1:8;
35 uint32_t opcode:8;
37 uint32_t count:14;
39 uint32_t type:2;
41 uint32_t u32all;
54 uint32_t ordinal1;
59 uint32_t pasid:16;
60 uint32_t reserved1:8;
61 uint32_t diq_enable:1;
62 uint32_t process_quantum:7;
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| /drivers/gpu/drm/amd/display/dc/spl/ |
| D | dc_spl_types.h | 16 uint32_t width;
17 uint32_t height;
40 uint32_t v_taps;
41 uint32_t h_taps;
42 uint32_t v_taps_c;
43 uint32_t h_taps_c;
173 uint32_t width;
174 uint32_t height;
188 uint32_t offset_rgb_y;
189 uint32_t offset_rgb_cbcr;
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| D | dml_top_dchub_registers.h | 12 uint32_t refcyc_h_blank_end;
13 uint32_t dlg_vblank_end;
14 uint32_t min_dst_y_next_start;
15 uint32_t refcyc_per_htotal;
16 uint32_t refcyc_x_after_scaler;
17 uint32_t dst_y_after_scaler;
18 uint32_t dst_y_prefetch;
19 uint32_t dst_y_per_vm_vblank;
20 uint32_t dst_y_per_row_vblank;
21 uint32_t dst_y_per_vm_flip;
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| /drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 67 uint32_t enum_id:16; /* 1 based enum */
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
82 uint32_t clk_mask_shift;
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| D | bios_parser_types.h | 119 uint32_t pixel_clock; /* khz */
132 uint32_t pixel_clock; /* in KHz */
161 uint32_t pixel_clock;
162 uint32_t lane_select;
163 uint32_t lane_settings;
172 uint32_t h_total;
173 uint32_t h_addressable;
174 uint32_t h_overscan_left;
175 uint32_t h_overscan_right;
176 uint32_t h_sync_start;
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| /drivers/scsi/lpfc/ |
| D | lpfc_hw.h | 80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
92 uint32_t word;
155 uint32_t PortId; /* For RNN_ID requests */
164 uint32_t port_id;
167 uint32_t PortId;
172 uint32_t PortId;
178 uint32_t PortId;
181 uint32_t fc4_types[8];
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ucode.h | 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
51 uint32_t ucode_start_addr;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
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| D | amdgpu_amdkfd_gfx_v9.h | 23 void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
24 uint32_t sh_mem_config,
25 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
26 uint32_t sh_mem_bases, uint32_t inst);
28 unsigned int vmid, uint32_t inst);
29 int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
30 uint32_t inst);
31 int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
32 uint32_t queue_id, uint32_t __user *wptr,
33 uint32_t wptr_shift, uint32_t wptr_mask,
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| /drivers/gpu/drm/meson/ |
| D | meson_drv.h | 70 uint32_t osd1_ctrl_stat;
71 uint32_t osd1_ctrl_stat2;
72 uint32_t osd1_blk0_cfg[5];
73 uint32_t osd1_blk1_cfg4;
74 uint32_t osd1_blk2_cfg4;
75 uint32_t osd1_addr;
76 uint32_t osd1_stride;
77 uint32_t osd1_height;
78 uint32_t osd1_width;
79 uint32_t osd_sc_ctrl0;
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| /drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_6_pmfw.h | 129 uint32_t AccumulationCounter;
132 uint32_t MaxSocketTemperature;
133 uint32_t MaxVrTemperature;
134 uint32_t MaxHbmTemperature;
140 uint32_t SocketPowerLimit;
141 uint32_t MaxSocketPowerLimit;
142 uint32_t SocketPower;
153 uint32_t CclkFrequencyLimit;
154 uint32_t GfxclkFrequencyLimit;
155 uint32_t FclkFrequency;
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu8_hwmgr.h | 45 uint32_t soft_min_clk;
46 uint32_t hard_min_clk;
47 uint32_t soft_max_clk;
48 uint32_t hard_max_clk;
52 uint32_t bootup_uma_clock;
53 uint32_t bootup_engine_clock;
54 uint32_t dentist_vco_freq;
55 uint32_t nb_dpm_enable;
56 uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
57 uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
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| D | smu7_hwmgr.h | 47 uint32_t offset;
48 uint32_t mask;
49 uint32_t shift;
50 uint32_t value;
55 uint32_t memory_clock;
56 uint32_t engine_clock;
68 uint32_t vclk;
69 uint32_t dclk;
73 uint32_t evclk;
74 uint32_t ecclk;
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