1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <linux/ptp_clock_kernel.h>
59 #include <net/devlink.h>
60
61 #define MLX5_ADEV_NAME "mlx5_core"
62
63 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
64
65 enum {
66 MLX5_BOARD_ID_LEN = 64,
67 };
68
69 enum {
70 MLX5_CMD_WQ_MAX_NAME = 32,
71 };
72
73 enum {
74 CMD_OWNER_SW = 0x0,
75 CMD_OWNER_HW = 0x1,
76 CMD_STATUS_SUCCESS = 0,
77 };
78
79 enum mlx5_sqp_t {
80 MLX5_SQP_SMI = 0,
81 MLX5_SQP_GSI = 1,
82 MLX5_SQP_IEEE_1588 = 2,
83 MLX5_SQP_SNIFFER = 3,
84 MLX5_SQP_SYNC_UMR = 4,
85 };
86
87 enum {
88 MLX5_MAX_PORTS = 8,
89 };
90
91 enum {
92 MLX5_ATOMIC_MODE_OFFSET = 16,
93 MLX5_ATOMIC_MODE_IB_COMP = 1,
94 MLX5_ATOMIC_MODE_CX = 2,
95 MLX5_ATOMIC_MODE_8B = 3,
96 MLX5_ATOMIC_MODE_16B = 4,
97 MLX5_ATOMIC_MODE_32B = 5,
98 MLX5_ATOMIC_MODE_64B = 6,
99 MLX5_ATOMIC_MODE_128B = 7,
100 MLX5_ATOMIC_MODE_256B = 8,
101 };
102
103 enum {
104 MLX5_REG_SBPR = 0xb001,
105 MLX5_REG_SBCM = 0xb002,
106 MLX5_REG_QPTS = 0x4002,
107 MLX5_REG_QETCR = 0x4005,
108 MLX5_REG_QTCT = 0x400a,
109 MLX5_REG_QPDPM = 0x4013,
110 MLX5_REG_QCAM = 0x4019,
111 MLX5_REG_DCBX_PARAM = 0x4020,
112 MLX5_REG_DCBX_APP = 0x4021,
113 MLX5_REG_FPGA_CAP = 0x4022,
114 MLX5_REG_FPGA_CTRL = 0x4023,
115 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 MLX5_REG_CORE_DUMP = 0x402e,
117 MLX5_REG_PCAP = 0x5001,
118 MLX5_REG_PMTU = 0x5003,
119 MLX5_REG_PTYS = 0x5004,
120 MLX5_REG_PAOS = 0x5006,
121 MLX5_REG_PFCC = 0x5007,
122 MLX5_REG_PPCNT = 0x5008,
123 MLX5_REG_PPTB = 0x500b,
124 MLX5_REG_PBMC = 0x500c,
125 MLX5_REG_PMAOS = 0x5012,
126 MLX5_REG_PUDE = 0x5009,
127 MLX5_REG_PMPE = 0x5010,
128 MLX5_REG_PELC = 0x500e,
129 MLX5_REG_PVLC = 0x500f,
130 MLX5_REG_PCMR = 0x5041,
131 MLX5_REG_PDDR = 0x5031,
132 MLX5_REG_PMLP = 0x5002,
133 MLX5_REG_PPLM = 0x5023,
134 MLX5_REG_PCAM = 0x507f,
135 MLX5_REG_NODE_DESC = 0x6001,
136 MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 MLX5_REG_MTCAP = 0x9009,
138 MLX5_REG_MTMP = 0x900A,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MFRL = 0x9028,
141 MLX5_REG_MLCR = 0x902b,
142 MLX5_REG_MRTC = 0x902d,
143 MLX5_REG_MTRC_CAP = 0x9040,
144 MLX5_REG_MTRC_CONF = 0x9041,
145 MLX5_REG_MTRC_STDB = 0x9042,
146 MLX5_REG_MTRC_CTRL = 0x9043,
147 MLX5_REG_MPEIN = 0x9050,
148 MLX5_REG_MPCNT = 0x9051,
149 MLX5_REG_MTPPS = 0x9053,
150 MLX5_REG_MTPPSE = 0x9054,
151 MLX5_REG_MTUTC = 0x9055,
152 MLX5_REG_MPEGC = 0x9056,
153 MLX5_REG_MPIR = 0x9059,
154 MLX5_REG_MCQS = 0x9060,
155 MLX5_REG_MCQI = 0x9061,
156 MLX5_REG_MCC = 0x9062,
157 MLX5_REG_MCDA = 0x9063,
158 MLX5_REG_MCAM = 0x907f,
159 MLX5_REG_MSECQ = 0x9155,
160 MLX5_REG_MSEES = 0x9156,
161 MLX5_REG_MIRC = 0x9162,
162 MLX5_REG_MTPTM = 0x9180,
163 MLX5_REG_MTCTR = 0x9181,
164 MLX5_REG_SBCAM = 0xB01F,
165 MLX5_REG_RESOURCE_DUMP = 0xC000,
166 MLX5_REG_DTOR = 0xC00E,
167 };
168
169 enum mlx5_qpts_trust_state {
170 MLX5_QPTS_TRUST_PCP = 1,
171 MLX5_QPTS_TRUST_DSCP = 2,
172 };
173
174 enum mlx5_dcbx_oper_mode {
175 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
176 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
177 };
178
179 enum {
180 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
181 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
182 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
183 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
184 };
185
186 enum mlx5_page_fault_resume_flags {
187 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
188 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
189 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
190 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
191 };
192
193 enum dbg_rsc_type {
194 MLX5_DBG_RSC_QP,
195 MLX5_DBG_RSC_EQ,
196 MLX5_DBG_RSC_CQ,
197 };
198
199 enum port_state_policy {
200 MLX5_POLICY_DOWN = 0,
201 MLX5_POLICY_UP = 1,
202 MLX5_POLICY_FOLLOW = 2,
203 MLX5_POLICY_INVALID = 0xffffffff
204 };
205
206 enum mlx5_coredev_type {
207 MLX5_COREDEV_PF,
208 MLX5_COREDEV_VF,
209 MLX5_COREDEV_SF,
210 };
211
212 struct mlx5_field_desc {
213 int i;
214 };
215
216 struct mlx5_rsc_debug {
217 struct mlx5_core_dev *dev;
218 void *object;
219 enum dbg_rsc_type type;
220 struct dentry *root;
221 struct mlx5_field_desc fields[];
222 };
223
224 enum mlx5_dev_event {
225 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
226 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
227 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
228 };
229
230 enum mlx5_port_status {
231 MLX5_PORT_UP = 1,
232 MLX5_PORT_DOWN = 2,
233 };
234
235 enum mlx5_cmdif_state {
236 MLX5_CMDIF_STATE_UNINITIALIZED,
237 MLX5_CMDIF_STATE_UP,
238 MLX5_CMDIF_STATE_DOWN,
239 };
240
241 struct mlx5_cmd_first {
242 __be32 data[4];
243 };
244
245 struct mlx5_cmd_msg {
246 struct list_head list;
247 struct cmd_msg_cache *parent;
248 u32 len;
249 struct mlx5_cmd_first first;
250 struct mlx5_cmd_mailbox *next;
251 };
252
253 struct mlx5_cmd_debug {
254 struct dentry *dbg_root;
255 void *in_msg;
256 void *out_msg;
257 u8 status;
258 u16 inlen;
259 u16 outlen;
260 };
261
262 struct cmd_msg_cache {
263 /* protect block chain allocations
264 */
265 spinlock_t lock;
266 struct list_head head;
267 unsigned int max_inbox_size;
268 unsigned int num_ent;
269 };
270
271 enum {
272 MLX5_NUM_COMMAND_CACHES = 5,
273 };
274
275 struct mlx5_cmd_stats {
276 u64 sum;
277 u64 n;
278 /* number of times command failed */
279 u64 failed;
280 /* number of times command failed on bad status returned by FW */
281 u64 failed_mbox_status;
282 /* last command failed returned errno */
283 u32 last_failed_errno;
284 /* last bad status returned by FW */
285 u8 last_failed_mbox_status;
286 /* last command failed syndrome returned by FW */
287 u32 last_failed_syndrome;
288 struct dentry *root;
289 /* protect command average calculations */
290 spinlock_t lock;
291 };
292
293 struct mlx5_cmd {
294 struct mlx5_nb nb;
295
296 /* members which needs to be queried or reinitialized each reload */
297 struct {
298 u16 cmdif_rev;
299 u8 log_sz;
300 u8 log_stride;
301 int max_reg_cmds;
302 unsigned long bitmask;
303 struct semaphore sem;
304 struct semaphore pages_sem;
305 struct semaphore throttle_sem;
306 } vars;
307 enum mlx5_cmdif_state state;
308 void *cmd_alloc_buf;
309 dma_addr_t alloc_dma;
310 int alloc_size;
311 void *cmd_buf;
312 dma_addr_t dma;
313
314 /* protect command queue allocations
315 */
316 spinlock_t alloc_lock;
317
318 /* protect token allocations
319 */
320 spinlock_t token_lock;
321 u8 token;
322 char wq_name[MLX5_CMD_WQ_MAX_NAME];
323 struct workqueue_struct *wq;
324 int mode;
325 u16 allowed_opcode;
326 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
327 struct dma_pool *pool;
328 struct mlx5_cmd_debug dbg;
329 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
330 int checksum_disabled;
331 struct xarray stats;
332 };
333
334 struct mlx5_cmd_mailbox {
335 void *buf;
336 dma_addr_t dma;
337 struct mlx5_cmd_mailbox *next;
338 };
339
340 struct mlx5_buf_list {
341 void *buf;
342 dma_addr_t map;
343 };
344
345 struct mlx5_frag_buf {
346 struct mlx5_buf_list *frags;
347 int npages;
348 int size;
349 u8 page_shift;
350 };
351
352 struct mlx5_frag_buf_ctrl {
353 struct mlx5_buf_list *frags;
354 u32 sz_m1;
355 u16 frag_sz_m1;
356 u16 strides_offset;
357 u8 log_sz;
358 u8 log_stride;
359 u8 log_frag_strides;
360 };
361
362 struct mlx5_core_psv {
363 u32 psv_idx;
364 struct psv_layout {
365 u32 pd;
366 u16 syndrome;
367 u16 reserved;
368 u16 bg;
369 u16 app_tag;
370 u32 ref_tag;
371 } psv;
372 };
373
374 struct mlx5_core_sig_ctx {
375 struct mlx5_core_psv psv_memory;
376 struct mlx5_core_psv psv_wire;
377 struct ib_sig_err err_item;
378 bool sig_status_checked;
379 bool sig_err_exists;
380 u32 sigerr_count;
381 };
382
383 #define MLX5_24BIT_MASK ((1 << 24) - 1)
384
385 enum mlx5_res_type {
386 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
387 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
388 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
389 MLX5_RES_SRQ = 3,
390 MLX5_RES_XSRQ = 4,
391 MLX5_RES_XRQ = 5,
392 };
393
394 struct mlx5_core_rsc_common {
395 enum mlx5_res_type res;
396 refcount_t refcount;
397 struct completion free;
398 bool invalid;
399 };
400
401 struct mlx5_uars_page {
402 void __iomem *map;
403 bool wc;
404 u32 index;
405 struct list_head list;
406 unsigned int bfregs;
407 unsigned long *reg_bitmap; /* for non fast path bf regs */
408 unsigned long *fp_bitmap;
409 unsigned int reg_avail;
410 unsigned int fp_avail;
411 struct kref ref_count;
412 struct mlx5_core_dev *mdev;
413 };
414
415 struct mlx5_bfreg_head {
416 /* protect blue flame registers allocations */
417 struct mutex lock;
418 struct list_head list;
419 };
420
421 struct mlx5_bfreg_data {
422 struct mlx5_bfreg_head reg_head;
423 struct mlx5_bfreg_head wc_head;
424 };
425
426 struct mlx5_sq_bfreg {
427 void __iomem *map;
428 struct mlx5_uars_page *up;
429 bool wc;
430 u32 index;
431 unsigned int offset;
432 };
433
434 struct mlx5_core_health {
435 struct health_buffer __iomem *health;
436 __be32 __iomem *health_counter;
437 struct timer_list timer;
438 u32 prev;
439 int miss_counter;
440 u8 synd;
441 u32 fatal_error;
442 u32 crdump_size;
443 struct workqueue_struct *wq;
444 unsigned long flags;
445 struct work_struct fatal_report_work;
446 struct work_struct report_work;
447 struct devlink_health_reporter *fw_reporter;
448 struct devlink_health_reporter *fw_fatal_reporter;
449 struct devlink_health_reporter *vnic_reporter;
450 struct delayed_work update_fw_log_ts_work;
451 };
452
453 enum {
454 MLX5_PF_NOTIFY_DISABLE_VF,
455 MLX5_PF_NOTIFY_ENABLE_VF,
456 };
457
458 struct mlx5_vf_context {
459 int enabled;
460 u64 port_guid;
461 u64 node_guid;
462 /* Valid bits are used to validate administrative guid only.
463 * Enabled after ndo_set_vf_guid
464 */
465 u8 port_guid_valid:1;
466 u8 node_guid_valid:1;
467 enum port_state_policy policy;
468 struct blocking_notifier_head notifier;
469 };
470
471 struct mlx5_core_sriov {
472 struct mlx5_vf_context *vfs_ctx;
473 int num_vfs;
474 u16 max_vfs;
475 u16 max_ec_vfs;
476 };
477
478 struct mlx5_fc_pool {
479 struct mlx5_core_dev *dev;
480 struct mutex pool_lock; /* protects pool lists */
481 struct list_head fully_used;
482 struct list_head partially_used;
483 struct list_head unused;
484 int available_fcs;
485 int used_fcs;
486 int threshold;
487 };
488
489 struct mlx5_fc_stats {
490 spinlock_t counters_idr_lock; /* protects counters_idr */
491 struct idr counters_idr;
492 struct list_head counters;
493 struct llist_head addlist;
494 struct llist_head dellist;
495
496 struct workqueue_struct *wq;
497 struct delayed_work work;
498 unsigned long next_query;
499 unsigned long sampling_interval; /* jiffies */
500 u32 *bulk_query_out;
501 int bulk_query_len;
502 size_t num_counters;
503 bool bulk_query_alloc_failed;
504 unsigned long next_bulk_query_alloc;
505 struct mlx5_fc_pool fc_pool;
506 };
507
508 struct mlx5_events;
509 struct mlx5_mpfs;
510 struct mlx5_eswitch;
511 struct mlx5_lag;
512 struct mlx5_devcom_dev;
513 struct mlx5_fw_reset;
514 struct mlx5_eq_table;
515 struct mlx5_irq_table;
516 struct mlx5_vhca_state_notifier;
517 struct mlx5_sf_dev_table;
518 struct mlx5_sf_hw_table;
519 struct mlx5_sf_table;
520 struct mlx5_crypto_dek_priv;
521
522 struct mlx5_rate_limit {
523 u32 rate;
524 u32 max_burst_sz;
525 u16 typical_pkt_sz;
526 };
527
528 struct mlx5_rl_entry {
529 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
530 u64 refcount;
531 u16 index;
532 u16 uid;
533 u8 dedicated : 1;
534 };
535
536 struct mlx5_rl_table {
537 /* protect rate limit table */
538 struct mutex rl_lock;
539 u16 max_size;
540 u32 max_rate;
541 u32 min_rate;
542 struct mlx5_rl_entry *rl_entry;
543 u64 refcount;
544 };
545
546 struct mlx5_core_roce {
547 struct mlx5_flow_table *ft;
548 struct mlx5_flow_group *fg;
549 struct mlx5_flow_handle *allow_rule;
550 };
551
552 enum {
553 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
554 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
555 /* Set during device detach to block any further devices
556 * creation/deletion on drivers rescan. Unset during device attach.
557 */
558 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
559 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
560 };
561
562 struct mlx5_adev {
563 struct auxiliary_device adev;
564 struct mlx5_core_dev *mdev;
565 int idx;
566 };
567
568 struct mlx5_debugfs_entries {
569 struct dentry *dbg_root;
570 struct dentry *qp_debugfs;
571 struct dentry *eq_debugfs;
572 struct dentry *cq_debugfs;
573 struct dentry *cmdif_debugfs;
574 struct dentry *pages_debugfs;
575 struct dentry *lag_debugfs;
576 };
577
578 enum mlx5_func_type {
579 MLX5_PF,
580 MLX5_VF,
581 MLX5_SF,
582 MLX5_HOST_PF,
583 MLX5_EC_VF,
584 MLX5_FUNC_TYPE_NUM,
585 };
586
587 struct mlx5_ft_pool;
588 struct mlx5_priv {
589 /* IRQ table valid only for real pci devices PF or VF */
590 struct mlx5_irq_table *irq_table;
591 struct mlx5_eq_table *eq_table;
592
593 /* pages stuff */
594 struct mlx5_nb pg_nb;
595 struct workqueue_struct *pg_wq;
596 struct xarray page_root_xa;
597 atomic_t reg_pages;
598 struct list_head free_list;
599 u32 fw_pages;
600 u32 page_counters[MLX5_FUNC_TYPE_NUM];
601 u32 fw_pages_alloc_failed;
602 u32 give_pages_dropped;
603 u32 reclaim_pages_discard;
604
605 struct mlx5_core_health health;
606 struct list_head traps;
607
608 struct mlx5_debugfs_entries dbg;
609
610 /* start: alloc staff */
611 /* protect buffer allocation according to numa node */
612 struct mutex alloc_mutex;
613 int numa_node;
614
615 struct mutex pgdir_mutex;
616 struct list_head pgdir_list;
617 /* end: alloc staff */
618
619 struct mlx5_adev **adev;
620 int adev_idx;
621 int sw_vhca_id;
622 struct mlx5_events *events;
623 struct mlx5_vhca_events *vhca_events;
624
625 struct mlx5_flow_steering *steering;
626 struct mlx5_mpfs *mpfs;
627 struct mlx5_eswitch *eswitch;
628 struct mlx5_core_sriov sriov;
629 struct mlx5_lag *lag;
630 u32 flags;
631 struct mlx5_devcom_dev *devc;
632 struct mlx5_devcom_comp_dev *hca_devcom_comp;
633 struct mlx5_fw_reset *fw_reset;
634 struct mlx5_core_roce roce;
635 struct mlx5_fc_stats fc_stats;
636 struct mlx5_rl_table rl_table;
637 struct mlx5_ft_pool *ft_pool;
638
639 struct mlx5_bfreg_data bfregs;
640 struct mlx5_uars_page *uar;
641 #ifdef CONFIG_MLX5_SF
642 struct mlx5_vhca_state_notifier *vhca_state_notifier;
643 struct mlx5_sf_dev_table *sf_dev_table;
644 struct mlx5_core_dev *parent_mdev;
645 #endif
646 #ifdef CONFIG_MLX5_SF_MANAGER
647 struct mlx5_sf_hw_table *sf_hw_table;
648 struct mlx5_sf_table *sf_table;
649 #endif
650 struct blocking_notifier_head lag_nh;
651 };
652
653 enum mlx5_device_state {
654 MLX5_DEVICE_STATE_UP = 1,
655 MLX5_DEVICE_STATE_INTERNAL_ERROR,
656 };
657
658 enum mlx5_interface_state {
659 MLX5_INTERFACE_STATE_UP = BIT(0),
660 MLX5_BREAK_FW_WAIT = BIT(1),
661 };
662
663 enum mlx5_pci_status {
664 MLX5_PCI_STATUS_DISABLED,
665 MLX5_PCI_STATUS_ENABLED,
666 };
667
668 enum mlx5_pagefault_type_flags {
669 MLX5_PFAULT_REQUESTOR = 1 << 0,
670 MLX5_PFAULT_WRITE = 1 << 1,
671 MLX5_PFAULT_RDMA = 1 << 2,
672 };
673
674 struct mlx5_td {
675 /* protects tirs list changes while tirs refresh */
676 struct mutex list_lock;
677 struct list_head tirs_list;
678 u32 tdn;
679 };
680
681 struct mlx5e_resources {
682 struct mlx5e_hw_objs {
683 u32 pdn;
684 struct mlx5_td td;
685 u32 mkey;
686 struct mlx5_sq_bfreg bfreg;
687 #define MLX5_MAX_NUM_TC 8
688 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
689 bool tisn_valid;
690 } hw_objs;
691 struct net_device *uplink_netdev;
692 netdevice_tracker tracker;
693 struct mutex uplink_netdev_lock;
694 struct mlx5_crypto_dek_priv *dek_priv;
695 };
696
697 enum mlx5_sw_icm_type {
698 MLX5_SW_ICM_TYPE_STEERING,
699 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
700 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
701 MLX5_SW_ICM_TYPE_SW_ENCAP,
702 };
703
704 #define MLX5_MAX_RESERVED_GIDS 8
705
706 struct mlx5_rsvd_gids {
707 unsigned int start;
708 unsigned int count;
709 struct ida ida;
710 };
711
712 #define MAX_PIN_NUM 8
713 struct mlx5_pps {
714 u8 pin_caps[MAX_PIN_NUM];
715 struct work_struct out_work;
716 u64 start[MAX_PIN_NUM];
717 u8 enabled;
718 u64 min_npps_period;
719 u64 min_out_pulse_duration_ns;
720 };
721
722 struct mlx5_timer {
723 struct cyclecounter cycles;
724 struct timecounter tc;
725 u32 nominal_c_mult;
726 unsigned long overflow_period;
727 };
728
729 struct mlx5_clock {
730 struct mlx5_nb pps_nb;
731 seqlock_t lock;
732 struct hwtstamp_config hwtstamp_config;
733 struct ptp_clock *ptp;
734 struct ptp_clock_info ptp_info;
735 struct mlx5_pps pps_info;
736 struct mlx5_timer timer;
737 };
738
739 struct mlx5_dm;
740 struct mlx5_fw_tracer;
741 struct mlx5_vxlan;
742 struct mlx5_geneve;
743 struct mlx5_hv_vhca;
744
745 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
746 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
747
748 enum {
749 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
750 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
751 };
752
753 enum {
754 MKEY_CACHE_LAST_STD_ENTRY = 20,
755 MLX5_IMR_KSM_CACHE_ENTRY,
756 MAX_MKEY_CACHE_ENTRIES
757 };
758
759 struct mlx5_profile {
760 u64 mask;
761 u8 log_max_qp;
762 u8 num_cmd_caches;
763 struct {
764 int size;
765 int limit;
766 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
767 };
768
769 struct mlx5_hca_cap {
770 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
771 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
772 };
773
774 enum mlx5_wc_state {
775 MLX5_WC_STATE_UNINITIALIZED,
776 MLX5_WC_STATE_UNSUPPORTED,
777 MLX5_WC_STATE_SUPPORTED,
778 };
779
780 struct mlx5_core_dev {
781 struct device *device;
782 enum mlx5_coredev_type coredev_type;
783 struct pci_dev *pdev;
784 /* sync pci state */
785 struct mutex pci_status_mutex;
786 enum mlx5_pci_status pci_status;
787 u8 rev_id;
788 char board_id[MLX5_BOARD_ID_LEN];
789 struct mlx5_cmd cmd;
790 struct {
791 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
792 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
793 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
794 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
795 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
796 u8 embedded_cpu;
797 } caps;
798 struct mlx5_timeouts *timeouts;
799 u64 sys_image_guid;
800 phys_addr_t iseg_base;
801 struct mlx5_init_seg __iomem *iseg;
802 phys_addr_t bar_addr;
803 enum mlx5_device_state state;
804 /* sync interface state */
805 struct mutex intf_state_mutex;
806 struct lock_class_key lock_key;
807 unsigned long intf_state;
808 struct mlx5_priv priv;
809 struct mlx5_profile profile;
810 u32 issi;
811 struct mlx5e_resources mlx5e_res;
812 struct mlx5_dm *dm;
813 struct mlx5_vxlan *vxlan;
814 struct mlx5_geneve *geneve;
815 struct {
816 struct mlx5_rsvd_gids reserved_gids;
817 u32 roce_en;
818 } roce;
819 #ifdef CONFIG_MLX5_FPGA
820 struct mlx5_fpga_device *fpga;
821 #endif
822 struct mlx5_clock clock;
823 struct mlx5_ib_clock_info *clock_info;
824 struct mlx5_fw_tracer *tracer;
825 struct mlx5_rsc_dump *rsc_dump;
826 u32 vsc_addr;
827 struct mlx5_hv_vhca *hv_vhca;
828 struct mlx5_hwmon *hwmon;
829 u64 num_block_tc;
830 u64 num_block_ipsec;
831 #ifdef CONFIG_MLX5_MACSEC
832 struct mlx5_macsec_fs *macsec_fs;
833 /* MACsec notifier chain to sync MACsec core and IB database */
834 struct blocking_notifier_head macsec_nh;
835 #endif
836 u64 num_ipsec_offloads;
837 struct mlx5_sd *sd;
838 enum mlx5_wc_state wc_state;
839 /* sync write combining state */
840 struct mutex wc_state_lock;
841 };
842
843 struct mlx5_db {
844 __be32 *db;
845 union {
846 struct mlx5_db_pgdir *pgdir;
847 struct mlx5_ib_user_db_page *user_page;
848 } u;
849 dma_addr_t dma;
850 int index;
851 };
852
853 enum {
854 MLX5_COMP_EQ_SIZE = 1024,
855 };
856
857 enum {
858 MLX5_PTYS_IB = 1 << 0,
859 MLX5_PTYS_EN = 1 << 2,
860 };
861
862 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
863
864 enum {
865 MLX5_CMD_ENT_STATE_PENDING_COMP,
866 };
867
868 struct mlx5_cmd_work_ent {
869 unsigned long state;
870 struct mlx5_cmd_msg *in;
871 struct mlx5_cmd_msg *out;
872 void *uout;
873 int uout_size;
874 mlx5_cmd_cbk_t callback;
875 struct delayed_work cb_timeout_work;
876 void *context;
877 int idx;
878 struct completion handling;
879 struct completion slotted;
880 struct completion done;
881 struct mlx5_cmd *cmd;
882 struct work_struct work;
883 struct mlx5_cmd_layout *lay;
884 int ret;
885 int page_queue;
886 u8 status;
887 u8 token;
888 u64 ts1;
889 u64 ts2;
890 u16 op;
891 bool polling;
892 /* Track the max comp handlers */
893 refcount_t refcnt;
894 };
895
896 enum phy_port_state {
897 MLX5_AAA_111
898 };
899
900 struct mlx5_hca_vport_context {
901 u32 field_select;
902 bool sm_virt_aware;
903 bool has_smi;
904 bool has_raw;
905 enum port_state_policy policy;
906 enum phy_port_state phys_state;
907 enum ib_port_state vport_state;
908 u8 port_physical_state;
909 u64 sys_image_guid;
910 u64 port_guid;
911 u64 node_guid;
912 u32 cap_mask1;
913 u32 cap_mask1_perm;
914 u16 cap_mask2;
915 u16 cap_mask2_perm;
916 u16 lid;
917 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
918 u8 lmc;
919 u8 subnet_timeout;
920 u16 sm_lid;
921 u8 sm_sl;
922 u16 qkey_violation_counter;
923 u16 pkey_violation_counter;
924 bool grh_required;
925 u8 num_plane;
926 };
927
928 #define STRUCT_FIELD(header, field) \
929 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
930 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
931
932 extern struct dentry *mlx5_debugfs_root;
933
fw_rev_maj(struct mlx5_core_dev * dev)934 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
935 {
936 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
937 }
938
fw_rev_min(struct mlx5_core_dev * dev)939 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
940 {
941 return ioread32be(&dev->iseg->fw_rev) >> 16;
942 }
943
fw_rev_sub(struct mlx5_core_dev * dev)944 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
945 {
946 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
947 }
948
mlx5_base_mkey(const u32 key)949 static inline u32 mlx5_base_mkey(const u32 key)
950 {
951 return key & 0xffffff00u;
952 }
953
wq_get_byte_sz(u8 log_sz,u8 log_stride)954 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
955 {
956 return ((u32)1 << log_sz) << log_stride;
957 }
958
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)959 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
960 u8 log_stride, u8 log_sz,
961 u16 strides_offset,
962 struct mlx5_frag_buf_ctrl *fbc)
963 {
964 fbc->frags = frags;
965 fbc->log_stride = log_stride;
966 fbc->log_sz = log_sz;
967 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
968 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
969 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
970 fbc->strides_offset = strides_offset;
971 }
972
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)973 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
974 u8 log_stride, u8 log_sz,
975 struct mlx5_frag_buf_ctrl *fbc)
976 {
977 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
978 }
979
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)980 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
981 u32 ix)
982 {
983 unsigned int frag;
984
985 ix += fbc->strides_offset;
986 frag = ix >> fbc->log_frag_strides;
987
988 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
989 }
990
991 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)992 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
993 {
994 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
995
996 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
997 }
998
999 enum {
1000 CMD_ALLOWED_OPCODE_ALL,
1001 };
1002
1003 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1004 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1005 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
1006
1007 struct mlx5_async_ctx {
1008 struct mlx5_core_dev *dev;
1009 atomic_t num_inflight;
1010 struct completion inflight_done;
1011 };
1012
1013 struct mlx5_async_work;
1014
1015 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
1016
1017 struct mlx5_async_work {
1018 struct mlx5_async_ctx *ctx;
1019 mlx5_async_cbk_t user_callback;
1020 u16 opcode; /* cmd opcode */
1021 u16 op_mod; /* cmd op_mod */
1022 void *out; /* pointer to the cmd output buffer */
1023 };
1024
1025 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1026 struct mlx5_async_ctx *ctx);
1027 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1028 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1029 void *out, int out_size, mlx5_async_cbk_t callback,
1030 struct mlx5_async_work *work);
1031 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1032 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1033 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1034 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1035 int out_size);
1036
1037 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1038 ({ \
1039 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1040 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1041 })
1042
1043 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1044 ({ \
1045 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1046 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1047 })
1048
1049 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1050 void *out, int out_size);
1051 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1052
1053 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1054 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1055
1056 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1057
1058 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1059 int mlx5_health_init(struct mlx5_core_dev *dev);
1060 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1061 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1062 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1063 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1064 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1065 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1066 struct mlx5_frag_buf *buf, int node);
1067 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1068 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1069 int inlen);
1070 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1071 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1072 int outlen);
1073 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1074 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1075 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1076 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1077 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1078 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1079 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1080 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1081 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1082 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1083 void mlx5_register_debugfs(void);
1084 void mlx5_unregister_debugfs(void);
1085
1086 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1087 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1088 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1089 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1090 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1091
1092 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1093 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1094 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1095 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1096 void *data_out, int size_out, u16 reg_id, int arg,
1097 int write, bool verbose);
1098 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1099 int size_in, void *data_out, int size_out,
1100 u16 reg_num, int arg, int write);
1101
1102 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1103 int node);
1104
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1105 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1106 {
1107 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1108 }
1109
1110 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1111
1112 const char *mlx5_command_str(int command);
1113 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1114 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1115 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1116 int npsvs, u32 *sig_index);
1117 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1118 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1119 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1120
1121 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1122 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1123 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1124 struct mlx5_rate_limit *rl);
1125 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1126 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1127 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1128 bool dedicated_entry, u16 *index);
1129 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1130 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1131 struct mlx5_rate_limit *rl_1);
1132 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1133 bool map_wc, bool fast_path);
1134 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1135
1136 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1137 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1138 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1139 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1140 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1141 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1142
mlx5_mkey_to_idx(u32 mkey)1143 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1144 {
1145 return mkey >> 8;
1146 }
1147
mlx5_idx_to_mkey(u32 mkey_idx)1148 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1149 {
1150 return mkey_idx << 8;
1151 }
1152
mlx5_mkey_variant(u32 mkey)1153 static inline u8 mlx5_mkey_variant(u32 mkey)
1154 {
1155 return mkey & 0xff;
1156 }
1157
1158 /* Async-atomic event notifier used by mlx5 core to forward FW
1159 * evetns received from event queue to mlx5 consumers.
1160 * Optimise event queue dipatching.
1161 */
1162 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1163 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1164
1165 /* Async-atomic event notifier used for forwarding
1166 * evetns from the event queue into the to mlx5 events dispatcher,
1167 * eswitch, clock and others.
1168 */
1169 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1170 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1171
1172 /* Blocking event notifier used to forward SW events, used for slow path */
1173 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1174 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1175 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1176 void *data);
1177
1178 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1179
1180 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1181 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1182 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1183 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1184 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1185 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1186 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1187 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1188 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1189 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1190 struct net_device *slave);
1191 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1192 u64 *values,
1193 int num_counters,
1194 size_t *offsets);
1195 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1196
1197 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1198 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1199 peer; \
1200 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1201
1202 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1203 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1204 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1205 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1206 u64 length, u32 log_alignment, u16 uid,
1207 phys_addr_t *addr, u32 *obj_id);
1208 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1209 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1210
1211 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1212 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1213
1214 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1215 int vf_id,
1216 struct notifier_block *nb);
1217 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1218 int vf_id,
1219 struct notifier_block *nb);
1220 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1221 struct ib_device *device,
1222 struct rdma_netdev_alloc_params *params);
1223
1224 enum {
1225 MLX5_PCI_DEV_IS_VF = 1 << 0,
1226 };
1227
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1228 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1229 {
1230 return dev->coredev_type == MLX5_COREDEV_PF;
1231 }
1232
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1233 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1234 {
1235 return dev->coredev_type == MLX5_COREDEV_VF;
1236 }
1237
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1238 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1239 const struct mlx5_core_dev *dev2)
1240 {
1241 return dev1->coredev_type == dev2->coredev_type;
1242 }
1243
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1244 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1245 {
1246 return dev->caps.embedded_cpu;
1247 }
1248
1249 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1250 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1251 {
1252 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1253 }
1254
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1255 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1256 {
1257 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1258 }
1259
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1260 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1261 {
1262 return dev->priv.sriov.max_vfs;
1263 }
1264
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1265 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1266 {
1267 /* LACP owner conditions:
1268 * 1) Function is physical.
1269 * 2) LAG is supported by FW.
1270 * 3) LAG is managed by driver (currently the only option).
1271 */
1272 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1273 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1274 MLX5_CAP_GEN(dev, lag_master);
1275 }
1276
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1277 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1278 {
1279 return dev->priv.sriov.max_ec_vfs;
1280 }
1281
mlx5_get_gid_table_len(u16 param)1282 static inline int mlx5_get_gid_table_len(u16 param)
1283 {
1284 if (param > 4) {
1285 pr_warn("gid table length is zero\n");
1286 return 0;
1287 }
1288
1289 return 8 * (1 << param);
1290 }
1291
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1292 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1293 {
1294 return !!(dev->priv.rl_table.max_size);
1295 }
1296
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1297 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1298 {
1299 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1300 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1301 }
1302
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1303 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1304 {
1305 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1306 }
1307
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1308 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1309 {
1310 return mlx5_core_is_mp_slave(dev) ||
1311 mlx5_core_is_mp_master(dev);
1312 }
1313
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1314 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1315 {
1316 if (!mlx5_core_mp_enabled(dev))
1317 return 1;
1318
1319 return MLX5_CAP_GEN(dev, native_port_num);
1320 }
1321
mlx5_get_dev_index(struct mlx5_core_dev * dev)1322 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1323 {
1324 int idx = MLX5_CAP_GEN(dev, native_port_num);
1325
1326 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1327 return idx - 1;
1328 else
1329 return PCI_FUNC(dev->pdev->devfn);
1330 }
1331
1332 enum {
1333 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1334 };
1335
1336 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1337
mlx5_get_roce_state(struct mlx5_core_dev * dev)1338 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1339 {
1340 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1341 return MLX5_CAP_GEN(dev, roce);
1342
1343 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1344 * in order to support RoCE enable/disable feature
1345 */
1346 return mlx5_is_roce_on(dev);
1347 }
1348
1349 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1350 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1351 {
1352 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1353 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1354 return false;
1355
1356 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1357 return false;
1358
1359 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1360 return false;
1361
1362 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1363 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1364 return false;
1365
1366 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1367 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1368 return false;
1369
1370 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1371 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1372 return false;
1373
1374 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1375 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1376 return false;
1377
1378 return true;
1379 }
1380
1381 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1382
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1383 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1384 {
1385 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1386 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1387 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1388 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1389 return false;
1390
1391 return true;
1392 }
1393 #endif
1394
1395 enum {
1396 MLX5_OCTWORD = 16,
1397 };
1398
1399 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1400 #endif /* MLX5_DRIVER_H */
1401