1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/fault-inject.h>
20 #include <linux/debugfs.h>
21 #include <linux/msi.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-direction.h>
24 #include <scsi/scsi_device.h>
25 #include <scsi/scsi_host.h>
26 #include <ufs/unipro.h>
27 #include <ufs/ufs.h>
28 #include <ufs/ufs_quirks.h>
29 #include <ufs/ufshci.h>
30 #include <linux/android_vendor.h>
31 #include <linux/android_kabi.h>
32
33 #define UFSHCD "ufshcd"
34
35 struct scsi_device;
36 struct ufs_hba;
37
38 enum dev_cmd_type {
39 DEV_CMD_TYPE_NOP = 0x0,
40 DEV_CMD_TYPE_QUERY = 0x1,
41 DEV_CMD_TYPE_RPMB = 0x2,
42 };
43
44 enum ufs_event_type {
45 /* uic specific errors */
46 UFS_EVT_PA_ERR = 0,
47 UFS_EVT_DL_ERR,
48 UFS_EVT_NL_ERR,
49 UFS_EVT_TL_ERR,
50 UFS_EVT_DME_ERR,
51
52 /* fatal errors */
53 UFS_EVT_AUTO_HIBERN8_ERR,
54 UFS_EVT_FATAL_ERR,
55 UFS_EVT_LINK_STARTUP_FAIL,
56 UFS_EVT_RESUME_ERR,
57 UFS_EVT_SUSPEND_ERR,
58 UFS_EVT_WL_SUSP_ERR,
59 UFS_EVT_WL_RES_ERR,
60
61 /* abnormal events */
62 UFS_EVT_DEV_RESET,
63 UFS_EVT_HOST_RESET,
64 UFS_EVT_ABORT,
65
66 UFS_EVT_CNT,
67 };
68
69 /**
70 * struct uic_command - UIC command structure
71 * @command: UIC command
72 * @argument1: UIC command argument 1
73 * @argument2: UIC command argument 2
74 * @argument3: UIC command argument 3
75 * @cmd_active: Indicate if UIC command is outstanding
76 * @done: UIC command completion
77 */
78 struct uic_command {
79 const u32 command;
80 const u32 argument1;
81 u32 argument2;
82 u32 argument3;
83 int cmd_active;
84 struct completion done;
85 };
86
87 /* Used to differentiate the power management options */
88 enum ufs_pm_op {
89 UFS_RUNTIME_PM,
90 UFS_SYSTEM_PM,
91 UFS_SHUTDOWN_PM,
92 };
93
94 /* Host <-> Device UniPro Link state */
95 enum uic_link_state {
96 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
97 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
98 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
99 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
100 };
101
102 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
103 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
104 UIC_LINK_ACTIVE_STATE)
105 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
106 UIC_LINK_HIBERN8_STATE)
107 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
108 UIC_LINK_BROKEN_STATE)
109 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
110 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
111 UIC_LINK_ACTIVE_STATE)
112 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
113 UIC_LINK_HIBERN8_STATE)
114 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
115 UIC_LINK_BROKEN_STATE)
116
117 #define ufshcd_set_ufs_dev_active(h) \
118 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
119 #define ufshcd_set_ufs_dev_sleep(h) \
120 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
121 #define ufshcd_set_ufs_dev_poweroff(h) \
122 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
123 #define ufshcd_set_ufs_dev_deepsleep(h) \
124 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
125 #define ufshcd_is_ufs_dev_active(h) \
126 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
127 #define ufshcd_is_ufs_dev_sleep(h) \
128 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
129 #define ufshcd_is_ufs_dev_poweroff(h) \
130 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
131 #define ufshcd_is_ufs_dev_deepsleep(h) \
132 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
133
134 /*
135 * UFS Power management levels.
136 * Each level is in increasing order of power savings, except DeepSleep
137 * which is lower than PowerDown with power on but not PowerDown with
138 * power off.
139 */
140 enum ufs_pm_level {
141 UFS_PM_LVL_0,
142 UFS_PM_LVL_1,
143 UFS_PM_LVL_2,
144 UFS_PM_LVL_3,
145 UFS_PM_LVL_4,
146 UFS_PM_LVL_5,
147 UFS_PM_LVL_6,
148 UFS_PM_LVL_MAX
149 };
150
151 struct ufs_pm_lvl_states {
152 enum ufs_dev_pwr_mode dev_state;
153 enum uic_link_state link_state;
154 };
155
156 /**
157 * struct ufshcd_lrb - local reference block
158 * @utr_descriptor_ptr: UTRD address of the command
159 * @ucd_req_ptr: UCD address of the command
160 * @ucd_rsp_ptr: Response UPIU address for this command
161 * @ucd_prdt_ptr: PRDT address of the command
162 * @utrd_dma_addr: UTRD dma address for debug
163 * @ucd_prdt_dma_addr: PRDT dma address for debug
164 * @ucd_rsp_dma_addr: UPIU response dma address for debug
165 * @ucd_req_dma_addr: UPIU request dma address for debug
166 * @cmd: pointer to SCSI command
167 * @scsi_status: SCSI status of the command
168 * @command_type: SCSI, UFS, Query.
169 * @task_tag: Task tag of the command
170 * @lun: LUN of the command
171 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
172 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
173 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
174 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
175 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
176 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
177 * @data_unit_num: the data unit number for the first block for inline crypto
178 * @req_abort_skip: skip request abort task flag
179 */
180 struct ufshcd_lrb {
181 struct utp_transfer_req_desc *utr_descriptor_ptr;
182 struct utp_upiu_req *ucd_req_ptr;
183 struct utp_upiu_rsp *ucd_rsp_ptr;
184 struct ufshcd_sg_entry *ucd_prdt_ptr;
185
186 dma_addr_t utrd_dma_addr;
187 dma_addr_t ucd_req_dma_addr;
188 dma_addr_t ucd_rsp_dma_addr;
189 dma_addr_t ucd_prdt_dma_addr;
190
191 struct scsi_cmnd *cmd;
192 int scsi_status;
193
194 int command_type;
195 int task_tag;
196 u8 lun; /* UPIU LUN id field is only 8-bit wide */
197 bool intr_cmd;
198 ktime_t issue_time_stamp;
199 u64 issue_time_stamp_local_clock;
200 ktime_t compl_time_stamp;
201 u64 compl_time_stamp_local_clock;
202 #ifdef CONFIG_SCSI_UFS_CRYPTO
203 int crypto_key_slot;
204 u64 data_unit_num;
205 #endif
206
207 bool req_abort_skip;
208
209 ANDROID_KABI_RESERVE(1);
210 };
211
212 /**
213 * struct ufs_query_req - parameters for building a query request
214 * @query_func: UPIU header query function
215 * @upiu_req: the query request data
216 */
217 struct ufs_query_req {
218 u8 query_func;
219 struct utp_upiu_query upiu_req;
220 };
221
222 /**
223 * struct ufs_query_resp - UPIU QUERY
224 * @response: device response code
225 * @upiu_res: query response data
226 */
227 struct ufs_query_res {
228 struct utp_upiu_query upiu_res;
229 };
230
231 /**
232 * struct ufs_query - holds relevant data structures for query request
233 * @request: request upiu and function
234 * @descriptor: buffer for sending/receiving descriptor
235 * @response: response upiu and response
236 */
237 struct ufs_query {
238 struct ufs_query_req request;
239 u8 *descriptor;
240 struct ufs_query_res response;
241 };
242
243 /**
244 * struct ufs_dev_cmd - all assosiated fields with device management commands
245 * @type: device management command type - Query, NOP OUT
246 * @lock: lock to allow one command at a time
247 * @complete: internal commands completion
248 * @query: Device management query information
249 */
250 struct ufs_dev_cmd {
251 enum dev_cmd_type type;
252 struct mutex lock;
253 struct completion *complete;
254 struct ufs_query query;
255 };
256
257 /**
258 * struct ufs_clk_info - UFS clock related info
259 * @list: list headed by hba->clk_list_head
260 * @clk: clock node
261 * @name: clock name
262 * @max_freq: maximum frequency supported by the clock
263 * @min_freq: min frequency that can be used for clock scaling
264 * @curr_freq: indicates the current frequency that it is set to
265 * @keep_link_active: indicates that the clk should not be disabled if
266 * link is active
267 * @enabled: variable to check against multiple enable/disable
268 */
269 struct ufs_clk_info {
270 struct list_head list;
271 struct clk *clk;
272 const char *name;
273 u32 max_freq;
274 u32 min_freq;
275 u32 curr_freq;
276 bool keep_link_active;
277 bool enabled;
278 };
279
280 enum ufs_notify_change_status {
281 PRE_CHANGE,
282 POST_CHANGE,
283 };
284
285 struct ufs_pa_layer_attr {
286 u32 gear_rx;
287 u32 gear_tx;
288 u32 lane_rx;
289 u32 lane_tx;
290 u32 pwr_rx;
291 u32 pwr_tx;
292 u32 hs_rate;
293 };
294
295 struct ufs_pwr_mode_info {
296 bool is_valid;
297 struct ufs_pa_layer_attr info;
298 };
299
300 /**
301 * struct ufs_hba_variant_ops - variant specific callbacks
302 * @name: variant name
303 * @max_num_rtt: maximum RTT supported by the host
304 * @init: called when the driver is initialized
305 * @exit: called to cleanup everything done in init
306 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
307 * capability bit.
308 * @get_ufs_hci_version: called to get UFS HCI version
309 * @clk_scale_notify: notifies that clks are scaled up/down
310 * @setup_clocks: called before touching any of the controller registers
311 * @hce_enable_notify: called before and after HCE enable bit is set to allow
312 * variant specific Uni-Pro initialization.
313 * @link_startup_notify: called before and after Link startup is carried out
314 * to allow variant specific Uni-Pro initialization.
315 * @pwr_change_notify: called before and after a power mode change
316 * is carried out to allow vendor spesific capabilities
317 * to be set. PRE_CHANGE can modify final_params based
318 * on desired_pwr_mode, but POST_CHANGE must not alter
319 * the final_params parameter
320 * @setup_xfer_req: called before any transfer request is issued
321 * to set some things
322 * @setup_task_mgmt: called before any task management request is issued
323 * to set some things
324 * @hibern8_notify: called around hibern8 enter/exit
325 * @apply_dev_quirks: called to apply device specific quirks
326 * @fixup_dev_quirks: called to modify device specific quirks
327 * @suspend: called during host controller PM callback
328 * @resume: called during host controller PM callback
329 * @dbg_register_dump: used to dump controller debug information
330 * @phy_initialization: used to initialize phys
331 * @device_reset: called to issue a reset pulse on the UFS device
332 * @config_scaling_param: called to configure clock scaling parameters
333 * @program_key: program or evict an inline encryption key
334 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
335 * @event_notify: called to notify important events
336 * @mcq_config_resource: called to configure MCQ platform resources
337 * @get_hba_mac: reports maximum number of outstanding commands supported by
338 * the controller. Should be implemented for UFSHCI 4.0 or later
339 * controllers that are not compliant with the UFSHCI 4.0 specification.
340 * @op_runtime_config: called to config Operation and runtime regs Pointers
341 * @get_outstanding_cqs: called to get outstanding completion queues
342 * @config_esi: called to config Event Specific Interrupt
343 * @config_scsi_dev: called to configure SCSI device parameters
344 * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed
345 */
346 struct ufs_hba_variant_ops {
347 const char *name;
348 int max_num_rtt;
349 int (*init)(struct ufs_hba *);
350 void (*exit)(struct ufs_hba *);
351 u32 (*get_ufs_hci_version)(struct ufs_hba *);
352 int (*set_dma_mask)(struct ufs_hba *);
353 int (*clk_scale_notify)(struct ufs_hba *, bool, unsigned long,
354 enum ufs_notify_change_status);
355 int (*setup_clocks)(struct ufs_hba *, bool,
356 enum ufs_notify_change_status);
357 int (*hce_enable_notify)(struct ufs_hba *,
358 enum ufs_notify_change_status);
359 int (*link_startup_notify)(struct ufs_hba *,
360 enum ufs_notify_change_status);
361 int (*pwr_change_notify)(struct ufs_hba *,
362 enum ufs_notify_change_status status,
363 struct ufs_pa_layer_attr *desired_pwr_mode,
364 struct ufs_pa_layer_attr *final_params);
365 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
366 bool is_scsi_cmd);
367 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
368 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
369 enum ufs_notify_change_status);
370 int (*apply_dev_quirks)(struct ufs_hba *hba);
371 void (*fixup_dev_quirks)(struct ufs_hba *hba);
372 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
373 enum ufs_notify_change_status);
374 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
375 void (*dbg_register_dump)(struct ufs_hba *hba);
376 int (*phy_initialization)(struct ufs_hba *);
377 int (*device_reset)(struct ufs_hba *hba);
378 void (*config_scaling_param)(struct ufs_hba *hba,
379 struct devfreq_dev_profile *profile,
380 struct devfreq_simple_ondemand_data *data);
381 int (*program_key)(struct ufs_hba *hba,
382 const union ufs_crypto_cfg_entry *cfg, int slot);
383 int (*fill_crypto_prdt)(struct ufs_hba *hba,
384 const struct bio_crypt_ctx *crypt_ctx,
385 void *prdt, unsigned int num_segments);
386 void (*event_notify)(struct ufs_hba *hba,
387 enum ufs_event_type evt, void *data);
388 int (*mcq_config_resource)(struct ufs_hba *hba);
389 int (*get_hba_mac)(struct ufs_hba *hba);
390 int (*op_runtime_config)(struct ufs_hba *hba);
391 int (*get_outstanding_cqs)(struct ufs_hba *hba,
392 unsigned long *ocqs);
393 int (*config_esi)(struct ufs_hba *hba);
394 void (*config_scsi_dev)(struct scsi_device *sdev);
395 u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq);
396 };
397
398 /* clock gating state */
399 enum clk_gating_state {
400 CLKS_OFF,
401 CLKS_ON,
402 REQ_CLKS_OFF,
403 REQ_CLKS_ON,
404 };
405
406 /**
407 * struct ufs_clk_gating - UFS clock gating related info
408 * @gate_work: worker to turn off clocks after some delay as specified in
409 * delay_ms
410 * @ungate_work: worker to turn on clocks that will be used in case of
411 * interrupt context
412 * @clk_gating_workq: workqueue for clock gating work.
413 * @lock: serialize access to some struct ufs_clk_gating members. An outer lock
414 * relative to the host lock
415 * @state: the current clocks state
416 * @delay_ms: gating delay in ms
417 * @is_suspended: clk gating is suspended when set to 1 which can be used
418 * during suspend/resume
419 * @delay_attr: sysfs attribute to control delay_attr
420 * @enable_attr: sysfs attribute to enable/disable clock gating
421 * @is_enabled: Indicates the current status of clock gating
422 * @is_initialized: Indicates whether clock gating is initialized or not
423 * @active_reqs: number of requests that are pending and should be waited for
424 * completion before gating clocks.
425 */
426 struct ufs_clk_gating {
427 struct delayed_work gate_work;
428 struct work_struct ungate_work;
429 struct workqueue_struct *clk_gating_workq;
430
431 spinlock_t lock;
432
433 enum clk_gating_state state;
434 unsigned long delay_ms;
435 bool is_suspended;
436 struct device_attribute delay_attr;
437 struct device_attribute enable_attr;
438 bool is_enabled;
439 bool is_initialized;
440 int active_reqs;
441
442 ANDROID_KABI_RESERVE(1);
443 };
444
445 /**
446 * struct ufs_clk_scaling - UFS clock scaling related data
447 * @active_reqs: number of requests that are pending. If this is zero when
448 * devfreq ->target() function is called then schedule "suspend_work" to
449 * suspend devfreq.
450 * @tot_busy_t: Total busy time in current polling window
451 * @window_start_t: Start time (in jiffies) of the current polling window
452 * @busy_start_t: Start time of current busy period
453 * @enable_attr: sysfs attribute to enable/disable clock scaling
454 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
455 * one keeps track of previous power mode.
456 * @workq: workqueue to schedule devfreq suspend/resume work
457 * @suspend_work: worker to suspend devfreq
458 * @resume_work: worker to resume devfreq
459 * @target_freq: frequency requested by devfreq framework
460 * @min_gear: lowest HS gear to scale down to
461 * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else
462 * disable Write Booster
463 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
464 * clkscale_enable sysfs node
465 * @is_allowed: tracks if scaling is currently allowed or not, used to block
466 * clock scaling which is not invoked from devfreq governor
467 * @is_initialized: Indicates whether clock scaling is initialized or not
468 * @is_busy_started: tracks if busy period has started or not
469 * @is_suspended: tracks if devfreq is suspended or not
470 */
471 struct ufs_clk_scaling {
472 int active_reqs;
473 unsigned long tot_busy_t;
474 ktime_t window_start_t;
475 ktime_t busy_start_t;
476 struct device_attribute enable_attr;
477 struct ufs_pa_layer_attr saved_pwr_info;
478 struct workqueue_struct *workq;
479 struct work_struct suspend_work;
480 struct work_struct resume_work;
481 unsigned long target_freq;
482 u32 min_gear;
483 u32 wb_gear;
484 bool is_enabled;
485 bool is_allowed;
486 bool is_initialized;
487 bool is_busy_started;
488 bool is_suspended;
489 bool suspend_on_no_request;
490
491 ANDROID_KABI_RESERVE(1);
492 };
493
494 #define UFS_EVENT_HIST_LENGTH 8
495 /**
496 * struct ufs_event_hist - keeps history of errors
497 * @pos: index to indicate cyclic buffer position
498 * @val: cyclic buffer for registers value
499 * @tstamp: cyclic buffer for time stamp
500 * @cnt: error counter
501 */
502 struct ufs_event_hist {
503 int pos;
504 u32 val[UFS_EVENT_HIST_LENGTH];
505 u64 tstamp[UFS_EVENT_HIST_LENGTH];
506 unsigned long long cnt;
507 };
508
509 /**
510 * struct ufs_stats - keeps usage/err statistics
511 * @last_intr_status: record the last interrupt status.
512 * @last_intr_ts: record the last interrupt timestamp.
513 * @hibern8_exit_cnt: Counter to keep track of number of exits,
514 * reset this after link-startup.
515 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
516 * Clear after the first successful command completion.
517 * @event: array with event history.
518 */
519 struct ufs_stats {
520 u32 last_intr_status;
521 u64 last_intr_ts;
522
523 u32 hibern8_exit_cnt;
524 u64 last_hibern8_exit_tstamp;
525 struct ufs_event_hist event[UFS_EVT_CNT];
526 };
527
528 /**
529 * enum ufshcd_state - UFS host controller state
530 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
531 * processing.
532 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
533 * SCSI commands.
534 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
535 * SCSI commands may be submitted to the controller.
536 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
537 * newly submitted SCSI commands with error code DID_BAD_TARGET.
538 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
539 * failed. Fail all SCSI commands with error code DID_ERROR.
540 */
541 enum ufshcd_state {
542 UFSHCD_STATE_RESET,
543 UFSHCD_STATE_OPERATIONAL,
544 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
545 UFSHCD_STATE_EH_SCHEDULED_FATAL,
546 UFSHCD_STATE_ERROR,
547 };
548
549 enum ufshcd_quirks {
550 /* Interrupt aggregation support is broken */
551 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
552
553 /*
554 * delay before each dme command is required as the unipro
555 * layer has shown instabilities
556 */
557 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
558
559 /*
560 * If UFS host controller is having issue in processing LCC (Line
561 * Control Command) coming from device then enable this quirk.
562 * When this quirk is enabled, host controller driver should disable
563 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
564 * attribute of device to 0).
565 */
566 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
567
568 /*
569 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
570 * inbound Link supports unterminated line in HS mode. Setting this
571 * attribute to 1 fixes moving to HS gear.
572 */
573 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
574
575 /*
576 * This quirk needs to be enabled if the host controller only allows
577 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
578 * SLOW AUTO).
579 */
580 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
581
582 /*
583 * This quirk needs to be enabled if the host controller doesn't
584 * advertise the correct version in UFS_VER register. If this quirk
585 * is enabled, standard UFS host driver will call the vendor specific
586 * ops (get_ufs_hci_version) to get the correct version.
587 */
588 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
589
590 /*
591 * Clear handling for transfer/task request list is just opposite.
592 */
593 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
594
595 /*
596 * This quirk needs to be enabled if host controller doesn't allow
597 * that the interrupt aggregation timer and counter are reset by s/w.
598 */
599 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
600
601 /*
602 * This quirks needs to be enabled if host controller cannot be
603 * enabled via HCE register.
604 */
605 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
606
607 /*
608 * This quirk needs to be enabled if the host controller regards
609 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
610 */
611 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
612
613 /*
614 * This quirk needs to be enabled if the host controller reports
615 * OCS FATAL ERROR with device error through sense data
616 */
617 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
618
619 /*
620 * This quirk needs to be enabled if the host controller has
621 * auto-hibernate capability but it doesn't work.
622 */
623 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
624
625 /*
626 * This quirk needs to disable manual flush for write booster
627 */
628 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
629
630 /*
631 * This quirk needs to disable unipro timeout values
632 * before power mode change
633 */
634 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
635
636 /*
637 * This quirk needs to be enabled if the host controller does not
638 * support UIC command
639 */
640 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
641
642 /*
643 * This quirk needs to be enabled if the host controller cannot
644 * support physical host configuration.
645 */
646 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
647
648 /*
649 * This quirk needs to be enabled if the host controller has
650 * auto-hibernate capability but it's FASTAUTO only.
651 */
652 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
653
654 /*
655 * This quirk needs to be enabled if the host controller needs
656 * to reinit the device after switching to maximum gear.
657 */
658 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
659
660 /*
661 * Some host raises interrupt (per queue) in addition to
662 * CQES (traditional) when ESI is disabled.
663 * Enable this quirk will disable CQES and use per queue interrupt.
664 */
665 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
666
667 /*
668 * Some host does not implement SQ Run Time Command (SQRTC) register
669 * thus need this quirk to skip related flow.
670 */
671 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
672
673 /*
674 * This quirk needs to be enabled if the host controller supports inline
675 * encryption but it needs to initialize the crypto capabilities in a
676 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
677 * enabled, the standard code won't initialize the blk_crypto_profile;
678 * ufs_hba_variant_ops::init() must do it instead.
679 */
680 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
681
682 /*
683 * This quirk needs to be enabled if the host controller supports inline
684 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
685 * host controller initialization fails if that bit is set.
686 */
687 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
688
689 /*
690 * This quirk needs to be enabled if the host controller driver copies
691 * cryptographic keys into the PRDT in order to send them to hardware,
692 * and therefore the PRDT should be zeroized after each request (as per
693 * the standard best practice for managing keys).
694 */
695 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
696
697 /*
698 * This quirk indicates that the controller reports the value 1 (not
699 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
700 * Controller Capabilities register although it supports the legacy
701 * single doorbell mode.
702 */
703 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
704 };
705
706 enum ufshcd_android_quirks {
707 /* Set IID to one. */
708 UFSHCD_ANDROID_QUIRK_SET_IID_TO_ONE = 1 << 0,
709
710 /* Do not read IS after H8 enter */
711 UFSHCD_ANDROID_QUIRK_NO_IS_READ_ON_H8 = 1 << 1,
712 };
713
714 enum ufshcd_caps {
715 /* Allow dynamic clk gating */
716 UFSHCD_CAP_CLK_GATING = 1 << 0,
717
718 /* Allow hiberb8 with clk gating */
719 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
720
721 /* Allow dynamic clk scaling */
722 UFSHCD_CAP_CLK_SCALING = 1 << 2,
723
724 /* Allow auto bkops to enabled during runtime suspend */
725 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
726
727 /*
728 * This capability allows host controller driver to use the UFS HCI's
729 * interrupt aggregation capability.
730 * CAUTION: Enabling this might reduce overall UFS throughput.
731 */
732 UFSHCD_CAP_INTR_AGGR = 1 << 4,
733
734 /*
735 * This capability allows the device auto-bkops to be always enabled
736 * except during suspend (both runtime and suspend).
737 * Enabling this capability means that device will always be allowed
738 * to do background operation when it's active but it might degrade
739 * the performance of ongoing read/write operations.
740 */
741 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
742
743 /*
744 * This capability allows host controller driver to automatically
745 * enable runtime power management by itself instead of waiting
746 * for userspace to control the power management.
747 */
748 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
749
750 /*
751 * This capability allows the host controller driver to turn-on
752 * WriteBooster, if the underlying device supports it and is
753 * provisioned to be used. This would increase the write performance.
754 */
755 UFSHCD_CAP_WB_EN = 1 << 7,
756
757 /*
758 * This capability allows the host controller driver to use the
759 * inline crypto engine, if it is present
760 */
761 UFSHCD_CAP_CRYPTO = 1 << 8,
762
763 /*
764 * This capability allows the controller regulators to be put into
765 * lpm mode aggressively during clock gating.
766 * This would increase power savings.
767 */
768 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
769
770 /*
771 * This capability allows the host controller driver to use DeepSleep,
772 * if it is supported by the UFS device. The host controller driver must
773 * support device hardware reset via the hba->device_reset() callback,
774 * in order to exit DeepSleep state.
775 */
776 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
777
778 /*
779 * This capability allows the host controller driver to use temperature
780 * notification if it is supported by the UFS device.
781 */
782 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
783
784 /*
785 * Enable WriteBooster when scaling up the clock and disable
786 * WriteBooster when scaling the clock down.
787 */
788 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
789 };
790
791 struct ufs_hba_variant_params {
792 struct devfreq_dev_profile devfreq_profile;
793 struct devfreq_simple_ondemand_data ondemand_data;
794 u16 hba_enable_delay_us;
795 u32 wb_flush_threshold;
796 };
797
798 struct ufs_hba_monitor {
799 unsigned long chunk_size;
800
801 unsigned long nr_sec_rw[2];
802 ktime_t total_busy[2];
803
804 unsigned long nr_req[2];
805 /* latencies*/
806 ktime_t lat_sum[2];
807 ktime_t lat_max[2];
808 ktime_t lat_min[2];
809
810 u32 nr_queued[2];
811 ktime_t busy_start_ts[2];
812
813 ktime_t enabled_ts;
814 bool enabled;
815 };
816
817 /**
818 * struct ufshcd_res_info_t - MCQ related resource regions
819 *
820 * @name: resource name
821 * @resource: pointer to resource region
822 * @base: register base address
823 */
824 struct ufshcd_res_info {
825 const char *name;
826 struct resource *resource;
827 void __iomem *base;
828 };
829
830 enum ufshcd_res {
831 RES_UFS,
832 RES_MCQ,
833 RES_MCQ_SQD,
834 RES_MCQ_SQIS,
835 RES_MCQ_CQD,
836 RES_MCQ_CQIS,
837 RES_MCQ_VS,
838 RES_MAX,
839 };
840
841 /**
842 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
843 *
844 * @offset: Doorbell Address Offset
845 * @stride: Steps proportional to queue [0...31]
846 * @base: base address
847 */
848 struct ufshcd_mcq_opr_info_t {
849 unsigned long offset;
850 unsigned long stride;
851 void __iomem *base;
852 };
853
854 enum ufshcd_mcq_opr {
855 OPR_SQD,
856 OPR_SQIS,
857 OPR_CQD,
858 OPR_CQIS,
859 OPR_MAX,
860 };
861
862 /**
863 * struct ufs_hba - per adapter private structure
864 * @mmio_base: UFSHCI base register address
865 * @ucdl_base_addr: UFS Command Descriptor base address
866 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
867 * @utmrdl_base_addr: UTP Task Management Descriptor base address
868 * @ucdl_dma_addr: UFS Command Descriptor DMA address
869 * @utrdl_dma_addr: UTRDL DMA address
870 * @utmrdl_dma_addr: UTMRDL DMA address
871 * @host: Scsi_Host instance of the driver
872 * @dev: device handle
873 * @ufs_device_wlun: WLUN that controls the entire UFS device.
874 * @hwmon_device: device instance registered with the hwmon core.
875 * @curr_dev_pwr_mode: active UFS device power mode.
876 * @uic_link_state: active state of the link to the UFS device.
877 * @rpm_lvl: desired UFS power management level during runtime PM.
878 * @spm_lvl: desired UFS power management level during system PM.
879 * @pm_op_in_progress: whether or not a PM operation is in progress.
880 * @ahit: value of Auto-Hibernate Idle Timer register.
881 * @lrb: local reference block
882 * @outstanding_tasks: Bits representing outstanding task requests
883 * @outstanding_lock: Protects @outstanding_reqs.
884 * @outstanding_reqs: Bits representing outstanding transfer requests
885 * @capabilities: UFS Controller Capabilities
886 * @mcq_capabilities: UFS Multi Circular Queue capabilities
887 * @nutrs: Transfer Request Queue depth supported by controller
888 * @nortt - Max outstanding RTTs supported by controller
889 * @nutmrs: Task Management Queue depth supported by controller
890 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
891 * @ufs_version: UFS Version to which controller complies
892 * @vops: pointer to variant specific operations
893 * @vps: pointer to variant specific parameters
894 * @priv: pointer to variant specific private data
895 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
896 * @irq: Irq number of the controller
897 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
898 * @dev_ref_clk_freq: reference clock frequency
899 * @quirks: bitmask with information about deviations from the UFSHCI standard.
900 * @dev_quirks: bitmask with information about deviations from the UFS standard.
901 * @tmf_tag_set: TMF tag set.
902 * @tmf_queue: Used to allocate TMF tags.
903 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
904 * @active_uic_cmd: handle of active UIC command
905 * @uic_cmd_mutex: mutex for UIC command
906 * @uic_async_done: completion used during UIC processing
907 * @ufshcd_state: UFSHCD state
908 * @eh_flags: Error handling flags
909 * @intr_mask: Interrupt Mask Bits
910 * @ee_ctrl_mask: Exception event control mask
911 * @ee_drv_mask: Exception event mask for driver
912 * @ee_usr_mask: Exception event mask for user (set via debugfs)
913 * @ee_ctrl_mutex: Used to serialize exception event information.
914 * @is_powered: flag to check if HBA is powered
915 * @shutting_down: flag to check if shutdown has been invoked
916 * @host_sem: semaphore used to serialize concurrent contexts
917 * @eh_wq: Workqueue that eh_work works on
918 * @eh_work: Worker to handle UFS errors that require s/w attention
919 * @eeh_work: Worker to handle exception events
920 * @errors: HBA errors
921 * @uic_error: UFS interconnect layer error status
922 * @saved_err: sticky error mask
923 * @saved_uic_err: sticky UIC error mask
924 * @ufs_stats: various error counters
925 * @force_reset: flag to force eh_work perform a full reset
926 * @force_pmc: flag to force a power mode change
927 * @silence_err_logs: flag to silence error logs
928 * @dev_cmd: ufs device management command information
929 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
930 * @nop_out_timeout: NOP OUT timeout value
931 * @dev_info: information about the UFS device
932 * @auto_bkops_enabled: to track whether bkops is enabled in device
933 * @vreg_info: UFS device voltage regulator information
934 * @clk_list_head: UFS host controller clocks list node head
935 * @use_pm_opp: Indicates whether OPP based scaling is used or not
936 * @req_abort_count: number of times ufshcd_abort() has been called
937 * @lanes_per_direction: number of lanes per data direction between the UFS
938 * controller and the UFS device.
939 * @pwr_info: holds current power mode
940 * @max_pwr_info: keeps the device max valid pwm
941 * @clk_gating: information related to clock gating
942 * @caps: bitmask with information about UFS controller capabilities
943 * @devfreq: frequency scaling information owned by the devfreq core
944 * @clk_scaling: frequency scaling information owned by the UFS driver
945 * @system_suspending: system suspend has been started and system resume has
946 * not yet finished.
947 * @is_sys_suspended: UFS device has been suspended because of system suspend
948 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
949 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
950 * device is known or not.
951 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
952 * @clk_scaling_lock: used to serialize device commands and clock scaling
953 * @desc_size: descriptor sizes reported by device
954 * @scsi_block_reqs_cnt: reference counting for scsi block requests
955 * @bsg_dev: struct device associated with the BSG queue
956 * @bsg_queue: BSG queue associated with the UFS controller
957 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
958 * management) after the UFS device has finished a WriteBooster buffer
959 * flush or auto BKOP.
960 * @monitor: statistics about UFS commands
961 * @crypto_capabilities: Content of crypto capabilities register (0x100)
962 * @crypto_cap_array: Array of crypto capabilities
963 * @crypto_cfg_register: Start of the crypto cfg array
964 * @crypto_profile: the crypto profile of this hba (if applicable)
965 * @debugfs_root: UFS controller debugfs root directory
966 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
967 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
968 * ee_ctrl_mask
969 * @luns_avail: number of regular and well known LUNs supported by the UFS
970 * device
971 * @nr_hw_queues: number of hardware queues configured
972 * @nr_queues: number of Queues of different queue types
973 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
974 * ufshcd_resume_complete()
975 * @ext_iid_sup: is EXT_IID is supported by UFSHC
976 * @mcq_sup: is mcq supported by UFSHC
977 * @mcq_enabled: is mcq ready to accept requests
978 * @res: array of resource info of MCQ registers
979 * @mcq_base: Multi circular queue registers base address
980 * @uhq: array of supported hardware queues
981 * @dev_cmd_queue: Queue for issuing device management commands
982 * @mcq_opr: MCQ operation and runtime registers
983 * @ufs_rtc_update_work: A work for UFS RTC periodic update
984 * @pm_qos_req: PM QoS request handle
985 * @pm_qos_enabled: flag to check if pm qos is enabled
986 * @critical_health_count: count of critical health exceptions
987 * @dev_lvl_exception_count: count of device level exceptions since last reset
988 * @dev_lvl_exception_id: vendor specific information about the
989 * device level exception event.
990 */
991 struct ufs_hba {
992 void __iomem *mmio_base;
993
994 /* Virtual memory reference */
995 struct utp_transfer_cmd_desc *ucdl_base_addr;
996 struct utp_transfer_req_desc *utrdl_base_addr;
997 struct utp_task_req_desc *utmrdl_base_addr;
998
999 /* DMA memory reference */
1000 dma_addr_t ucdl_dma_addr;
1001 dma_addr_t utrdl_dma_addr;
1002 dma_addr_t utmrdl_dma_addr;
1003
1004 struct Scsi_Host *host;
1005 struct device *dev;
1006 struct scsi_device *ufs_device_wlun;
1007
1008 #ifdef CONFIG_SCSI_UFS_HWMON
1009 struct device *hwmon_device;
1010 #endif
1011
1012 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
1013 enum uic_link_state uic_link_state;
1014 /* Desired UFS power management level during runtime PM */
1015 enum ufs_pm_level rpm_lvl;
1016 /* Desired UFS power management level during system PM */
1017 enum ufs_pm_level spm_lvl;
1018 int pm_op_in_progress;
1019
1020 /* Auto-Hibernate Idle Timer register value */
1021 u32 ahit;
1022
1023 struct ufshcd_lrb *lrb;
1024
1025 unsigned long outstanding_tasks;
1026 spinlock_t outstanding_lock;
1027 unsigned long outstanding_reqs;
1028
1029 u32 capabilities;
1030 int nutrs;
1031 int nortt;
1032 u32 mcq_capabilities;
1033 int nutmrs;
1034 u32 reserved_slot;
1035 u32 ufs_version;
1036 const struct ufs_hba_variant_ops *vops;
1037 struct ufs_hba_variant_params *vps;
1038 void *priv;
1039 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1040 size_t sg_entry_size;
1041 #endif
1042 unsigned int irq;
1043 bool is_irq_enabled;
1044 enum ufs_ref_clk_freq dev_ref_clk_freq;
1045
1046 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1047
1048 unsigned int android_quirks; /* for UFSHCD_ANDROID_QUIRK_* flags */
1049
1050 /* Device deviations from standard UFS device spec. */
1051 unsigned int dev_quirks;
1052
1053 struct blk_mq_tag_set tmf_tag_set;
1054 struct request_queue *tmf_queue;
1055 struct request **tmf_rqs;
1056
1057 struct uic_command *active_uic_cmd;
1058 struct mutex uic_cmd_mutex;
1059 struct completion *uic_async_done;
1060
1061 enum ufshcd_state ufshcd_state;
1062 u32 eh_flags;
1063 u32 intr_mask;
1064 u16 ee_ctrl_mask;
1065 u16 ee_drv_mask;
1066 u16 ee_usr_mask;
1067 struct mutex ee_ctrl_mutex;
1068 bool is_powered;
1069 bool shutting_down;
1070 struct semaphore host_sem;
1071
1072 /* Work Queues */
1073 struct workqueue_struct *eh_wq;
1074 struct work_struct eh_work;
1075 struct work_struct eeh_work;
1076
1077 /* HBA Errors */
1078 u32 errors;
1079 u32 uic_error;
1080 u32 saved_err;
1081 u32 saved_uic_err;
1082 struct ufs_stats ufs_stats;
1083 bool force_reset;
1084 bool force_pmc;
1085 bool silence_err_logs;
1086
1087 /* Device management request data */
1088 struct ufs_dev_cmd dev_cmd;
1089 ktime_t last_dme_cmd_tstamp;
1090 int nop_out_timeout;
1091
1092 /* Keeps information of the UFS device connected to this host */
1093 struct ufs_dev_info dev_info;
1094 bool auto_bkops_enabled;
1095 struct ufs_vreg_info vreg_info;
1096 struct list_head clk_list_head;
1097 bool use_pm_opp;
1098
1099 /* Number of requests aborts */
1100 int req_abort_count;
1101
1102 /* Number of lanes available (1 or 2) for Rx/Tx */
1103 u32 lanes_per_direction;
1104 struct ufs_pa_layer_attr pwr_info;
1105 struct ufs_pwr_mode_info max_pwr_info;
1106
1107 struct ufs_clk_gating clk_gating;
1108 /* Control to enable/disable host capabilities */
1109 u32 caps;
1110
1111 struct devfreq *devfreq;
1112 struct ufs_clk_scaling clk_scaling;
1113 bool system_suspending;
1114 bool is_sys_suspended;
1115
1116 enum bkops_status urgent_bkops_lvl;
1117 bool is_urgent_bkops_lvl_checked;
1118
1119 struct mutex wb_mutex;
1120 struct rw_semaphore clk_scaling_lock;
1121 atomic_t scsi_block_reqs_cnt;
1122
1123 struct device bsg_dev;
1124 struct request_queue *bsg_queue;
1125 struct delayed_work rpm_dev_flush_recheck_work;
1126
1127 struct ufs_hba_monitor monitor;
1128
1129 #ifdef CONFIG_SCSI_UFS_CRYPTO
1130 union ufs_crypto_capabilities crypto_capabilities;
1131 union ufs_crypto_cap_entry *crypto_cap_array;
1132 u32 crypto_cfg_register;
1133 struct blk_crypto_profile crypto_profile;
1134 #endif
1135 #ifdef CONFIG_DEBUG_FS
1136 struct dentry *debugfs_root;
1137 struct delayed_work debugfs_ee_work;
1138 u32 debugfs_ee_rate_limit_ms;
1139 #endif
1140 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1141 struct fault_attr trigger_eh_attr;
1142 struct fault_attr timeout_attr;
1143 #endif
1144 u32 luns_avail;
1145 unsigned int nr_hw_queues;
1146 unsigned int nr_queues[HCTX_MAX_TYPES];
1147 bool complete_put;
1148 bool ext_iid_sup;
1149 bool scsi_host_added;
1150 bool mcq_sup;
1151 bool lsdb_sup;
1152 bool mcq_enabled;
1153 struct ufshcd_res_info res[RES_MAX];
1154 void __iomem *mcq_base;
1155 struct ufs_hw_queue *uhq;
1156 struct ufs_hw_queue *dev_cmd_queue;
1157 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1158
1159 struct delayed_work ufs_rtc_update_work;
1160 struct pm_qos_request pm_qos_req;
1161 bool pm_qos_enabled;
1162
1163 int critical_health_count;
1164 atomic_t dev_lvl_exception_count;
1165 u64 dev_lvl_exception_id;
1166
1167 ANDROID_OEM_DATA(1);
1168 };
1169
1170 /**
1171 * struct ufs_hw_queue - per hardware queue structure
1172 * @mcq_sq_head: base address of submission queue head pointer
1173 * @mcq_sq_tail: base address of submission queue tail pointer
1174 * @mcq_cq_head: base address of completion queue head pointer
1175 * @mcq_cq_tail: base address of completion queue tail pointer
1176 * @sqe_base_addr: submission queue entry base address
1177 * @sqe_dma_addr: submission queue dma address
1178 * @cqe_base_addr: completion queue base address
1179 * @cqe_dma_addr: completion queue dma address
1180 * @max_entries: max number of slots in this hardware queue
1181 * @id: hardware queue ID
1182 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1183 * @sq_lock: serialize submission queue access
1184 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1185 * @cq_head_slot: current slot to which CQ head pointer is pointing
1186 * @cq_lock: Synchronize between multiple polling instances
1187 * @sq_mutex: prevent submission queue concurrent access
1188 */
1189 struct ufs_hw_queue {
1190 void __iomem *mcq_sq_head;
1191 void __iomem *mcq_sq_tail;
1192 void __iomem *mcq_cq_head;
1193 void __iomem *mcq_cq_tail;
1194
1195 struct utp_transfer_req_desc *sqe_base_addr;
1196 dma_addr_t sqe_dma_addr;
1197 struct cq_entry *cqe_base_addr;
1198 dma_addr_t cqe_dma_addr;
1199 u32 max_entries;
1200 u32 id;
1201 u32 sq_tail_slot;
1202 spinlock_t sq_lock;
1203 u32 cq_tail_slot;
1204 u32 cq_head_slot;
1205 spinlock_t cq_lock;
1206 /* prevent concurrent access to submission queue */
1207 struct mutex sq_mutex;
1208 };
1209
1210 #define MCQ_QCFG_SIZE 0x40
1211
ufshcd_mcq_opr_offset(struct ufs_hba * hba,enum ufshcd_mcq_opr opr,int idx)1212 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1213 enum ufshcd_mcq_opr opr, int idx)
1214 {
1215 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1216 }
1217
ufshcd_mcq_cfg_offset(unsigned int reg,int idx)1218 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1219 {
1220 return reg + MCQ_QCFG_SIZE * idx;
1221 }
1222
1223 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
ufshcd_sg_entry_size(const struct ufs_hba * hba)1224 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1225 {
1226 return hba->sg_entry_size;
1227 }
1228
ufshcd_set_sg_entry_size(struct ufs_hba * hba,size_t sg_entry_size)1229 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1230 {
1231 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1232 hba->sg_entry_size = sg_entry_size;
1233 }
1234 #else
ufshcd_sg_entry_size(const struct ufs_hba * hba)1235 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1236 {
1237 return sizeof(struct ufshcd_sg_entry);
1238 }
1239
1240 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1241 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1242 #endif
1243
ufshcd_get_ucd_size(const struct ufs_hba * hba)1244 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1245 {
1246 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1247 }
1248
1249 /* Returns true if clocks can be gated. Otherwise false */
ufshcd_is_clkgating_allowed(struct ufs_hba * hba)1250 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1251 {
1252 return hba->caps & UFSHCD_CAP_CLK_GATING;
1253 }
ufshcd_can_hibern8_during_gating(struct ufs_hba * hba)1254 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1255 {
1256 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1257 }
ufshcd_is_clkscaling_supported(struct ufs_hba * hba)1258 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1259 {
1260 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1261 }
ufshcd_can_autobkops_during_suspend(struct ufs_hba * hba)1262 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1263 {
1264 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1265 }
ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba * hba)1266 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1267 {
1268 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1269 }
1270
ufshcd_is_intr_aggr_allowed(struct ufs_hba * hba)1271 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1272 {
1273 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1274 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1275 }
1276
ufshcd_can_aggressive_pc(struct ufs_hba * hba)1277 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1278 {
1279 return !!(ufshcd_is_link_hibern8(hba) &&
1280 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1281 }
1282
ufshcd_is_auto_hibern8_supported(struct ufs_hba * hba)1283 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1284 {
1285 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1286 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1287 }
1288
ufshcd_is_auto_hibern8_enabled(struct ufs_hba * hba)1289 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1290 {
1291 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1292 }
1293
ufshcd_is_wb_allowed(struct ufs_hba * hba)1294 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1295 {
1296 return hba->caps & UFSHCD_CAP_WB_EN;
1297 }
1298
ufshcd_enable_wb_if_scaling_up(struct ufs_hba * hba)1299 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1300 {
1301 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1302 }
1303
1304 #define ufsmcq_writel(hba, val, reg) \
1305 writel((val), (hba)->mcq_base + (reg))
1306 #define ufsmcq_readl(hba, reg) \
1307 readl((hba)->mcq_base + (reg))
1308
1309 #define ufsmcq_writelx(hba, val, reg) \
1310 writel_relaxed((val), (hba)->mcq_base + (reg))
1311 #define ufsmcq_readlx(hba, reg) \
1312 readl_relaxed((hba)->mcq_base + (reg))
1313
1314 #define ufshcd_writel(hba, val, reg) \
1315 writel((val), (hba)->mmio_base + (reg))
1316 #define ufshcd_readl(hba, reg) \
1317 readl((hba)->mmio_base + (reg))
1318
1319 /**
1320 * ufshcd_rmwl - perform read/modify/write for a controller register
1321 * @hba: per adapter instance
1322 * @mask: mask to apply on read value
1323 * @val: actual value to write
1324 * @reg: register address
1325 */
ufshcd_rmwl(struct ufs_hba * hba,u32 mask,u32 val,u32 reg)1326 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1327 {
1328 u32 tmp;
1329
1330 tmp = ufshcd_readl(hba, reg);
1331 tmp &= ~mask;
1332 tmp |= (val & mask);
1333 ufshcd_writel(hba, tmp, reg);
1334 }
1335
1336 void ufshcd_enable_irq(struct ufs_hba *hba);
1337 void ufshcd_disable_irq(struct ufs_hba *hba);
1338 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1339 int ufshcd_hba_enable(struct ufs_hba *hba);
1340 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1341 int ufshcd_link_recovery(struct ufs_hba *hba);
1342 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1343 void ufshcd_remove(struct ufs_hba *);
1344 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1345 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1346 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1347 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1348 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1349 void ufshcd_hba_stop(struct ufs_hba *hba);
1350 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1351 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1352 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1353 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1354 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1355 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1356 struct ufs_hw_queue *hwq);
1357 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1358 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1359 void ufshcd_mcq_enable(struct ufs_hba *hba);
1360 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1361
1362 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1363 struct dev_pm_opp *opp, void *data,
1364 bool scaling_down);
1365 /**
1366 * ufshcd_set_variant - set variant specific data to the hba
1367 * @hba: per adapter instance
1368 * @variant: pointer to variant specific data
1369 */
ufshcd_set_variant(struct ufs_hba * hba,void * variant)1370 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1371 {
1372 BUG_ON(!hba);
1373 hba->priv = variant;
1374 }
1375
1376 /**
1377 * ufshcd_get_variant - get variant specific data from the hba
1378 * @hba: per adapter instance
1379 */
ufshcd_get_variant(struct ufs_hba * hba)1380 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1381 {
1382 BUG_ON(!hba);
1383 return hba->priv;
1384 }
1385
1386 #ifdef CONFIG_PM
1387 extern int ufshcd_runtime_suspend(struct device *dev);
1388 extern int ufshcd_runtime_resume(struct device *dev);
1389 #endif
1390 #ifdef CONFIG_PM_SLEEP
1391 extern int ufshcd_system_suspend(struct device *dev);
1392 extern int ufshcd_system_resume(struct device *dev);
1393 extern int ufshcd_system_freeze(struct device *dev);
1394 extern int ufshcd_system_thaw(struct device *dev);
1395 extern int ufshcd_system_restore(struct device *dev);
1396 #endif
1397
1398 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1399 int agreed_gear,
1400 int adapt_val);
1401 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1402 u8 attr_set, u32 mib_val, u8 peer);
1403 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1404 u32 *mib_val, u8 peer);
1405 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1406 struct ufs_pa_layer_attr *desired_pwr_mode);
1407 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1408
1409 /* UIC command interfaces for DME primitives */
1410 #define DME_LOCAL 0
1411 #define DME_PEER 1
1412 #define ATTR_SET_NOR 0 /* NORMAL */
1413 #define ATTR_SET_ST 1 /* STATIC */
1414
ufshcd_dme_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1415 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1416 u32 mib_val)
1417 {
1418 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1419 mib_val, DME_LOCAL);
1420 }
1421
ufshcd_dme_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1422 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1423 u32 mib_val)
1424 {
1425 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1426 mib_val, DME_LOCAL);
1427 }
1428
ufshcd_dme_peer_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1429 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1430 u32 mib_val)
1431 {
1432 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1433 mib_val, DME_PEER);
1434 }
1435
ufshcd_dme_peer_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1436 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1437 u32 mib_val)
1438 {
1439 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1440 mib_val, DME_PEER);
1441 }
1442
ufshcd_dme_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1443 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1444 u32 attr_sel, u32 *mib_val)
1445 {
1446 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1447 }
1448
ufshcd_dme_peer_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1449 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1450 u32 attr_sel, u32 *mib_val)
1451 {
1452 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1453 }
1454
ufshcd_is_hs_mode(struct ufs_pa_layer_attr * pwr_info)1455 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1456 {
1457 return (pwr_info->pwr_rx == FAST_MODE ||
1458 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1459 (pwr_info->pwr_tx == FAST_MODE ||
1460 pwr_info->pwr_tx == FASTAUTO_MODE);
1461 }
1462
ufshcd_disable_host_tx_lcc(struct ufs_hba * hba)1463 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1464 {
1465 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1466 }
1467
1468 int ufshcd_query_flag_retry(struct ufs_hba *hba,
1469 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res);
1470
1471 int ufshcd_bkops_ctrl(struct ufs_hba *hba);
1472
1473 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1474 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1475 const struct ufs_dev_quirk *fixups);
1476 #define SD_ASCII_STD true
1477 #define SD_RAW false
1478 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1479 u8 **buf, bool ascii);
1480
1481 void ufshcd_hold(struct ufs_hba *hba);
1482 void ufshcd_release(struct ufs_hba *hba);
1483
1484 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1485
1486 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1487
1488 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1489
1490 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1491 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1492 struct ufs_ehs *ehs_rsp, int sg_cnt,
1493 struct scatterlist *sg_list, enum dma_data_direction dir);
1494 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1495 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1496 int ufshcd_suspend_prepare(struct device *dev);
1497 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1498 void ufshcd_resume_complete(struct device *dev);
1499 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1500 void ufshcd_pm_qos_init(struct ufs_hba *hba);
1501 void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1502
1503 /* Wrapper functions for safely calling variant operations */
ufshcd_vops_init(struct ufs_hba * hba)1504 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1505 {
1506 if (hba->vops && hba->vops->init)
1507 return hba->vops->init(hba);
1508
1509 return 0;
1510 }
1511
ufshcd_vops_phy_initialization(struct ufs_hba * hba)1512 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1513 {
1514 if (hba->vops && hba->vops->phy_initialization)
1515 return hba->vops->phy_initialization(hba);
1516
1517 return 0;
1518 }
1519
1520 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1521
1522 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1523 const char *prefix);
1524
1525 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1526 int ufshcd_write_ee_control(struct ufs_hba *hba);
1527 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1528 const u16 *other_mask, u16 set, u16 clr);
1529
1530 #endif /* End of Header */
1531