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/Documentation/driver-api/
Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
11 defaults to 1 byte
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
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/Documentation/virt/kvm/devices/
Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
21 Base address of the 256 KiB MPIC register space. Must be
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
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/Documentation/userspace-api/media/v4l/
Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
25 additionally output the histogram with 64 or 256 bins, resulting in four
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
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Dpixfmt-indexed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-indexed:
9 In this format each pixel is represented by an 8 bit index into a 256
16 .. flat-table:: Indexed Image Format
17 :header-rows: 2
18 :stub-columns: 0
20 * - Identifier
21 - Code
22 -
23 - :cspan:`7` Byte 0
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Dpixfmt-reserved.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-reserved:
11 register your own format, send an e-mail to the linux-media mailing list
15 copy to the linux-media mailing list for inclusion in this section. If
17 please make a proposal on the linux-media mailing list.
26 .. _reserved-formats:
28 .. flat-table:: Reserved Image Formats
29 :header-rows: 1
30 :stub-columns: 0
33 * - Identifier
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/Documentation/infiniband/
Duser_mad.rst9 "issm" device attached. For example, a two-port HCA will have two
19 request succeeds, a 32-bit id will be returned in the structure.
44 struct ib_user_mad + 256 bytes. For example:
53 mad = malloc(sizeof *mad + 256);
54 ret = read(fd, mad, sizeof *mad + 256);
55 if (ret != sizeof mad + 256) {
63 mad = malloc(sizeof *mad + 256);
64 ret = read(fd, mad, sizeof *mad + 256);
65 if (ret == -ENOSPC)) {
98 /* fill in mad->data */
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/Documentation/staging/
Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
27 to decide on the endianness of the bits within each byte. To get
28 the best error-detecting properties, this should correspond to the
29 order they're actually sent. For example, standard RS-232 serial is
30 little-endian; the most significant bit (sometimes used for parity)
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/Documentation/translations/zh_CN/infiniband/
Duser_mad.rst1 .. include:: ../disclaimer-zh_CN.rst
54 一个struct ib_user_mad + 256字节。比如说:
62 mad = malloc(sizeof *mad + 256);
63 ret = read(fd, mad, sizeof *mad + 256);
64 if (ret != sizeof mad + 256) {
72 mad = malloc(sizeof *mad + 256);
73 ret = read(fd, mad, sizeof *mad + 256);
74 if (ret == -ENOSPC)) {
106 /* fill in mad->data */
108 mad->hdr.id = my_agent; /* req.id from agent registration */
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/Documentation/filesystems/ext4/
Dinlinedata.rst1 .. SPDX-License-Identifier: GPL-2.0
4 -----------
19 256-byte inode (as of June 2015, when i_extra_isize is 28). Prior to
29 directory. Following that is a 56-byte space for an array of directory
Dattributes.rst1 .. SPDX-License-Identifier: GPL-2.0
4 -------------------
17 sb.inode_size = 256, then there are 256 - (128 + 28) = 100 bytes
18 available for in-inode extended attribute storage. The second place
32 .. list-table::
34 :header-rows: 1
36 * - Offset
37 - Type
38 - Name
39 - Description
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/Documentation/crypto/
Dapi-samples.rst5 -----------------------------------------------
7 This code encrypts some data with AES-256-XTS. For sake of example,
8 all inputs are random bytes, the encryption is done in-place, and it's
21 u8 iv[16]; /* AES-256-XTS takes a 16-byte IV */
22 u8 key[64]; /* AES-256-XTS takes a 64-byte key */
28 * In real-world use, a tfm and key are typically used for many
49 err = -ENOMEM;
56 err = -ENOMEM;
65 * Encrypt the data in-place.
94 -----------------------------------------------------------
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/Documentation/w1/slaves/
Dw1_ds2438.rst16 -----------
28 -----
36 When writing to sysfs file bits 2-7 are ignored, so it's safe to write ASCII.
40 -------
43 Internally when this file is read, the additional CRC byte is also obtained
48 -------
51 Internally when this file is read, the additional CRC byte is also obtained
56 --------
57 This file controls the 2-byte Offset Register of the chip.
58 Writing a 2-byte value will change the Offset Register, which changes the
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/Documentation/devicetree/bindings/eeprom/
Dat25.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Eggers <ceggers@arri.de>
15 - pattern: "^eeprom@[0-9a-f]{1,2}$"
16 - pattern: "^fram@[0-9a-f]{1,2}$"
26 - items:
27 - enum:
28 - anvo,anv32e61w
29 - atmel,at25256B
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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/Documentation/filesystems/
Dfscrypt.rst2 Filesystem-level encryption (fscrypt)
11 Note: "fscrypt" in this document refers to the kernel-level portion,
14 covers the kernel-level portion. For command-line examples of how to
20 <https://source.android.com/security/encryption/file-based>`_, over
25 Unlike dm-crypt, fscrypt operates at the filesystem level rather than
28 filesystem. This is useful for multi-user systems where each user's
29 data-at-rest needs to be cryptographically isolated from the others.
34 directly into supported filesystems --- currently ext4, F2FS, UBIFS,
44 fscrypt does not support encrypting files in-place. Instead, it
54 ---------------
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/Documentation/ABI/stable/
Dsysfs-class-tpm4 Contact: linux-integrity@vger.kernel.org
12 Contact: linux-integrity@vger.kernel.org
24 Contact: linux-integrity@vger.kernel.org
32 Contact: linux-integrity@vger.kernel.org
41 Manufacturer is a hex dump of the 4 byte manufacturer info
49 Contact: linux-integrity@vger.kernel.org
50 Description: The "durations" property shows the 3 vendor-specific values
72 Contact: linux-integrity@vger.kernel.org
81 Contact: linux-integrity@vger.kernel.org
89 Contact: linux-integrity@vger.kernel.org
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/Documentation/ABI/testing/
Dsysfs-driver-wacom4 Contact: linux-bluetooth@vger.kernel.org
14 Contact: linux-input@vger.kernel.org
25 Contact: linux-input@vger.kernel.org
35 Contact: linux-input@vger.kernel.org
44 Contact: linux-input@vger.kernel.org
54 Contact: linux-input@vger.kernel.org
63 Contact: linux-input@vger.kernel.org
70 Contact: linux-input@vger.kernel.org
72 When writing a 1024 byte raw image in Wacom Intuos 4
74 of the device. The image is a 64x32 pixel 4-bit gray image. The
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Dsysfs-driver-chromeos-acpi56 Returns firmware version for the read-only portion of the
79 256 to 511 Debug header GPIO 0 to GPIO 255.
121 Returns the SHA-1 or SHA-256 hash that is read out of the
132 Returns offset in CMOS bank 0 of the verified boot non-volatile
133 storage block, counting from the first writable CMOS byte
134 (that is, 'offset = 0' is the byte following the 14 bytes of
142 Return the size in bytes of the verified boot non-volatile
/Documentation/driver-api/mtd/
Dnand_ecc.rst2 NAND Error-correction Code
11 After that the speed was increased by 35-40%.
22 NAND flash (at least SLC one) typically has sectors of 256 bytes.
31 As I said before the ecc calculation is performed on sectors of 256
45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
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/Documentation/firmware-guide/acpi/
Dchromeos-acpi-device.rst1 .. SPDX-License-Identifier: GPL-2.0
11 .. flat-table:: Supported ACPI Objects
13 :header-rows: 1
15 * - Object
16 - Description
18 * - CHSW
19 - Chrome OS switch positions
21 * - HWID
22 - Chrome OS hardware ID
24 * - FWID
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/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr-props.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Krzysztof Kozlowski <krzk@kernel.org>
23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
36 revision-id:
37 $ref: /schemas/types.yaml#/definitions/uint32-array
39 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
50 - 64
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/Documentation/scsi/
Darcmsr_spec.rst11 ------------
13 - InitThread message and return code
15 2. Doorbell is used for RS-232 emulation
16 ----------------------------------------
35 ---------------------
46 4. RS-232 emulation
47 -------------------
49 Currently 128 byte buffer is used:
52 1st uint32_t Data length (1--124)
53 Byte 4--127 Max 124 bytes of data
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/Documentation/devicetree/bindings/net/
Dqcom-emac.txt11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
20 - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
21 - reg : Offset and length of the register region(s) for the device
22 - interrupts : Interrupt number used by this controller
25 - reg : The phy address
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/Documentation/filesystems/spufs/
Dspufs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
72 which normally is 256 kilobytes.
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
89 box, the return value is set to -1 and errno becomes EAGAIN.
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