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/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,gicp.txt2 -----------------------
11 - compatible: Must be "marvell,ap806-gicp"
13 - reg: Must be the address and size of the GICP SPI registers
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
18 - msi-controller: indicates that this is an MSI controller
22 gicp_spi: gicp-spi@3f0040 {
23 compatible = "marvell,ap806-gicp";
25 marvell,spi-ranges = <64 64>, <288 64>;
26 msi-controller;
/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt6 - reg: should contain two address length tuples
12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
13 interrupt-map = <
14 /* IDSEL 0x0E -mini PCI */
20 /* IDSEL 0x0F - PCI slot */
25 interrupt-parent = <&ipic>;
27 bus-range = <0x0 0x0>;
31 clock-frequency = <66666666>;
32 #interrupt-cells = <1>;
33 #size-cells = <2>;
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Dpci-iommu.txt12 * Bits [7:3] are the Device number.
33 -------------------
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
38 The property is an arbitrary number of tuples of
39 (rid-base,iommu,iommu-base,length).
41 Any RID r in the interval [rid-base, rid-base + length) is associated with
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
45 mapped to an IOMMU specifier per the iommu-map property.
52 #address-cells = <1>;
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Dpci-msi.txt12 * Bits [7:3] are the Device number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
44 following the rid-base.
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/Documentation/devicetree/bindings/leds/
Dleds-trigger-pattern.txt3 The pattern is given by a series of tuples, of brightness and duration (ms).
19 It will make the LED go gradually from zero-intensity to max (255) intensity in
24 255-| / \ / \ /
28 0-| / \/ \/
29 +---0----1----2----3----4----5----6------------> time (s)
32 use zero-time lengths (the brightness must be same as the previous tuple's). So
44 255-| +---------+ +---------+
48 0-| -----+ +----+ +----
49 +---0----1----2----3----4----5----6------------> time (s)
Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
48 function-enumerator:
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/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/Documentation/
Dconf.py1 # -*- coding: utf-8 -*-
4 # sphinx-quickstart on Fri Feb 12 13:51:46 2016.
21 # ------
32 major, minor, patch = sphinx.version_info[:3]
47 # -- General configuration ------------------------------------------------
60 if major >= 3:
61 if (major > 3) or (minor > 0 or patch >= 2):
171 #source_encoding = 'utf-8-sig'
213 # command-line options and find it for ourselves.
224 return c_version + '-' + c_release
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/Documentation/devicetree/bindings/sound/
Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
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/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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/Documentation/devicetree/bindings/mailbox/
Darm,mhuv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
33 - Data-transfer: Each transfer is made of one or more words, using one or more
36 - Doorbell: Each transfer is made up of single bit flag, using any one of the
49 - arm,mhuv2-tx
50 - arm,mhuv2-rx
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/Documentation/power/
Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
11 3. OPP Search Functions
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
29 The set of discrete tuples consisting of frequency and voltage pairs that
39 We can represent these as three OPPs as the following {Hz, uV} tuples:
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
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Denergy-model.rst1 .. SPDX-License-Identifier: GPL-2.0
8 -----------
12 subsystems willing to use that information to make energy-aware decisions.
18 each and every client subsystem to re-implement support for each and every
23 The power values might be expressed in micro-Watts or in an 'abstract scale'.
26 can be found in the Energy-Aware Scheduler documentation
27 Documentation/scheduler/sched-energy.rst. For some subsystems like thermal or
30 thus the real micro-Watts might be needed. An example of these requirements can
32 Documentation/driver-api/thermal/power_allocator.rst.
36 an 'abstract scale' deriving real energy in micro-Joules would not be possible.
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/Documentation/pcmcia/
Ddriver-changes.rst8 If `struct pcmcia_device *p_dev->config_flags` is set accordingly,
14 - CONF_AUTO_CHECK_VCC : check for matching Vcc
15 - CONF_AUTO_SET_VPP : set Vpp
16 - CONF_AUTO_AUDIO : auto-enable audio line, if required
17 - CONF_AUTO_SET_IO : set ioport resources (->resource[0,1])
18 - CONF_AUTO_SET_IOMEM : set first iomem resource (->resource[2])
20 * pcmcia_request_configuration -> pcmcia_enable_device (as of 2.6.36)
28 `struct pcmcia_device *p_dev->resource[2,3,4,5]` for up to four ioport
30 are reserved and may be used immediately -- until pcmcia_release_window()
35 `struct pcmcia_device *p_dev->resource[0,1]` for up to two ioport
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/Documentation/devicetree/bindings/mtd/
Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
/Documentation/devicetree/bindings/display/
Drenesas,du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
[all …]
/Documentation/networking/
Dcan_ucan_protocol.rst5 UCAN is the protocol used by the microcontroller-based USB-CAN
6 adapter that is integrated on System-on-Modules from Theobroma Systems
9 The UCAN protocol has been designed to be hardware-independent.
11 internally. All multi-byte integers are encoded as Little Endian.
44 ------------
51 ``wLength`` * Host to Device - Number of bytes to transmit
52 * Device to Host - Maximum Number of bytes to
58 --------------
64 ---------------
75 ------------------
[all …]
Dfilter.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _networking-filter:
10 ------
17 ------------
24 BPF allows a user-space program to attach a filter onto any socket and
49 The biggest user of this construct might be libpcap. Issuing a high-level
50 filter command like `tcpdump -i em1 port 22` passes through the libpcap
52 via SO_ATTACH_FILTER to the kernel. `tcpdump -i em1 port 22 -ddd`
57 qdisc layer, SECCOMP-BPF (SECure COMPuting [1]_), and lots of other places
60 .. [1] Documentation/userspace-api/seccomp_filter.rst
[all …]
Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
[all …]
/Documentation/filesystems/
Dpath-lookup.txt17 thus in every component during path look-up. Since 2.5.10 onwards, fast-walk
23 make dcache look-up lock-free.
30 are path-walk intensive tend to do path lookups starting from a common dentry
35 (including dcache look-up) completely "store-free" (so, no locks, atomics, or
36 even stores into cachelines of common dentries). This is known as "rcu-walk"
42 A name string specifies a start (root directory, cwd, fd-relative) and a
45 elements are sub-strings, separated by '/'.
49 the path given by the name's starting point (which we know in advance -- eg.
50 current->fs->cwd or current->fs->root) as the first parent of the lookup. Then
67 - find the start point of the walk;
[all …]
/Documentation/accel/qaic/
Daic100.rst1 .. SPDX-License-Identifier: GPL-2.0-only
10 The Qualcomm Cloud AI 100/AIC100 family of products (including SA9000P - part of
20 performance. AIC100 cards are multi-user capable and able to execute workloads
26 An AIC100 card consists of an AIC100 SoC, on-card DDR, and a set of misc
39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
44 hardware. AIC100 provides 3, 64-bit BARs.
54 From the host perspective, AIC100 has several key hardware components -
63 ---
71 ---
74 firmware of the card and performs on-card management tasks. It also
[all …]
/Documentation/filesystems/xfs/
Dxfs-online-fsck-design.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Heading 3 uses "----"
25 - To help kernel distributors understand exactly what the XFS online fsck
28 - To help people reading the code to familiarize themselves with the relevant
31 - To help developers maintaining the system by capturing the reasons
42 Parts 2 and 3 present a high level overview of how online fsck process works
59 - Provide a hierarchy of names through which application programs can associate
62 - Virtualize physical storage media across those names, and
64 - Retrieve the named data blobs at any time.
66 - Examine resource usage.
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