Searched +full:4 +full:- +full:cpu (Results 1 – 25 of 575) sorted by relevance
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| /Documentation/admin-guide/ |
| D | cputopology.rst | 2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
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| /Documentation/translations/zh_CN/core-api/ |
| D | cpu_hotplug.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cpu_hotplug.rst
79 hot-add/hot-remove。目前还没有定死规定。典型的用法是在启动时启动拓扑结构，这时
95 $ ls -lh /sys/devices/system/cpu
97 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
98 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
99 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
100 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
101 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
102 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
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| D | workqueue.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/core-api/workqueue.rst
109 每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当
139 参数 - ``@name`` , ``@flags`` 和 ``@max_active`` 。
148 ---------
202 --------------
234 0 w0 starts and burns CPU
236 15 w0 wakes up and burns CPU
238 20 w1 starts and burns CPU
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| /Documentation/tools/rtla/ |
| D | rtla-hwnoise.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 rtla-hwnoise
6 ------------------------------------------
7 Detect and quantify hardware-related noise
8 ------------------------------------------
22 of threads as a consequence, only non-maskable interrupts and hardware-related
38 In the example below, the **rtla hwnoise** tool is set to run on CPUs *1-7*
39 on a system with 8 cores/16 threads with hyper-threading enabled.
45 # rtla hwnoise -c 1-7 -T 1 -d 10m -q
46 Hardware-related Noise
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| /Documentation/core-api/ |
| D | cpu_hotplug.rst | 2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
53 CPU maps
66 after a CPU is available for kernel scheduling and ready to receive
67 interrupts from devices. Its cleared when a CPU is brought down using
69 migrated to another target CPU.
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| D | workqueue.rst | 32 worker thread per CPU and a single threaded (ST) wq had one worker
33 thread system-wide. A single MT wq needed to keep around the same
35 wq users over the years and with the number of CPU cores continuously
42 worker pool. An MT wq could provide only one execution context per CPU
60 * Use per-CPU unified worker pools shared by all wq to provide
85 worker-pools.
87 The cmwq design differentiates between the user-facing workqueues that
89 which manages worker-pools and processes the queued work items.
91 There are two worker-pools, one for normal work items and the other
92 for high priority ones, for each possible CPU and some extra
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| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
13 due to potential endianness mismatches between the CPU and the hardware device.
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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| /Documentation/translations/zh_CN/admin-guide/ |
| D | cputopology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/admin-guide/cputopology.rst
15 /sys/devices/system/cpu/cpuX/topology/。请阅读ABI文件：
16 Documentation/ABI/stable/sysfs-devices-system-cpu。
21 对于支持这个特性的体系结构，它必须在include/asm-XXX/topology.h中定义这些宏中的一部分::
23 #define topology_physical_package_id(cpu)
24 #define topology_die_id(cpu)
25 #define topology_cluster_id(cpu)
26 #define topology_core_id(cpu)
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| /Documentation/translations/zh_TW/admin-guide/ |
| D | cputopology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_TW.rst
4 :Original: Documentation/admin-guide/cputopology.rst
15 /sys/devices/system/cpu/cpuX/topology/。請閱讀ABI文件：
16 Documentation/ABI/stable/sysfs-devices-system-cpu。
21 對於支持這個特性的體系結構，它必須在include/asm-XXX/topology.h中定義這些宏中的一部分::
23 #define topology_physical_package_id(cpu)
24 #define topology_die_id(cpu)
25 #define topology_cluster_id(cpu)
26 #define topology_core_id(cpu)
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
45 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟件。
54 4、調用內核映像
58 -----------------
69 ---------------
81 -------------
90 4、調用內核映像
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
50 4、调用内核映像
54 -----------------
65 ---------------
77 -------------
86 4、调用内核映像
87 -------------
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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| /Documentation/arch/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - topology_num_threads_per_package()
54 - topology_num_cores_per_package()
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
19 output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
64 bits with ECC), the data flows to the CPU using a 128 bits parallel
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| /Documentation/scheduler/ |
| D | schedutil.rst | 15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
32 and CPU runqueues), which reflects their expected contribution when they
36 reflects the time an entity spends on the CPU, while 'runnable' reflects the
38 two metrics are the same, but once there is contention for the CPU 'running'
39 will decrease to reflect the fraction of time each task spends on the CPU
45 Frequency / CPU Invariance
48 Because consuming the CPU for 50% at 1GHz is not the same as consuming the CPU
49 for 50% at 2GHz, nor is running 50% on a LITTLE CPU the same as running 50% on
50 a big CPU, we allow architectures to scale the time delta with two ratios, one
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| D | sched-stats.rst | 16 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
17 release). Some counters make more sense to be per-runqueue; other to be
18 per-domain. Note that domains (and their associated information) will only
22 statistics for each cpu listed, and there may well be more than one
38 Note that any such script will necessarily be version-specific, as the main
42 CPU statistics
43 --------------
44 cpu<N> 1 2 3 4 5 6 7 8 9
55 4) # of times schedule() left the processor idle
60 6) # of times try_to_wake_up() was called to wake up the local cpu
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| /Documentation/translations/zh_CN/scheduler/ |
| D | sched-bwc.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/scheduler/sched-bwc.rst
19 SCHED_RT的情况在Documentation/scheduler/sched-rt-group.rst中有涉及。
29 它以需求为基础被转移到cpu-local“筒仓”，在每次更新中转移的数量是可调整的，被描述为“片“（时
33 --------
37 传统的（UP-EDF）带宽控制是这样的:
61 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
64 ----
69 :ref:`Documentation/admin-guide/cgroup-v2.rst <cgroup-v2-cpu>`.
71 - cpu.cfs_quota_us：在一个时期内补充的运行时间（微秒）。
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| /Documentation/translations/ko_KR/ |
| D | memory-barriers.txt | 2 This is a version of Documentation/memory-barriers.txt translated into Korean.
15 Documentation/memory-barriers.txt
39 일부 이상한 점들은 공식적인 메모리 일관성 모델과 tools/memory-model/ 에 있는
60 해당 배리어의 명시적 사용이 불필요해서 no-op 이 될수도 있음을 알아두시기
76 - 디바이스 오퍼레이션.
77 - 보장사항.
81 - 메모리 배리어의 종류.
82 - 메모리 배리어에 대해 가정해선 안될 것.
83 - 주소 데이터 의존성 배리어 (역사적).
84 - 컨트롤 의존성.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc. LPASS CPU dai driver
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
15 of MI2S interface for audio data transfer on external codecs. LPASS cpu driver
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
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| /Documentation/ |
| D | memory-barriers.txt | 19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-cpu-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CPU Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-cpu-clk
26 maxItems: 4
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,liointc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K series chips, as the primary package interrupt controller which
17 1.The Loongson-2K0500 is a single core CPU;
18 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19 need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
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