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/Documentation/devicetree/bindings/arm/
Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
11 - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
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Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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Dfsl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
17 - description: i.MX1 based Boards
19 - enum:
20 - armadeus,imx1-apf9328
21 - fsl,imx1ads
22 - const: fsl,imx1
24 - description: i.MX23 based Boards
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/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
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/Documentation/devicetree/bindings/sound/
Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
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/Documentation/translations/zh_TW/arch/arm64/
Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
11 M: Will Deacon <will.deacon@arm.com>
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 “內核特性（Kernel Features）”->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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/Documentation/translations/zh_CN/arch/arm64/
Dsilicon-errata.txt1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
9 M: Will Deacon <will.deacon@arm.com>
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/Documentation/arch/arm/stm32/
Doverview.rst6 ------------
8 The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
9 Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
13 -------------
21 ------
24 contained in arch/arm/mach-stm32
26 There is a generic board board-dt.c in the mach folder which support
32 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
33 - Ludovic Barre <ludovic.barre@st.com>
34 - Gerald Baeza <gerald.baeza@st.com>
/Documentation/devicetree/bindings/interrupt-controller/
Darm,nvic.txt4 Cortex-M based processor cores. The NVIC implemented on different SoCs
9 - compatible : should be one of:
10 "arm,v6m-nvic"
11 "arm,v7m-nvic"
12 "arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
29 intc: interrupt-controller@e000e100 {
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/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
30 - clocks:
34 - clock-indices:
37 - clock-output-names:
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/Documentation/arch/arm/keystone/
Doverview.rst6 ------------
7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
11 Following SoCs & EVMs are currently supported:-
23 http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
30 K2E - 66AK2E05:
37 https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
44 K2L - TCI6630K2L:
50 https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
53 -------------
60 k2hk-evm.dts
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/Documentation/translations/zh_TW/arch/arm/
DBooting11 ---------------------------------------------------------------------
24 ---------------------------------------------------------------------
32 以下文檔適用於 2.4.18-rmk6 及以上版本。
48 -------------------
60 -----------------------------
71 Documentation/admin-guide/kernel-parameters.rst。
75 --------------------------
83 (詳見 linux/arch/arm/tools/mach-types )。
86 ------------------
95 --------------------------------
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/Documentation/translations/zh_CN/arch/arm/
DBooting11 ---------------------------------------------------------------------
24 ---------------------------------------------------------------------
32 以下文档适用于 2.4.18-rmk6 及以上版本。
48 -------------------
60 -----------------------------
71 Documentation/admin-guide/kernel-parameters.rst。
75 --------------------------
83 (详见 linux/arch/arm/tools/mach-types )。
86 ------------------
95 --------------------------------
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/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/Documentation/arch/arm/
Dbooting.rst9 The following documentation is relevant to 2.4.18-rmk6 and beyond.
28 ---------------------------
44 -----------------------------
60 Documentation/admin-guide/kernel-parameters.rst.
64 --------------------------
69 MANDATORY except for DT-only platforms
75 value to the kernel. (see linux/arch/arm/tools/mach-types). This
78 For DT-only platforms, the machine type will be determined by device
83 ------------------
95 --------------------------------
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