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/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
14 converts DSI/DPI to eDP/DP .
19 - items:
20 - enum:
21 - toshiba,tc358867
22 - toshiba,tc9595
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Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPI DSI to eDP Video Format Converter
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
14 mobile devices with embedded panel resolutions up to 2048 x 1536. The
15 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
17 device outputs eDP v1.4, one or two lanes, at a link rate of up to
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Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
34 Set if the HPD line on the bridge isn't hooked up to anything or is
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/Documentation/gpu/
Dtegra.rst7 buffer provided directly by the CPU, to its clients via channels. Software,
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
22 outputs, such as RGB, HDMI, DSI, and DisplayPort.
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
31 order to expose their functionality to users. The infrastructure that supports
35 tree for matching device nodes, adding the required clients to a list. Drivers
37 to the logical host1x device.
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/Documentation/devicetree/bindings/display/msm/
Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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Dqcom,mdp5.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
[all …]
/Documentation/devicetree/bindings/clock/
Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
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/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 series of SoCs which transfers the image data from a video memory buffer to
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
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