Searched +full:ip +full:- +full:core (Results 1 – 25 of 319) sorted by relevance
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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| D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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| /Documentation/devicetree/bindings/ptp/ |
| D | ptp-ines.txt | 1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
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| /Documentation/devicetree/bindings/pwm/ |
| D | microchip,corepwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
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| D | snps,dw-apb-timers-pwm2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Synopsys DW-APB timers PWM controller
11 - Ben Dooks <ben.dooks@sifive.com>
15 mode. The IP core can be generated with various options which can
19 The IP block has a version register so this can be used for detection
20 instead of having to encode the IP version number in the device tree
24 - $ref: pwm.yaml#
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
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| D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
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| /Documentation/devicetree/bindings/input/ |
| D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
11 - name : Should be "GAISLER_APBPS2" or "01_060"
12 - reg : Address and length of the register set for the device
13 - interrupts : Interrupt numbers for this device
15 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,axi-dac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI DAC IP core
10 - Nuno Sa <nuno.sa@analog.com>
13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device
17 interface for the actual DAC, while this IP core will interface
18 to the data-lines of the DAC and handle the streaming of data from
26 - adi,axi-dac-9.1.b
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| /Documentation/devicetree/bindings/media/ |
| D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
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| D | samsung,exynos4210-fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 fimc<n>, where <n> is an integer specifying the IP block instance.
20 - samsung,exynos4210-fimc
21 - samsung,exynos4212-fimc
22 - samsung,s5pv210-fimc
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,axi-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
26 - adi,axi-adc-10.0.a
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-grgpio.txt | 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/devicetree/bindings/sound/ |
| D | xlnx,spdif.txt | 1 Device-Tree bindings for Xilinx SPDIF IP
3 The IP supports playback and capture of SPDIF audio
6 - compatible: "xlnx,spdif-2.0"
7 - clock-names: List of input clocks.
9 - clocks: Input clock specifier. Refer to common clock bindings.
10 - reg: Base address and address length of the IP core instance.
11 - interrupts-parent: Phandle for interrupt controller.
12 - interrupts: List of Interrupt numbers.
13 - xlnx,spdif-mode: 0 :- receiver mode
14 1 :- transmitter mode
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| D | xlnx,audio-formatter.txt | 1 Device-Tree bindings for Xilinx PL audio formatter
3 The IP core supports DMA, data formatting(AES<->PCM conversion)
7 - compatible: "xlnx,audio-formatter-1.0"
8 - interrupt-names: Names specified to list of interrupts in same
13 - interrupts-parent: Phandle for interrupt controller.
14 - interrupts: List of Interrupt numbers.
15 - reg: Base address and size of the IP core instance.
16 - clock-names: List of input clocks.
18 - clocks: Input clock specifier. Refer to common clock bindings.
22 compatible = "xlnx,audio-formatter-1.0";
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| /Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /Documentation/devicetree/bindings/i2c/ |
| D | opencores,i2c-ocores.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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| D | microchip,corei2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
32 clock-frequency:
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| /Documentation/devicetree/bindings/usb/ |
| D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
11 - name : Should be "GAISLER_USBDC" or "01_021"
13 - reg : Address and length of the register set for the device
15 - interrupts : Interrupt numbers for this device. Either one interrupt number
21 - epobufsizes : Array of buffer sizes for OUT endpoints when they differ
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
27 - epibufsizes : Array of buffer sizes for IN endpoints when they differ
30 each IN endpoint of the core. Fewer entries overrides the default sizes
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| /Documentation/devicetree/bindings/net/can/ |
| D | grcan.txt | 3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
12 - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
14 - reg : Address and length of the register set for the device
16 - freq : Frequency of the external oscillator clock in Hz (the frequency of
19 - interrupts : Interrupt number for this device
23 - systemid : If not present or if the value of the least significant 16 bits
24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
27 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/networking/caif/ |
| D | linux_caif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| ST-Ericsson AB 2010
17 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
22 ST-Ericsson modems support a number of transports between modem
31 * CAIF Socket Layer and GPRS IP Interface.
32 * CAIF Core Protocol Implementation
39 ! +------+ +------+
40 ! +------+! +------+!
41 ! ! IP !! !Socket!!
42 +-------> !interf!+ ! API !+ <- CAIF Client APIs
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| /Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
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| /Documentation/devicetree/bindings/thermal/ |
| D | imx8mm-thermal.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/thermal/imx8mm-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 i.MX8MM has TMU IP to allow temperature measurement, there are
16 currently two distinct major versions of the IP that is supported
17 by a single driver. The IP versions are named v1 and v2, v1 is
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| /Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 2 Core Driver Infrastructure
9 "IPs" (Intellectual Property blocks). Each IP encapsulates certain
13 the initialization and operation of each IP. There are also a bunch
32 This was a dedicated IP on older pre-vega chips, but has since
43 their interrupts into this IP and it aggregates them into a set of
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
61 This is a multi-purpose DMA engine. The kernel driver uses it for
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
74 VCN (Video Core Next)
75 This is the multi-media engine. It handles video and image encode and
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