Searched +full:machine +full:- +full:level (Results 1 – 25 of 177) sorted by relevance
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| /Documentation/arch/arm/ |
| D | interrupts.rst | 5 2.5.2-rmk5:
7 major architecture-specific subsystems.
10 MMU TLB. Each MMU TLB variant is now handled completely separately -
19 Unfortunately, this means that machine types that touch the irq_desc[]
20 array (basically all machine types) will break, and this means every
21 machine type that we currently have.
26 SA1100 ------------> Neponset -----------> SA1111
28 -----------> USAR
30 -----------> SMC9196
33 exclusive of each other - if you're processing one interrupt from the
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| D | arm.rst | 9 ---------------------
17 in the top level Makefile. However, if you don't have the ARM Linux ELF
21 If you wish to cross-compile, then alter the following lines in the top
22 level make file::
36 CROSS_COMPILE=<your-path-to-your-compiler-without-gcc>
40 CROSS_COMPILE=arm-linux-
48 ---------------
54 Bug reports should be sent to linux-arm-kernel@lists.arm.linux.org.uk,
64 -------------
66 Several new include directories have been created under include/asm-arm,
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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| D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
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| D | thead,c900-aclint-mswi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
15 - enum:
16 - sophgo,sg2042-aclint-mswi
17 - const: thead,c900-aclint-mswi
22 interrupts-extended:
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| /Documentation/arch/riscv/ |
| D | uabi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
7 ------------------------------------
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
21 single-letter extensions and before any higher-privileged extensions.
29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
33 #. Standard machine-level extensions (starting with 'Zxm') will be listed
34 after any lower-privileged, standard extensions. If multiple machine-level
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| /Documentation/virt/ |
| D | paravirt_ops.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
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| /Documentation/sound/soc/ |
| D | overview.rst | 6 provide better ALSA support for embedded system-on-chip processors (e.g.
9 had some limitations:-
12 CPU. This is not ideal and leads to code duplication - for example,
18 machine specific code to re-route audio, enable amps, etc., after such an
31 features :-
50 * Machine specific controls: Allow machines to add controls to the sound card
54 multiple re-usable component drivers :-
60 on any architecture and machine.
66 * Machine class driver: The machine driver class acts as the glue that
68 "sound card device". It handles any machine specific controls and
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| D | dapm.rst | 11 management frameworks and, as such, can easily co-exist with them.
32 The graph for the STM32MP1-DK1 sound card is shown in picture:
34 .. kernel-figure:: dapm-graph.svg
49 Platform/Machine domain
52 Is platform/machine and user action specific, is configured by the
53 machine driver and responds to asynchronous events e.g when HP
139 (Widgets are defined in include/sound/soc-dapm.h)
142 There are convenience macros defined in soc-dapm.h that can be used to quickly
150 ---------------------
179 -------------------
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| /Documentation/power/regulator/ |
| D | overview.rst | 26 - Regulator
27 - Electronic device that supplies power to other devices.
31 Input Voltage -> Regulator -> Output Voltage
34 - PMIC
35 - Power Management IC. An IC that contains numerous
39 - Consumer
40 - Electronic device that is supplied power by a regulator.
41 Consumers can be classified into two types:-
52 - Power Domain
53 - Electronic circuit that is supplied its input power by the
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| /Documentation/arch/x86/x86_64/ |
| D | 5level-paging.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 5-level paging
9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
31 In this case additional page table level -- p4d -- will be folded at
34 User-space and large virtual address space
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| D | boot-options.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 Machine check
15 Disable machine check
17 Disable CMCI(Corrected Machine Check Interrupt) that
39 Do not opt-in to Local MCE delivery. Use legacy method
42 Enable logging of machine checks left over from booting.
46 to make sure you log even machine check events that result
49 Disable boot machine check logging.
52 Sets the time in us to wait for other CPUs on machine checks. 0
55 Don't overwrite the bios-set CMCI threshold. This boot option
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| /Documentation/arch/s390/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
37 Holds messages from the processing of PCI events, like machine check handling
40 Change the level of logging to be more or less verbose by piping
41 a number between 0 and 6 to /sys/kernel/debug/s390dbf/pci_*/level. For
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
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| /Documentation/sound/hd-audio/ |
| D | realtek-pc-beep.rst | 17 identified below have no discernible effect on my machine, a Dell XPS 13 9350::
20 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
24 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
35 by h and S bits. Does not affect the level of 1Ah exposed to other widgets.
39 by h and S bits. Does not affect the level of 1Ah exposed to other widgets.
43 into 21h (headphone jack on my machine). Mixed signal respects the mute
48 into 14h (internal speaker on my machine). Mixed signal **ignores** the mute
58 +--DIV--+--!DIV--+ {1Ah boost control}
60 +--(b == 0)--+--(b != 0)--+
70 +-----!h-----+-----S-----+
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| /Documentation/devicetree/ |
| D | usage-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
21 machine.
44 ----------
56 In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit
57 and 64-bit support, the decision was made to require DT support on all
61 blob without requiring a real Open Firmware implementation. U-Boot,
66 existing non-DT aware firmware.
71 out of mainline (nios) have some level of DT support.
74 -------------
78 2.1 High Level View
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| /Documentation/mm/ |
| D | hwpoison.rst | 16 High level machine check handler. Handles pages reported by the
25 when that happens another machine check will happen.
41 The code consists of a the high level handler in mm/memory-failure.c,
46 of applications. KVM support requires a recent qemu-kvm release.
49 KVM can inject the machine check into the guest with the proper
109 * madvise(MADV_HWPOISON, ....) (as root) - Poison a page in the
112 * hwpoison-inject module through debugfs ``/sys/kernel/debug/hwpoison/``
114 corrupt-pfn
118 unpoison-pfn
119 Software-unpoison page at PFN echoed into this file. This way
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| /Documentation/crypto/ |
| D | descore-readme.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 ------------------------------------------------------------------------------
15 des - fast & portable DES encryption & decryption.
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
43 3. Plug-compatible replacement for KERBEROS's low-level routines.
46 register-starved machines. My discussions with Richard Outerbridge,
51 up in a parameterized fashion so it can easily be modified by speed-daemon
58 compile on a SPARCStation 1 (cc -O4, gcc -O2):
60 this code (byte-order independent):
62 - 30us per encryption (options: 64k tables, no IP/FP)
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| /Documentation/arch/parisc/ |
| D | debugging.rst | 2 PA-RISC Debugging
5 okay, here are some hints for debugging the lower-level parts of
22 When real-mode code tries to access non-existent memory, you'll get
26 the I/O range); the System Responder address is the address real-mode
31 get translated to a physical address before real-mode code tried to
40 registers interruption handlers read to find out where the machine
41 was interrupted - so if you get an interruption between the instruction
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| /Documentation/scheduler/ |
| D | sched-domains.rst | 6 hierarchy is built from these base domains via the ->parent pointer. ->parent
7 MUST be NULL terminated, and domain structures should be per-CPU as they are
10 Each scheduling domain spans a number of CPUs (stored in the ->span field).
20 which are organised as a circular one way linked list from the ->groups
22 domain's span. The group pointed to by the ->groups pointer MUST contain the CPU
37 balancing workhorse, sched_balance_softirq()->sched_balance_domains(), is then run
42 sched domains our CPU is on, starting from its base domain and going up the ->parent
58 The "base" domain will "span" the first level of the hierarchy. In the case
64 of the SMP domain will span the entire machine, with each group having the
65 cpumask of a node. Or, you could do multi-level NUMA or Opteron, for example,
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| /Documentation/security/ |
| D | sak.rst | 15 providing SAK. One is the ALT-SYSRQ-K sequence. You shouldn't use
25 run level 5, the X server will restart. This is what you want to
28 What key sequence should you use? Well, CTRL-ALT-DEL is used to reboot
29 the machine. CTRL-ALT-BACKSPACE is magical to the X server. We'll
30 choose CTRL-ALT-PAUSE.
42 systems which implement C2 level security. This author does not
57 # ls -l /proc/[0-9]*/fd/* | grep console
58 l-wx------ 1 root root 64 Mar 18 00:46 /proc/579/fd/0 -> /dev/console
63 root 579 0.0 0.1 1088 436 ? S 00:43 0:00 gpm -t ps/2
90 applications to malfunction - test everything well.
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| /Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
9 To meet the whole system security needs and support virtual machine requesting
15 Intel Stratix10 service layer driver, running at privileged exception level
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
32 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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| /Documentation/networking/device_drivers/ethernet/3com/ |
| D | vortex.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 - Andrew Morton
21 - Netdev mailing list <netdev@vger.kernel.org>
22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
35 - 3c597 EISA Fast Demon/Vortex
36 - 3c595 Vortex 100baseTx
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
168 Memory Access at Last Level
207 Power Gate Finite State Machine
225 Transition-Minimized Differential Signaling
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| /Documentation/core-api/ |
| D | entry.rst | 16 exceptions`_, `NMI and NMI-like exceptions`_.
18 Non-instrumentable code - noinstr
19 ---------------------------------
33 .. code-block:: c
37 handle_entry(); // <-- must be 'noinstr' or '__always_inline'
41 handle_context(); // <-- instrumentable code
45 handle_exit(); // <-- must be 'noinstr' or '__always_inline'
51 Invoking non-instrumentable functions from instrumentable context has no
55 All non-instrumentable entry/exit code sections before and after the RCU
59 --------
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-irq | 8 but in a more machine-friendly format. This directory contains
15 Description: The IRQ action chain. A comma-separated list of zero or more
22 Description: Human-readable chip name supplied by the associated device
36 Description: Human-readable flow handler name as defined by the irq chip
44 is a comma-separated list of counters; one per CPU in CPU id
53 Description: The type of the interrupt. Either the string 'level' or 'edge'.
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