Home
last modified time | relevance | path

Searched +full:bits +full:- +full:per +full:- +full:pixel (Results 1 – 25 of 69) sorted by relevance

123

/Documentation/userspace-api/media/v4l/
Dfourcc.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Guidelines for Video4Linux pixel format 4CCs
8 the pixel format, compression and colour space. The interpretation of the
14 ---------
18 - B: raw bayer, uncompressed
19 - b: raw bayer, DPCM compressed
20 - a: A-law compressed
21 - u: u-law compressed
23 2nd character: pixel order
25 - B: BGGR
[all …]
Dpixfmt-cnf4.rst1 .. -*- coding: utf-8; mode: rst -*-
3 .. _V4L2-PIX-FMT-CNF4:
9 Depth sensor confidence information as a 4 bits per pixel packed array
15 confidence information in range 0-15 with 0 indicating that the sensor was
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
21 bits 4-7 to confidence value of depth pixel 2*n+1.
23 **Bit-packed representation.**
25 .. flat-table::
26 :header-rows: 0
27 :stub-columns: 0
[all …]
Dpixfmt-y8i.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Y8I:
10 Interleaved grey-scale image, e.g. from a stereo-pair
16 This is a grey-scale image with a depth of 8 bits per pixel, but with
17 pixels from 2 sources interleaved. Each pixel is stored in a 16-bit
18 word. E.g. the R200 RealSense camera stores pixel from the left sensor
19 in lower and from the right sensor in the higher 8 bits.
27 .. flat-table::
28 :header-rows: 0
29 :stub-columns: 0
[all …]
Dpixfmt-y12i.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-Y12I:
9 Interleaved grey-scale image, e.g. from a stereo-pair
15 This is a grey-scale image with a depth of 12 bits per pixel, but with
16 pixels from 2 sources interleaved and bit-packed. Each pixel is stored
17 in a 24-bit word in the little-endian order. On a little-endian machine
20 .. code-block:: c
26 **Bit-packed representation.**
28 interleaved pixel.
30 .. flat-table::
[all …]
Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
24 bytes. Each of the first 4 bytes contain the 8 high order bits
26 bits of each pixel, in the same order.
[all …]
Dpixfmt-srggb12p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
20 These four pixel formats are packed raw sRGB / Bayer formats with 12
21 bits per colour. Every two consecutive samples are packed into three
22 bytes. Each of the first two bytes contain the 8 high order bits of
[all …]
Dpixfmt-packed-yuv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
19 denotes padding bits.
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
31 order, and on the number of bits for each component. For instance the YUV565
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
[all …]
Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 14
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
[all …]
Dpixfmt-srggb12.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12:
4 .. _v4l2-pix-fmt-sbggr12:
5 .. _v4l2-pix-fmt-sgbrg12:
6 .. _v4l2-pix-fmt-sgrbg12:
17 12-bit Bayer formats expanded to 16 bits
23 These four pixel formats are raw sRGB / Bayer formats with 12 bits per
24 colour. Each colour component is stored in a 16-bit word, with 4 unused
25 high bits filled with zeros. Each n-pixel row contains n/2 green samples
32 Each cell is one byte, the 4 most significant bits in the high bytes are
[all …]
Dpixfmt-srggb10.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10:
4 .. _v4l2-pix-fmt-sbggr10:
5 .. _v4l2-pix-fmt-sgbrg10:
6 .. _v4l2-pix-fmt-sgrbg10:
16 10-bit Bayer formats expanded to 16 bits
22 These four pixel formats are raw sRGB / Bayer formats with 10 bits per
23 sample. Each sample is stored in a 16-bit word, with 6 unused
24 high bits filled with zeros. Each n-pixel row contains n/2 green samples and
31 Each cell is one byte, the 6 most significant bits in the high bytes
[all …]
Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
9 These formats encode each pixel as a triplet of RGB values. They are packed
10 formats, meaning that the RGB values for one pixel are stored consecutively in
11 memory and each pixel consumes an integer number of bytes. When the number of
12 bits required to store a pixel is not aligned to a byte boundary, the data is
13 padded with additional bits to fill the remaining byte.
15 The formats differ by the number of bits per RGB component (typically but not
17 presence of an alpha component or additional padding bits.
19 The usage and value of the alpha bits in formats that support them (named ARGB
[all …]
/Documentation/devicetree/bindings/display/
Dcirrus,clps711x-fb.txt4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
14 - cmap-invert : Invert the color levels (Optional).
17 - lcd-supply: Regulator for LCD supply voltage.
21 compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
[all …]
Datmel,lcdc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
16 input buffer per layer that fetches pixels through the single bus host
17 interface and a look-up table to allow palletized display configurations. The
18 LCDC is programmable on a per layer basis, and supports different LCD
19 resolutions, window sizes, image formats and pixel depths.
[all …]
Dwm,wm8505-fb.txt2 -----------------------------------------------------
5 - compatible : "wm,wm8505-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - bits-per-pixel : bit depth of framebuffer (16 or 32)
10 - display-timings: see display-timing.txt for information
15 compatible = "wm,wm8505-fb";
17 bits-per-pixel = <16>;
19 display-timings {
20 native-mode = <&timing0>;
22 clock-frequency = <0>; /* unused but required */
[all …]
Dvia,vt8500-fb.txt2 -----------------------------------------------------
5 - compatible : "via,vt8500-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - interrupts : framebuffer controller interrupt
8 - bits-per-pixel : bit depth of framebuffer (16 or 32)
11 - display-timings: see display-timing.txt for information
16 compatible = "via,vt8500-fb";
19 bits-per-pixel = <16>;
21 display-timings {
22 native-mode = <&timing0>;
[all …]
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
28 Bits Per Colour/Component
31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
50 raw stream of pixels, clocked at pixel clock
95 Display Stream Compression (Reduce the amount of bits to represent pixel
96 count while at the same pixel clock)
[all …]
/Documentation/fb/
Dapi.rst9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
47 to be aware of the pixel storage format in order to write image data to the
58 - FB_TYPE_PACKED_PIXELS
60 Macropixels are stored contiguously in a single plane. If the number of bits
61 per macropixel is not a multiple of 8, whether macropixels are padded to the
[all …]
Dsa1100fb.rst8 This is a driver for a graphic framebuffer for the SA-1100 LCD
19 controller. The bits per pixel (bpp) value should be 4, 8, 12, or
20 16. LCCR values are display-specific and should be computed as
21 documented in the SA-1100 Developer's Manual, Section 11.7. Dual-panel
34 bpp:<value> Configure for <value> bits per pixel
Dsm501.rst11 Specify bits-per-pixel if not specified by 'mode'
15 "<xres>x<yres>[-<bpp>][@<refresh>]"
Dtridentfb.rst17 The driver supports 8, 16 and 32 bits per pixel depths.
40 video=tridentfb:800x600-16@75,noaccel
69 bpp bits per pixel (8,16 or 32)
70 mode a mode name like 800x600-8@75 as described in
Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
33 Pixel clock in picoseconds
63 4 or 8 pixel monochrome single panel data
72 Double pixel clock. 1=>true, 0=>false
80 pixel clock polarity
87 PXA27x and later processors support overlay1 and overlay2 on-top of the
88 base framebuffer (although under-neath the base is also possible). They
89 support palette and no-palette RGB formats, as well as YUV formats (only
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
[all …]
/Documentation/userspace-api/
Ddma-buf-alloc-exchange.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. Copyright 2021-2023 Collabora Ltd.
5 Exchanging pixel buffers
9 support for sharing pixel-buffer allocations between processes, devices, and
12 approach this sharing for two-dimensional image data.
25 Conceptually a two-dimensional array of pixels. The pixels may be stored
26 in one or more memory buffers. Has width and height in pixels, pixel
30 A span along a single y-axis value, e.g. from co-ordinates (0,100) to
37 A span along a single x-axis value, e.g. from co-ordinates (100,0) to
41 A piece of memory for storing (parts of) pixel data. Has stride and size
[all …]
/Documentation/driver-api/media/
Dtx-rx.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _transmitter-receiver:
5 Pixel data transmitter and receiver drivers
8 V4L2 supports various devices that transmit and receive pixel data. Examples of
10 CSI-2 receiver in an SoC.
13 ---------
17 MIPI CSI-2
20 CSI-2 is a data bus intended for transferring images from cameras to
29 per data line. The parallel bus uses synchronisation and other additional
32 .. _`BT.656`: https://en.wikipedia.org/wiki/ITU-R_BT.656
[all …]
/Documentation/admin-guide/media/
Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
33 | 1 - FPDL3
34 | 2 - GMSL
42 PRODUCT-REVISION-SERIES-SERIAL
55 | 0 - single
[all …]

123