Searched +full:boot +full:- +full:pages (Results 1 – 25 of 89) sorted by relevance
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| /Documentation/devicetree/bindings/mtd/ |
| D | amlogic,meson-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - liang.yang@amlogic.com
18 - amlogic,meson-gxl-nfc
19 - amlogic,meson-axg-nfc
24 reg-names:
26 - const: nfc
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| D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
32 Contains the chip-select IDs.
34 nand-ecc-placement:
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| /Documentation/admin-guide/mm/ |
| D | zswap.rst | 8 Zswap is a lightweight compressed cache for swap pages. It takes pages that are
10 dynamically allocated RAM-based memory pool. zswap basically trades CPU cycles
11 for potentially reduced swap I/O. This trade-off can also result in a
24 drastically reducing life-shortening writes.
26 Zswap evicts pages from compressed cache on an LRU basis to the backing swap
30 Whether Zswap is enabled at the boot time depends on whether
40 When zswap is disabled at runtime it will stop storing pages that are
42 back into memory all of the pages stored in the compressed pool. The
43 pages stored in zswap will remain in the compressed pool until they are
45 pages out of the compressed pool, a swapoff on the swap device(s) will
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| D | hugetlbpage.rst | 2 HugeTLB Pages
13 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
28 persistent hugetlb pages in the kernel's huge page pool. It also displays
30 and surplus huge pages in the pool of huge pages of default size.
46 is the size of the pool of huge pages.
48 is the number of huge pages in the pool that are not yet
51 is short for "reserved," and is the number of huge pages for
53 but no allocation has yet been made. Reserved huge pages
55 huge page from the pool of huge pages at fault time.
57 is short for "surplus," and is the number of huge pages in
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| D | memory-hotplug.rst | 20 - The physical memory available to a machine can be adjusted at runtime, up- or
25 - Replacing hardware, such as DIMMs or whole NUMA nodes, without downtime. One
28 - Reducing energy consumption either by physically unplugging memory modules or
32 used to expose persistent memory, other performance-differentiated memory and
39 ------------------------------
54 ------------------------
71 --------------------------
80 relevant free pages from the page allocator After this phase, the memory is no
94 ------------------
112 --------------
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| D | numa_memory_policy.rst | 10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
38 use "local allocation" described below. However, during boot
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
67 A task policy applies only to pages allocated after the policy is
68 installed. Any pages already faulted in by the task when the task
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| D | transhuge.rst | 11 using huge pages for the backing of virtual memory with huge pages
26 requiring larger clear-page copy-page in page faults which is a
48 Modern kernels support "multi-size THP" (mTHP), which introduces the
50 but smaller than traditional PMD-size (as described above), in
51 increments of a power-of-2 number of pages. mTHP can back anonymous
53 PTE-mapped, but in many cases can still provide similar benefits to
56 prominent because the size of each page isn't as huge as the PMD-sized
66 collapses sequences of basic pages into PMD-sized huge pages.
91 possible to disable hugepages system-wide and to only have them inside
108 -------------------
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| /Documentation/virt/kvm/s390/ |
| D | s390-pv-boot.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 s390 (IBM Z) Boot/IPL of Protected VMs
8 -------
13 Documentation/virt/kvm/s390/s390-pv.rst for details."
15 On IPL (boot) a small plaintext bootloader is started, which provides
29 direct kernel, ...) without the need to change the boot process.
33 -------
46 The new PV load-device-specific-parameters field specifies all data
52 * AES-XTS Tweak prefix
62 After the initial import of the encrypted data, all defined pages will
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 1 * Boot Bus
3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
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| /Documentation/mm/ |
| D | page_owner.rst | 11 and order of pages is stored into certain storage for each page.
12 When we need to know about status of all pages, we can get and analyze
28 allocated base pages, which gives us a quick overview of where the memory
29 is going without the need to screen through all the pages and match the
33 to add "page_owner=on" to your boot cmdline. If the kernel is built
35 boot option, runtime overhead is marginal. If disabled in runtime, it
52 memory system, so, until initialization, many pages can be allocated and
54 pages are investigated and marked as allocated in initialization phase.
57 more accurately. On 2GB memory x86-64 VM box, 13343 early allocated pages
60 un-tracking state.
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| D | physical_memory.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 architecture-independent abstraction to represent the physical memory. This
13 `Non-Uniform Memory Access (NUMA)
14 <https://en.wikipedia.org/wiki/Non-uniform_memory_access>`_.
15 With multi-core and multi-socket machines, memory may be arranged into banks
27 specific code early during boot. Usually, these structures are allocated
42 memory with DMA specific requirements (Documentation/core-api/dma-api.rst),
47 ``CONFIG_ZONE_DMA32`` configuration options. Some 64-bit platforms may need
52 the time. DMA operations can be performed on pages in this zone if the DMA
59 only on some 32-bit architectures and is enabled with ``CONFIG_HIGHMEM``.
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| D | vmemmap_dedup.rst | 2 .. SPDX-License-Identifier: GPL-2.0
14 default, there is a one-to-one mapping from a page frame to its corresponding
17 HugeTLB pages consist of multiple base page size pages and is supported by many
18 architectures. See Documentation/admin-guide/mm/hugetlbpage.rst for more
19 details. On the x86-64 architecture, HugeTLB pages of size 2MB and 1GB are
21 consists of 512 base pages and a 1GB HugeTLB page consists of 262144 base pages.
27 is the compound_head field, and this field is the same for all tail pages.
29 By removing redundant ``struct page`` for HugeTLB pages, memory can be returned
32 Different architectures support different HugeTLB pages. For example, the
34 architectures. Because arm64 supports 4k, 16k, and 64k base pages and
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| D | page_table_check.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 Page table check performs extra verifications at the time when new pages become
27 userfaultfd is the only user of such to sanity check wr-protect bit against
29 corruption in this case immediately, but that will cause read-only data to
35 +-------------------+-------------------+-------------------+------------------+
39 +-------------------+-------------------+-------------------+------------------+
41 +-------------------+-------------------+-------------------+------------------+
43 +-------------------+-------------------+-------------------+------------------+
45 +-------------------+-------------------+-------------------+------------------+
47 +-------------------+-------------------+-------------------+------------------+
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-mm-mempolicy-weighted-interleave | 3 Contact: Linux memory management mailing list <linux-mm@kvack.org>
8 Contact: Linux memory management mailing list <linux-mm@kvack.org>
16 will not cause migrations on already allocated pages.
25 or drivers at boot or during hotplug events.
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| /Documentation/dev-tools/ |
| D | kfence.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Kernel Electric-Fence (KFENCE)
7 Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety
8 error detector. KFENCE detects heap out-of-bounds access, use-after-free, and
9 invalid-free errors.
15 non-production test workloads. One way to quickly achieve a large enough total
19 -----
26 ``kfence.sample_interval`` to non-zero value), configure the kernel with::
38 the kernel boot parameter ``kfence.sample_interval`` in milliseconds. The
46 causes CPU wake-ups when the system is completely idle. This may be undesirable
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| D | kmsan.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 -------------------
27 --------------
32 BUG: KMSAN: uninit-value in test_uninit_kmsan_check_memory+0x1be/0x380 [kmsan_test]
36 kunit_generic_run_threadfn_adapter+0x6d/0xc0 lib/kunit/try-catch.c:28
45 kunit_generic_run_threadfn_adapter+0x6d/0xc0 lib/kunit/try-catch.c:28
53 Bytes 4-7 of 8 are uninitialized
56 CPU: 0 PID: 6731 Comm: kunit_try_catch Tainted: G B E 5.16.0-rc3+ #104
57 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014
71 - in a condition, e.g. ``if (v) { ... }``;
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| /Documentation/arch/x86/ |
| D | tdx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
18 CPU-attested software module called 'the TDX module' runs inside the new
22 TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to
23 provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs
32 TDX boot-time detection
33 -----------------------
36 boot. Below dmesg shows when TDX is enabled by BIOS::
41 ---------------------------------------
59 Besides initializing the TDX module, a per-cpu initialization SEAMCALL
103 ------------------------------------------
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| D | sgx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 * Privileged (ring-0) ENCLS functions orchestrate the construction of the
15 * Unprivileged (ring-3) ENCLU functions allow an application to enter and
37 SGX utilizes an *Enclave Page Cache (EPC)* to store pages that are associated
38 with an enclave. It is contained in a BIOS-reserved region of physical memory.
39 Unlike pages used for regular memory, pages can only be accessed from outside of
49 ------------------
56 Regular EPC pages contain the code and data of an enclave.
59 Thread Control Structure pages define the entry points to an enclave and
63 Version Array pages contain 512 slots, each of which can contain a version
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| D | amd-memory-encryption.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 SME provides the ability to mark individual pages of memory as encrypted using
19 memory. Private memory is encrypted with the guest-specific key, while shared
36 When SEV is enabled, instruction pages and guest page tables are always treated
39 is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware
78 - Supported:
81 - Enabled:
84 - Active:
87 kernel is non-zero).
102 SEV-SNP introduces new features (SEV_FEATURES[1:63]) which can be enabled
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| /Documentation/virt/hyperv/ |
| D | coco.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Hyper-V can create and run Linux guests that are Confidential Computing
9 CoCo VMs on Hyper-V share the generic CoCo VM threat model and security
10 objectives described in Documentation/security/snp-tdx-threat-model.rst. Note
11 that Hyper-V specific code in Linux refers to CoCo VMs as "isolated VMs" or
14 A Linux CoCo VM on Hyper-V requires the cooperation and interaction of the
19 * The hardware runs a version of Windows/Hyper-V with support for CoCo VMs
25 * AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
26 SEV, or SEV-ES encryption, and such encryption is not sufficient for a CoCo
27 VM on Hyper-V.
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| /Documentation/arch/arm64/ |
| D | memory.rst | 12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
23 contains only user (non-global) mappings. The swapper_pg_dir address is
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
30 -----------------------------------------------------------------------
44 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
47 -----------------------------------------------------------------------
61 Translation table lookup with 4KB pages::
63 +--------+--------+--------+--------+--------+--------+--------+--------+
65 +--------+--------+--------+--------+--------+--------+--------+--------+
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| /Documentation/admin-guide/hw-vuln/ |
| D | multihit.rst | 13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
43 into pages of a given size. Page tables translate virtual addresses to physical
56 cause a machine-check error which can result in a system hang or shutdown.
60 ----------------
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| /Documentation/arch/x86/x86_64/ |
| D | boot-options.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 AMD64 Specific Boot Options
39 Do not opt-in to Local MCE delivery. Use legacy method
49 Disable boot machine check logging.
55 Don't overwrite the bios-set CMCI threshold. This boot option
62 Force-enable recoverable machine check code paths
73 Use IO-APIC. Default
76 Don't use the IO-APIC.
85 See Documentation/arch/x86/i386/IO-APIC.rst
91 Don't check the IO-APIC timer. This can work around
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| /Documentation/accounting/ |
| D | delay-accounting.rst | 9 The per-task delay accounting functionality measures
14 c) swapping in pages
18 g) write-protect copy
40 ---------
44 generic data structure to userspace corresponding to per-pid and per-tgid
53 cache, direct compact, write-protect copy, IRQ/SOFTIRQ etc.
60 When a task exits, records containing the per-task statistics
62 task of a thread group, the per-tgid statistics are also sent. More details
70 -----
77 Delay accounting is disabled by default at boot up.
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| /Documentation/admin-guide/sysctl/ |
| D | vm.rst | 13 ------------------------------------------------------------------------------
27 - admin_reserve_kbytes
28 - compact_memory
29 - compaction_proactiveness
30 - compact_unevictable_allowed
31 - dirty_background_bytes
32 - dirty_background_ratio
33 - dirty_bytes
34 - dirty_expire_centisecs
35 - dirty_ratio
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