Searched +full:burst +full:- +full:read (Results 1 – 25 of 33) sorted by relevance
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| /Documentation/devicetree/bindings/dma/ |
| D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
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| D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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| D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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| D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
35 Read parameters:
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-diseqc-send-burst.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 FE_DISEQC_SEND_BURST - Sends a 22KHz tone burst for 2x1 mini DiSEqC satellite selection.
34 This ioctl is used to set the generation of a 22kHz tone burst for mini
36 read/write permissions.
39 `Digital Satellite Equipment Control (DiSEqC) - Simple "ToneBurst" Detection Circuit specification.…
46 On error -1 is returned, and the ``errno`` variable is set
50 :ref:`Generic Error Codes <gen-errors>` chapter.
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| D | frontend_fcalls.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
14 fe-get-info
15 fe-read-status
16 fe-get-property
17 fe-diseqc-reset-overload
18 fe-diseqc-send-master-cmd
19 fe-diseqc-recv-slave-reply
20 fe-diseqc-send-burst
21 fe-set-tone
22 fe-set-voltage
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| /Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| /Documentation/scheduler/ |
| D | sched-bwc.rst | 7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
25 Burst feature
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
40 The burst feature observes that a workload doesn't always executes the full
62 The interferenece when using burst is valued by the possibilities for
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
69 ----------
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| /Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
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| /Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 * Asynchronous, synchronous, and page mode burst NOR flash devices
14 * Pseudo-SRAM devices
74 3. read async muxed
85 4. read async non-muxed
96 5. read sync muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
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| /Documentation/driver-api/dmaengine/ |
| D | provider.rst | 20 DMA-eligible devices to the controller itself. Whenever the device
42 using a parameter called the burst size, that defines how many single
44 transfer into smaller sub-transfers.
49 non-contiguous buffers to a contiguous buffer, which is called
50 scatter-gather.
53 scatter-gather. So we're left with two cases here: either we have a
56 that implements in hardware scatter-gather.
72 not and the three parameters we saw earlier: the burst size, the
79 These were just the general memory-to-memory (also called mem2mem) or
80 memory-to-device (mem2dev) kind of transfers. Most devices often
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| D | client.rst | 8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
40 .. code-block:: c
56 DMA direction, DMA addresses, bus widths, DMA burst lengths etc
66 .. code-block:: c
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| /Documentation/dev-tools/ |
| D | kfence.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Kernel Electric-Fence (KFENCE)
7 Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety
8 error detector. KFENCE detects heap out-of-bounds access, use-after-free, and
9 invalid-free errors.
15 non-production test workloads. One way to quickly achieve a large enough total
19 -----
26 ``kfence.sample_interval`` to non-zero value), configure the kernel with::
46 causes CPU wake-ups when the system is completely idle. This may be undesirable
47 on power-constrained systems. The boot parameter ``kfence.deferrable=1``
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| /Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /Documentation/scsi/ |
| D | ncr53c8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
51 10.2.11 Burst max
64 10.4 PCI configuration fix-up boot option
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
97 - Gerard Roudier <groudier@free.fr>
101 - Wolfgang Stanglmeier <wolf@cologne.de>
102 - Stefan Esser <se@mi.Uni-Koeln.de>
106 - ncr53c8xx generic driver that supports all the SYM53C8XX family including
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| D | sym53c8xx_2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SYM-2 driver
11 95170 DEUIL LA BARRE - FRANCE
15 2004-10-09
42 10.2.2 Burst max
67 This driver supports the whole SYM53C8XX family of PCI-SCSI controllers.
68 It also support the subset of LSI53C10XX PCI-SCSI controllers that are based
72 with the FreeBSD SYM-2 driver. The 'glue' that allows this driver to work
81 - Wolfgang Stanglmeier <wolf@cologne.de>
82 - Stefan Esser <se@mi.Uni-Koeln.de>
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| D | ChangeLog.ncr53c8xx | 1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version ncr53c8xx-3.4.3b
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
7 Mon Feb 12 22:30 2001 Gerard Roudier (groudier@club-internet.fr)
8 * version ncr53c8xx-3.4.3
9 - Call pci_enable_device() as AC wants this to be done.
10 - Get both the BAR cookies actual and PCI BAR values.
12 - Merge changes for linux-2.4 that declare the host template
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| /Documentation/sound/designs/ |
| D | control-names.rst | 8 ---------------
68 Headset Mic mic part of combined headset jack - 4-pin
70 Headphone Mic mic part of either/or - 3-pin headphone or mic
79 Analog Loopback D/A -> A/D loopback
80 Digital Loopback playback -> capture loopback -
98 -----------------------
106 Tone Control - Switch
107 Tone Control - Bass
108 Tone Control - Treble
109 3D Control - Switch
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| /Documentation/driver-api/usb/ |
| D | error-codes.rst | 1 .. _usb-error-codes:
6 :Revised: 2004-Oct-21
20 Non-USB-specific:
26 ``-ENOMEM`` no memory for allocation of internal structures
29 USB-specific:
32 ``-EBUSY`` The URB is already active.
34 ``-ENODEV`` specified USB-device or bus doesn't exist
36 ``-ENOENT`` specified interface or endpoint does not exist or
39 ``-ENXIO`` host controller driver does not support queuing of
42 ``-EINVAL`` a) Invalid transfer type specified (or not supported)
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| /Documentation/admin-guide/ |
| D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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| /Documentation/networking/device_drivers/ethernet/cirrus/ |
| D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
85 or loaded at run-time as a device driver module.
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-camera.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _camera-controls:
13 .. _camera-control-id:
23 .. _v4l2-exposure-auto-type:
28 enum v4l2_exposure_auto_type -
37 .. flat-table::
38 :header-rows: 0
39 :stub-columns: 0
41 * - ``V4L2_EXPOSURE_AUTO``
42 - Automatic exposure time, automatic iris aperture.
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| /Documentation/arch/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
30 without the ability to generate convenient burst transfer ensuring the best
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
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