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/Documentation/devicetree/bindings/sound/
Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
[all …]
Drealtek,rt5682s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Derek Fang <derek.fang@realtek.com>
13 Rt5682s(ALC5682I-VS) is a rt5682i variant which supports I2C only.
16 - $ref: dai-common.yaml#
30 realtek,dmic1-data-pin:
33 - 0 # dmic1 data is not used
34 - 1 # using GPIO2 pin as dmic1 data pin
35 - 2 # using GPIO5 pin as dmic1 data pin
[all …]
Deverest,es8326.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Yang <yangxiaohua@everest-semi.com>
21 - description: clock for master clock (MCLK)
23 clock-names:
25 - const: mclk
27 "#sound-dai-cells":
30 everest,jack-pol:
40 everest,mic1-src:
[all …]
Dfsl,micfil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 The MICFIL digital interface provides a 16-bit or 24-bit audio signal
19 - items:
20 - enum:
21 - fsl,imx95-micfil
22 - const: fsl,imx93-micfil
24 - enum:
[all …]
Drt5668.txt7 - compatible : "realtek,rt5668b"
9 - reg : The I2C address of the device.
13 - interrupts : The CODEC's interrupt output.
15 - realtek,dmic1-data-pin
20 - realtek,dmic1-clk-pin
24 - realtek,jd-src
26 1: using JD1 as JD source
28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
43 interrupt-parent = <&gpio>;
45 realtek,ldo1-en-gpios =
[all …]
Dnvidia,tegra-audio-wm8753.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8753.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm8753(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm8753
22 nvidia,audio-routing:
[all …]
Dnvidia,tegra-audio-wm9712.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm9712.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm9712([-_][a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm9712
22 nvidia,audio-routing:
[all …]
Dnvidia,tegra-audio-alc5632.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-alc5632.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-alc5632(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-alc5632
22 nvidia,audio-routing:
[all …]
Dnvidia,tegra-audio-rt5640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5640.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt56(39|40)(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5640
22 nvidia,audio-routing:
[all …]
Drt5682.txt7 - compatible : "realtek,rt5682" or "realtek,rt5682i"
9 - reg : The I2C address of the device.
11 - AVDD-supply: phandle to the regulator supplying analog power through the
14 - MICVDD-supply: phandle to the regulator supplying power for the microphone
17 - VBAT-supply: phandle to the regulator supplying battery power through the
20 - DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
23 - LDO1-IN-supply: phandle to the regulator supplying power to the digital core
28 - interrupts : The CODEC's interrupt output.
30 - realtek,dmic1-data-pin
35 - realtek,dmic1-clk-pin
[all …]
Dnvidia,tegra-audio-rt5677.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5677.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt5677(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5677
22 nvidia,audio-routing:
[all …]
Dnvidia,tegra-audio-wm8903.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8903.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - items:
20 - pattern: '^[a-z0-9]+,tegra-audio-wm8903(-[a-z0-9]+)+$'
21 - const: nvidia,tegra-audio-wm8903
[all …]
Dmt8195-mt6359.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-mt6359.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8195_mt6359_rt1019_rt5682
22 - mediatek,mt8195_mt6359_rt1011_rt5682
23 - mediatek,mt8195_mt6359_max98390_rt5682
29 audio-routing:
[all …]
/Documentation/devicetree/bindings/timer/
Dcsky,gx6605s-timer.txt6 contain clk event and clk source.
16 - compatible
19 Definition: must be "csky,gx6605s-timer"
20 - reg
24 - clocks
27 Definition: must be input clk node
28 - interrupt
34 ---------
37 compatible = "csky,gx6605s-timer";
41 interrupt-parent = <&intc>;
/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
[all …]
Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
27 - description: Sleep clock source
[all …]
Dzynq-7000.txt3 The Zynq EPP has several different clk providers, each with there own bindings.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
20 - clock-output-names : List of strings used to name the clock outputs. Shall be
24 - clocks : as described in the clock bindings
25 - clock-names : as described in the clock bindings
26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
32 The following strings are optional parameters to the 'clock-names' property in
[all …]
/Documentation/devicetree/bindings/display/imx/
Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
15 The DCSS (display controller sub system) is used to source up to three
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
[all …]
/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/Documentation/devicetree/bindings/phy/
Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/Documentation/devicetree/bindings/mfd/
Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
27 System controller Advanced Power Bus (APB) interface clock source.
29 clock-names:
[all …]
/Documentation/devicetree/bindings/net/can/
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
22 - fsl,imx8qm-flexcan
[all …]
/Documentation/devicetree/bindings/watchdog/
Dmicrochip,pic32-wdt.txt7 - compatible: must be "microchip,pic32mzda-wdt".
8 - reg: physical base address of the controller and length of memory mapped
10 - clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
15 compatible = "microchip,pic32mzda-wdt";
Dmicrochip,pic32-dmt.txt4 malfunction. It is a free-running instruction fetch timer, which is clocked
8 - compatible: must be "microchip,pic32mzda-dmt".
9 - reg: physical base address of the controller and length of memory mapped
11 - clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
16 compatible = "microchip,pic32mzda-dmt";

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