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/Documentation/devicetree/bindings/clock/
Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 Preferred name is 'clock-<freq>' with <freq> being the output
18 frequency as defined in the 'clock-frequency' property.
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/Documentation/hwmon/
Dshtc1.rst41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
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Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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Dlm63.rst45 -----------
53 - No low limit for local temperature.
54 - No critical limit for local temperature.
55 - Critical limit for remote temperature can be changed only once. We
56 will consider that the critical limit is read-only.
67 store the value in an 8-bit register and have a selectable clock divider
68 to make sure that the result will fit in the register, the LM63 uses 16-bit
93 The LM96163 is an enhanced version of LM63 with improved temperature accuracy
Dit87.rst174 - Christophe Gauthron
175 - Jean Delvare <jdelvare@suse.de>
179 -----------------
192 misconfigured by BIOS - PWM values would be inverted. This option tries
209 Provided since there are reports that system-wide acpi_enfore_resources=lax
217 -------------------
219 All the chips supported by this driver are LPC Super-I/O chips, accessed
220 through the LPC bus (ISA-like I/O ports). The IT8712F additionally has an
228 -----------
247 is stored in the Super-I/O configuration space. Due to technical limitations,
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Dw83781d.rst10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
34 Addresses scanned: I2C 0x28 - 0x2f
42 - Frodo Looijaard <frodol@dds.nl>,
43 - Philip Edelbrock <phil@netroedge.com>,
44 - Mark Studebaker <mdsxyz123@yahoo.com>
47 -----------------
67 -----------
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/Documentation/timers/
Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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/Documentation/devicetree/bindings/mtd/
Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
11 Hz, to make them independent of actual clock speed and to provide for good
12 accuracy:)
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
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/Documentation/sound/designs/
Dtimestamping.rst7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
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/Documentation/devicetree/bindings/iio/adc/
Dti,adc12138.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADC12138 and similar self-calibrating ADCs
10 - Akinobu Mita <akinobu.mita@gmail.com>
19 - ti,adc12130
20 - ti,adc12132
21 - ti,adc12138
32 description: Conversion clock input.
34 vref-p-supply:
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Drenesas,rzg2l-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
16 stored in a 32-bit data register corresponding to each channel.
21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
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/Documentation/devicetree/bindings/iio/pressure/
Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
23 pressure-triplet (directly extracted from the part number) or in case it's
27 by the sensor. pmin-pascal and pmax-pascal corespond to the minimum and
30 Please note that in case of an SPI-based sensor, the clock signal should not
34 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
35 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
38 - Petre Rodan <petre.rodan@subdimension.ro>
47 honeywell,transfer-function:
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/Documentation/core-api/
Dtimekeeping.rst10 ------------------------------
13 that return time for different clock references:
56 clocksource without (NTP) adjustments for clock drift. This is
60 -----------------------------------------
92 Return a coarse-grained version of the time as a scalar
93 time64_t. This avoids accessing the clock hardware and rounds
98 -------------------------
117 These are quicker than the non-coarse versions, but less accurate,
125 in a fast path and one still expects better than second accuracy,
127 Skipping the hardware clock access saves around 100 CPU cycles
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/Documentation/driver-api/pm/
Dcpuidle.rst1 .. SPDX-License-Identifier: GPL-2.0
89 code, and that causes the kernel to run the architecture-specific
91 until the ``->enable()`` governor callback is invoked for that CPU
103 It is expected to reverse any changes made by the ``->enable()``
142 Called to allow the governor to evaluate the accuracy of the idle state
143 selection made by the ``->select()`` callback (when it was invoked last
144 time) and possibly use the result of that to improve the accuracy of
152 :c:func:`cpuidle_governor_latency_req()`. Then, the governor's ``->select()``
217 The analogous ``->enter_s2idle()`` callback in struct cpuidle_state is used
218 only for implementing the suspend-to-idle system-wide power management feature.
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/Documentation/ABI/testing/
Dsysfs-class-hwmon16 The contents of the label are free-form.
135 this voltage channel is being used for, and user-space
137 user-space.
145 When disabled the sensor read will return -ENODATA.
147 - 1: Enable
148 - 0: Disable
156 - 1: Failed
157 - 0: Ok
234 Note that this is actually an internal clock divisor, which
262 Only makes sense if the chip supports closed-loop fan speed
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/Documentation/RCU/Design/Memory-Ordering/
DTree-RCU-Memory-Ordering.rst2 A Tour Through TREE_RCU's Grace-Period Memory Ordering
13 grace-period memory ordering guarantee is provided.
18 RCU grace periods provide extremely strong memory-ordering guarantees
19 for non-idle non-offline code.
22 period that are within RCU read-side critical sections.
25 of that grace period that are within RCU read-side critical sections.
27 Note well that RCU-sched read-side critical sections include any region
30 an extremely small region of preemption-disabled code, one can think of
37 a linked RCU-protected data structure, and phase two frees that element.
39 phase-one update (in the common case, removal) must not witness state
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