Searched +full:clock +full:- +full:controller (Results 1 – 25 of 1044) sorted by relevance
12345678910>>...42
| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,mt8195-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
14 PLLs -->
15 dividers -->
17 -->
[all …]
|
| D | mediatek,mt8192-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
[all …]
|
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
|
| D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
|
| D | marvell,pxa1928.txt | 1 * Marvell PXA1928 Clock Controllers
3 The PXA1928 clock subsystem generates and supplies clock to various
4 controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
9 - compatible: should be one of the following.
10 - "marvell,pxa1928-apmu" - APMU controller compatible
11 - "marvell,pxa1928-mpmu" - MPMU controller compatible
12 - "marvell,pxa1928-apbc" - APBC controller compatible
13 - reg: physical base address of the clock controller and length of memory mapped
15 - #clock-cells: should be 1.
16 - #reset-cells: should be 1.
[all …]
|
| D | rockchip,rk3328-cru.txt | 1 * Rockchip RK3328 Clock and Reset Unit
3 The RK3328 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume. All available clocks are defined as
[all …]
|
| D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI clock controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| D | samsung,exynos4412-isp-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4412 SoC ISP clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
[all …]
|
| D | ti-clkctrl.txt | 1 Texas Instruments clkctrl clock binding
3 Texas Instruments SoCs can have a clkctrl clock controller for each
4 interconnect target module. The clkctrl clock controller manages functional
5 and interface clocks for each module. Each clkctrl controller can also
7 or more clock muxes. There is a clkctrl clock controller typically for each
10 The clock consumers can specify the index of the clkctrl clock using
13 optional clock.
15 For more information, please see the Linux clock framework binding at
16 Documentation/devicetree/bindings/clock/clock-bindings.txt.
19 - compatible : shall be "ti,clkctrl" or a clock domain specific name:
[all …]
|
| D | hi3670-clock.txt | 1 * Hisilicon Hi3670 Clock Controller
3 The Hi3670 clock controller generates and supplies clock to various
8 - compatible: the compatible should be one of the following strings to
9 indicate the clock controller functionality.
11 - "hisilicon,hi3670-crgctrl"
12 - "hisilicon,hi3670-pctrl"
13 - "hisilicon,hi3670-pmuctrl"
14 - "hisilicon,hi3670-sctrl"
15 - "hisilicon,hi3670-iomcu"
16 - "hisilicon,hi3670-media1-crg"
[all …]
|
| D | intel,easic-n5x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel SoCFPGA eASIC N5X platform clock controller
10 - Dinh Nguyen <dinguyen@kernel.org>
13 The Intel eASIC N5X Clock controller is an integrated clock controller, which
18 const: intel,easic-n5x-clkmgr
20 '#clock-cells':
30 - compatible
[all …]
|
| D | intel,agilex.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel SoCFPGA Agilex platform clock controller
10 - Dinh Nguyen <dinguyen@kernel.org>
13 The Intel Agilex Clock controller is an integrated clock controller, which
18 const: intel,agilex-clkmgr
20 '#clock-cells':
30 - compatible
[all …]
|
| D | hi3660-clock.txt | 1 * Hisilicon Hi3660 Clock Controller
3 The Hi3660 clock controller generates and supplies clock to various
8 - compatible: the compatible should be one of the following strings to
9 indicate the clock controller functionality.
11 - "hisilicon,hi3660-crgctrl"
12 - "hisilicon,hi3660-pctrl"
13 - "hisilicon,hi3660-pmuctrl"
14 - "hisilicon,hi3660-sctrl"
15 - "hisilicon,hi3660-iomcu"
16 - "hisilicon,hi3660-stub-clk"
[all …]
|
| D | milbeaut-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Milbeaut SoCs Clock Controller
10 - Taichi Sugaya <sugaya.taichi@socionext.com>
13 Milbeaut SoCs Clock controller is an integrated clock controller, which
16 This binding uses common clock bindings
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - socionext,milbeaut-m10v-ccu
[all …]
|
| D | amlogic,meson8b-clkc.txt | 1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
4 supplies clock to various controllers within the SoC.
8 - compatible: must be one of:
9 - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
[all …]
|
| D | vf610-clock.txt | 1 * Clock bindings for Freescale Vybrid VF610 SOC
4 - compatible: Should be "fsl,vf610-ccm"
5 - reg: Address and length of the register set
6 - #clock-cells: Should be <1>
9 - clocks: list of clock identifiers which are external input clocks to the
10 given clock controller. Please refer the next section to find
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are external input clocks to the
13 given clock controller.
15 Input clocks for top clock controller:
[all …]
|
| D | microchip,lan966x-gck.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN966X Generic Clock Controller
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
14 ddr_clk and sys_clk. This clock controller generates and supplies
15 clock to various peripherals within the SoC.
19 const: microchip,lan966x-gck
[all …]
|
| D | microchip,pic32.txt | 1 Microchip PIC32 Clock Controller Binding
2 ----------------------------------------
3 Microchip clock controller is consists of few oscillators, PLL, multiplexer
6 This binding uses common clock bindings.
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
19 rootclk: clock-controller@1f801200 {
[all …]
|
| D | bitmain,bm1880-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Bitmain BM1880 Clock Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Bitmain BM1880 clock controller generates and supplies clock to
16 This binding uses common clock bindings
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21 const: bitmain,bm1880-clk
[all …]
|
| D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
14 reads required input clock frequencies from the devicetree and acts as clock
15 provider for all clock consumers of PS clocks.
20 - enum:
[all …]
|
| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
34 * PCLK: Pixel Clock
35 * SYMCLK: Symbol Clock
36 * SOCCLK: GPU Engine Clock
37 * DISPCLK: Display Clock
38 * DPPCLK: DPP Clock
39 * DCFCLK: Display Controller Fabric Clock
40 * REFCLK: Real Time Reference Clock
42 * FCLK: Fabric Clock
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
[all …]
|
| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
18 Hisilicon system controller, but some same registers located at different
[all …]
|
| /Documentation/devicetree/bindings/usb/ |
| D | hisilicon,hi3798mv200-dwc3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Hi3798MV200 DWC3 USB SoC controller
10 - Yang Xiwen <forbidden405@foxmail.com>
14 const: hisilicon,hi3798mv200-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description: Controller bus clock
[all …]
|
| /Documentation/devicetree/bindings/soc/amlogic/ |
| D | amlogic,meson-gx-hhi-sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - enum:
16 - amlogic,meson-gx-hhi-sysctrl
17 - amlogic,meson-gx-ao-sysctrl
18 - amlogic,meson-axg-hhi-sysctrl
19 - amlogic,meson-axg-ao-sysctrl
[all …]
|
12345678910>>...42