Searched +full:clock +full:- +full:master (Results 1 – 25 of 230) sorted by relevance
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| /Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
14 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to
25 as BCLK). This clock is used to drive the digital audio data across the link
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-soundwire-master | 1 What: /sys/bus/soundwire/devices/sdw-master-<N>/revision
2 /sys/bus/soundwire/devices/sdw-master-<N>/clk_stop_modes
3 /sys/bus/soundwire/devices/sdw-master-<N>/clk_freq
4 /sys/bus/soundwire/devices/sdw-master-<N>/clk_gears
5 /sys/bus/soundwire/devices/sdw-master-<N>/default_col
6 /sys/bus/soundwire/devices/sdw-master-<N>/default_frame_rate
7 /sys/bus/soundwire/devices/sdw-master-<N>/default_row
8 /sys/bus/soundwire/devices/sdw-master-<N>/dynamic_shape
9 /sys/bus/soundwire/devices/sdw-master-<N>/err_threshold
10 /sys/bus/soundwire/devices/sdw-master-<N>/max_clk_freq
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| /Documentation/devicetree/bindings/sound/ |
| D | fsl,ssi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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| D | mediatek,mt2701-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Eugen Hristev <eugen.hristev@collabora.com>
18 - mediatek,mt2701-audio
19 - mediatek,mt7622-audio
23 - description: AFE interrupt
24 - description: ASYS interrupt
26 interrupt-names:
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| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| D | mikroe,mikroe-proto.txt | 1 Mikroe-PROTO audio board
4 - compatible: "mikroe,mikroe-proto"
5 - dai-format: Must be "i2s".
6 - i2s-controller: The phandle of the I2S controller.
7 - audio-codec: The phandle of the WM8731 audio codec.
9 - model: The user-visible name of this sound complex.
10 - bitclock-master: Indicates dai-link bit clock master; for details see simple-card.txt (1).
11 - frame-master: Indicates dai-link frame master; for details see simple-card.txt (1).
13 (1) : There must be the same master for both bit and frame clocks.
17 compatible = "mikroe,mikroe-proto";
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| D | amlogic,aiu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
13 - $ref: dai-common.yaml#
17 pattern: "^audio-controller@.*"
19 "#sound-dai-cells":
24 - enum:
25 - amlogic,aiu-gxbb
26 - amlogic,aiu-gxl
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| /Documentation/devicetree/bindings/ata/ |
| D | cortina,gemini-sata-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
31 - const: sata1
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| /Documentation/devicetree/bindings/clock/ |
| D | nxp,imx95-display-master-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX95 Display Master Block Control
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
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| D | brcm,kona-ccu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family clock control units (CCU)
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 Broadcom "Kona" style clock control unit (CCU) is a clock provider that
16 manages a set of clock signals.
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| /Documentation/devicetree/bindings/i3c/ |
| D | silvaco,i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silvaco I3C master
10 - Conor Culhane <conor.culhane@silvaco.com>
13 - $ref: i3c.yaml#
17 const: silvaco,i3c-master-v1
27 - description: system clock
28 - description: bus clock
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| D | snps,dw-i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i3c/snps,dw-i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare I3C master block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - $ref: i3c.yaml#
17 const: snps,dw-i3c-master-1.00a
25 - description: Core clock
26 - description: APB clock
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| D | cdns,i3c-master.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i3c/cdns,i3c-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence I3C master block
10 - Boris Brezillon <bbrezillon@kernel.org>
13 - $ref: i3c.yaml#
17 const: cdns,i3c-master
25 clock-names:
27 - const: pclk
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi-master-gpio.txt | 1 Device-tree bindings for gpio-based FSI master driver
2 -----------------------------------------------------
5 - compatible = "fsi-master-gpio";
6 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
7 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
10 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
11 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
12 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
14 - no-gpio-delays; : Don't add extra delays between GPIO
21 fsi-master {
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| D | fsi-master-ast-cf.txt | 1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
2 ------------------------------------------------------------------------
5 - compatible =
6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
10 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
11 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
12 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
13 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
14 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
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| D | aspeed,ast2600-fsi-master.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed FSI master
10 - Eddie James <eajames@linux.ibm.com>
14 clock and have a separate interrupt line and output pins.
19 - aspeed,ast2600-fsi-master
20 - aspeed,ast2700-fsi-master
25 cfam-reset-gpios:
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| /Documentation/driver-api/soundwire/ |
| D | summary.rst | 10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
15 commands over a single two-pin interface.
17 (2) Lower clock frequency, and hence lower power consumption, by use of DDR
20 (3) Clock scaling and optional multiple data lanes to give wide flexibility
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
26 interfaces share the common Bus containing data and clock line. Each of the
35 Below figure shows an example of connectivity between a SoundWire Master and
38 +---------------+ +---------------+
39 | | Clock Signal | |
40 | Master |-------+-------------------------------| Slave |
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| /Documentation/devicetree/bindings/spi/ |
| D | icpdas-lp8841-spi-rtc.txt | 1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | max2175.txt | 2 -----------------------------------------
4 The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with
5 RF to Bits® front-end designed for software-defined radio solutions.
8 --------------------
9 - compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
10 - clocks: clock specifier.
11 - port: child port node corresponding to the I2S output, in accordance with
13 Documentation/devicetree/bindings/media/video-interfaces.txt. The port
17 --------------------
18 - maxim,master : phandle to the master tuner if it is a slave. This
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | synopsys,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
36 - description: The bus clock for either AHB and APB
37 - description: The internal register configuration clock
40 clock-names:
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| /Documentation/i2c/ |
| D | gpio-fault-injection.rst | 5 The GPIO based I2C bus master driver can be configured to provide fault
7 which is driven by the I2C bus master driver under test. The GPIO fault
9 master driver should handle gracefully.
12 'i2c-fault-injector' subdirectory in the Kernel debugfs filesystem, usually
15 injection. They will be described now along with their intended use-cases.
21 -----
26 because the bus master under test will not be able to clock. It should detect
31 -----
36 master under test should detect this condition and trigger a bus recovery (see
52 in a bus master driver, make sure you checked your hardware setup for such
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| /Documentation/devicetree/bindings/dma/ |
| D | arm-pl08x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: dma-controller.yaml#
22 - arm,pl080
23 - arm,pl081
25 - compatible
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
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| /Documentation/devicetree/bindings/rtc/ |
| D | maxim-ds1302.txt | 1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
6 Master output is set on low clock and sensed by the RTC on the rising
7 edge. Master input is set by the RTC on the trailing edge and is sensed
8 by the master on low clock.
12 - compatible : Should be "maxim,ds1302"
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
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