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/Documentation/devicetree/bindings/mmc/
Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
[all …]
Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
31 bus interface unit clock and the card interface unit clock.
33 clock-names:
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Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <heiko@sntech.de>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
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Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
[all …]
/Documentation/devicetree/bindings/watchdog/
Drealtek,otto-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
14 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
[all …]
Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
25 - enum:
26 - starfive,jh7100-wdt
[all …]
/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
[all …]
Dcirrus,cs2000-cp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
14 utilizes a programmable phase lock loop.
21 - cirrus,cs2000-cp
25 Common clock binding for CLK_IN, XTI/REF_CLK
[all …]
/Documentation/netlink/specs/
Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
41 -
[all …]
/Documentation/devicetree/bindings/net/
Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
/Documentation/driver-api/
Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
11 signal of a device with an external clock signal. Effectively enabling
12 device to run on the same clock signal beat as provided on a PLL input.
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
15 addition to plain PLL behavior incorporates a digital phase detector
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
[all …]
/Documentation/devicetree/bindings/iio/dac/
Dadi,ad5755.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
/Documentation/devicetree/bindings/iio/frequency/
Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
[all …]
/Documentation/devicetree/bindings/timer/
Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
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/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
34 description: Continuous clock enable (first bank must be configured
40 st,fmc2-ebi-cs-mux-enable:
[all …]
/Documentation/devicetree/bindings/rtc/
Depson,rx6110.txt1 Epson RX6110 Real Time Clock
8 --------
11 - compatible: should be: "epson,rx6110"
12 - reg : the I2C address of the device for I2C
22 --------
25 - compatible: should be: "epson,rx6110"
26 - reg: chip select number
27 - spi-cs-high: RX6110 needs chipselect high
28 - spi-cpha: RX6110 works with SPI shifted clock phase
29 - spi-cpol: RX6110 works with SPI inverse clock polarity
[all …]
/Documentation/ABI/testing/
Dsysfs-bus-iio-frequency-ad95238 Contact: linux-iio@vger.kernel.org
12 '1' means that the clock in question is present.
14 '0' means that the clock is missing.
18 Contact: linux-iio@vger.kernel.org
25 Contact: linux-iio@vger.kernel.org
27 Writing '1' triggers the clock distribution synchronization
29 with their predefined phase offsets (out_altvoltageY_phase).
Dsysfs-timecard18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
83 for internal disciplining of the atomic clock.
89 for internal disciplining of the atomic clock.
[all …]
/Documentation/devicetree/bindings/clock/ti/
Dapll.txt1 Binding for Texas Instruments APLL clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
6 loop logic for multiplying the input clock to a desired output
7 clock. This clock also typically supports different operation
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
[all …]
/Documentation/scsi/
DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
[all …]
/Documentation/driver-api/pm/
Ddevices.rst1 .. SPDX-License-Identifier: GPL-2.0
10 :Copyright: |copy| 2010-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
18 management (PM) code is also driver-specific. Most drivers will do very
22 This writeup gives an overview of how drivers interact with system-wide
25 background for the domain-specific work you'd do with any specific driver.
31 Drivers will use one or both of these models to put devices into low-power
36 Drivers can enter low-power states as part of entering system-wide
37 low-power states like "suspend" (also known as "suspend-to-RAM"), or
39 "suspend-to-disk").
42 by implementing various role-specific suspend and resume methods to
[all …]
/Documentation/devicetree/bindings/bus/
Dmoxtet.txt4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
14 ../spi/spi-bus.txt.
17 - reg : Should be position on the Moxtet bus (how many Moxtet
[all …]
/Documentation/devicetree/bindings/phy/
Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
16 transmit clock is transmitted in parallel with each group of
18 clock, 56/80 bits of input data are sampled and transmitted
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
[all …]
/Documentation/devicetree/bindings/display/
Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]
/Documentation/hwmon/
Dnsa320.rst22 Adam Baker <linux@baker-net.org.uk>
25 -----------
30 lines which are used to provide chip select, clock and data lines. The
40 sysfs-Interface
41 ---------------
49 -----
53 the first clock pulse is reduced from 100 ms to just under 10ms then the chip
54 will not produce any output. If the duration of either phase of the clock

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