Searched +full:controller +full:- +full:data (Results 1 – 25 of 826) sorted by relevance
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-ep9301.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 16 MSIs may be distinguished in part through the use of sideband data accompanying
17 writes. In the case of PCI devices, this sideband data may be derived from the
19 controllers it can address, and the sideband data that will be associated with
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
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| /Documentation/wmi/devices/ |
| D | msi-wmi-platform.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 MSI WMI Platform Features driver (msi-wmi-platform)
11 by the embedded controller, with the ACPI firmware exposing a standard ACPI WMI interface on top
12 of the embedded controller interface.
18 data using the `bmfdec <https://github.com/pali/bmfdec>`_ utility:
24 guid("{ABBC0F60-8EA1-11d1-00A0-C90629100000}")]
26 [WmiDataId(1), read, write, Description("16 bytes of data")] uint8 Bytes[16];
31 guid("{ABBC0F63-8EA1-11d1-00A0-C90629100000}")]
33 [WmiDataId(1), read, write, Description("32 bytes of data")] uint8 Bytes[32];
38 guid("{ABBC0F6E-8EA1-11d1-00A0-C90629100000}")]
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 1 Memory mapped Bosch CC770 and Intel AN82527 CAN controller
3 Note: The CC770 is a CAN controller from Bosch, which is 100%
8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
12 to map the registers of the controller. The size is usually 0x80.
14 - interrupts : property with a value describing the interrupt source
15 (number and sensitivity) required for the controller.
19 - bosch,external-clock-frequency : frequency of the external oscillator
21 controller is half of that value. If not specified, a default
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
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| /Documentation/devicetree/bindings/media/ |
| D | microchip,csi2dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip CSI2 Demux Controller (CSI2DC)
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
15 CSI2DC is a hardware block that receives incoming data from either from an
17 It filters IDI packets based on their data type and virtual channel
20 controller.
22 CSI2DC can act a simple bypass bridge if the incoming data is coming from
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| /Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
39 * DCFCLK: Display Controller Fabric Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
86 Display Data Channel
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
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| /Documentation/mhi/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 MHI Controller
11 --------------
13 MHI controller driver manages the interaction with the MHI client devices
16 It is however not involved in the actual data transfer as the data transfer
17 is taken care by the physical bus such as PCIe. Each controller driver exposes
20 Below are the roles of the MHI controller driver:
30 ----------
33 for bi-directional communication. Once MHI is in powered on state, the MHI
35 by the controller. There can be a single MHI device for each channel or for a
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| /Documentation/devicetree/bindings/display/ |
| D | solomon,ssd-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/solomon,ssd-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Martinez Canillas <javierm@redhat.com>
16 reset-gpios:
20 dc-gpios:
22 GPIO connected to the controller's D/C# (Data/Command) pin,
23 that is needed for 4-wire SPI to tell the controller if the
24 data sent is for a command register or the display data RAM
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| D | sm501fb.txt | 3 The SM SM501 is a LCD controller, with proper hardware, it can also
7 - compatible : should be "smi,sm501".
8 - reg : contain two entries:
9 - First entry: System Configuration register
10 - Second entry: IO space (Display Controller register)
11 - interrupts : SMI interrupt to the cpu should be described here.
14 - mode : select a video mode:
15 <xres>x<yres>[-<bpp>][@<refresh>]
16 - edid : verbatim EDID data block describing attached display.
17 Data from the detailed timing descriptor will be used to
[all …]
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mtk-svs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Lu <roger.lu@mediatek.com>
11 - Matthias Brugger <matthias.bgg@gmail.com>
12 - Kevin Hilman <khilman@kernel.org>
24 - mediatek,mt8183-svs
25 - mediatek,mt8186-svs
26 - mediatek,mt8188-svs
[all …]
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| /Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware Mobile Storage Host Controller Common Properties
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
11 The interface also requires a reference to the AVS host interrupt controller,
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
23 --------------------------
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
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| /Documentation/devicetree/bindings/dma/ |
| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| /Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhuv2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM MHUv2 Mailbox Controller
10 - Tushar Khandelwal <tushar.khandelwal@arm.com>
11 - Viresh Kumar <viresh.kumar@linaro.org>
14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
15 between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
19 Given the unidirectional nature of the controller, an MHUv2 mailbox may only
27 An MHU controller must be specified along with the supported transport
[all …]
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| /Documentation/devicetree/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
[all …]
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| /Documentation/driver-api/usb/ |
| D | writing_musb_glue_layer.rst | 12 use Universal Host Controller Interface (UHCI) or Open Host Controller
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
42 Linux USB stack is a layered architecture in which the MUSB controller
43 hardware sits at the lowest. The MUSB controller driver abstract the
44 MUSB controller hardware to the Linux USB stack::
46 ------------------------
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| /Documentation/devicetree/bindings/soundwire/ |
| D | qcom,soundwire.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SoundWire Controller
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
14 The Qualcomm SoundWire controller along with its board specific bus parameters.
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
[all …]
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| /Documentation/userspace-api/media/mediactl/ |
| D | media-controller-model.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-model:
9 is one of the goals of the media controller API. To achieve this,
14 - An **entity** is a basic media hardware or software building block.
17 hardware devices (a building block in a System-on-Chip image
20 - An **interface** is a graph representation of a Linux Kernel
24 - A **pad** is a data connection endpoint through which an entity can
25 interact with other entities. Data (not restricted to video) produced
30 - A **data link** is a point-to-point oriented connection between two
31 pads, either on the same entity or on different entities. Data flows
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | st,stm32-fmc2-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
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| /Documentation/admin-guide/auxdisplay/ |
| D | cfag12864b.rst | 7 :Date: 2006-10-27
19 ---------------------
25 ---------------------
36 :Controller: ks0108
38 :Pages: 8 each controller
40 :Data size: 1 byte each address
45 ---------
55 Strobe ( 1)------------------------------(17) Enable
56 Data 0 ( 2)------------------------------( 4) Data 0
57 Data 1 ( 3)------------------------------( 5) Data 1
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| /Documentation/driver-api/ |
| D | slimbus.rst | 9 ----------------
12 configuration, and is a 2-wire multi-drop implementation (clock, and data).
15 (System-on-Chip) and peripheral components (typically codec). SLIMbus uses
16 Time-Division-Multiplexing to accommodate multiple data channels, and
21 reading/writing device specific values), or multicast (e.g. data channel
24 A data channel is used for data-transfer between 2 SLIMbus devices. Data
28 ---------------------
36 Framer device is responsible for clocking the bus, and transmitting frame-sync
42 1 generic device (for data channel support), and 1 interface device.
44 functionality/data channel support), and an associated interface device.
[all …]
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| /Documentation/devicetree/bindings/nvmem/ |
| D | sprd-efuse.txt | 4 - compatible: Should be "sprd,ums312-efuse".
5 - reg: Specify the address offset of efuse controller.
6 - clock-names: Should be "enable".
7 - clocks: The phandle and specifier referencing the controller's clock.
8 - hwlocks: Reference to a phandle of a hwlock provider node.
10 = Data cells =
17 compatible = "sprd,ums312-efuse";
19 clock-names = "enable";
23 /* Data cells */
29 = Data consumers =
[all …]
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| /Documentation/spi/ |
| D | spi-summary.rst | 5 02-Feb-2012
8 ------------
15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
18 commonly used. Each clock cycle shifts data out and data in; the clock
19 doesn't cycle except when there is a data bit to shift. Not all data bits
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
[all …]
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| /Documentation/devicetree/bindings/cache/ |
| D | baikal,bt1-l2-ctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 L2-cache Control Block
11 - Serge Semin <fancer.lancer@gmail.com>
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
17 L2-cache controller block is responsible for the tuning. Its DT node is
18 supposed to be a child of the system controller.
[all …]
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| /Documentation/devicetree/bindings/gpu/host1x/ |
| D | nvidia,tegra234-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
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