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/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/Documentation/core-api/
Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
77 Linux to keep track of mmap'd regions for a process, the
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Ddma-api.rst8 of the API (and actual examples), see Documentation/core-api/dma-api-howto.rst.
11 Part II describes extensions for supporting non-consistent memory
13 non-consistent platforms (this is usually only legacy platforms) you
16 Part I - dma_API
17 ----------------
19 To get the dma_API, you must #include <linux/dma-mapping.h>. This
27 Part Ia - Using large DMA-coherent buffers
28 ------------------------------------------
33 dma_alloc_coherent(struct device *dev, size_t size,
42 This routine allocates a region of <size> bytes of consistent memory.
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/Documentation/admin-guide/
Dbcache.rst2 A block layer cache (bcache)
6 nice if you could use them as cache... Hence bcache.
11 This is the git repository of bcache-tools:
12 https://git.kernel.org/pub/scm/linux/kernel/git/colyli/bcache-tools.git/
17 It's designed around the performance characteristics of SSDs - it only allocates
19 extents (which can be anywhere from a single sector to the bucket size). It's
25 great lengths to protect your data - it reliably handles unclean shutdown. (It
29 Writeback caching can use most of the cache for buffering writes - writing
36 average is above the cutoff it will skip all IO from that task - instead of
38 thus entirely bypass the cache.
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/Documentation/trace/
Devents-kmem.rst8 - Slab allocation of small objects of unknown type (kmalloc)
9 - Slab allocation of small objects of known type
10 - Page allocation
11 - Per-CPU Allocator Activity
12 - External Fragmentation
22 kmalloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
25 Heavy activity for these events may indicate that a specific cache is
37 kmem_cache_alloc_node call_site=%lx ptr=%p bytes_req=%zu bytes_alloc=%zu gfp_flags=%s node=%d
40 These events are similar in usage to the kmalloc-related events except that
41 it is likely easier to pin the event down to a specific cache. At the time
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Dftrace.rst2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
41 ----------------------
43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
47 ---------------
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/Documentation/filesystems/caching/
Dcachefiles.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Cache on Already Mounted Filesystem
15 (*) Starting the cache.
19 (*) Cache culling.
21 (*) Cache structure.
31 (*) On-demand Read.
37 CacheFiles is a caching backend that's meant to use as a cache a directory on
40 CacheFiles uses a userspace daemon to do some of the cache management - such as
44 The filesystem and data integrity of the cache are only as good as those of the
49 CacheFiles creates a misc character device - "/dev/cachefiles" - that is used
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Dfscache.rst1 .. SPDX-License-Identifier: GPL-2.0
10 This facility is a general purpose cache for network filesystems, though it
13 FS-Cache mediates between cache backends (such as CacheFiles) and network
16 +---------+
17 | | +--------------+
18 | NFS |--+ | |
19 | | | +-->| CacheFS |
20 +---------+ | +----------+ | | /dev/hda5 |
21 | | | | +--------------+
22 +---------+ +-------------->| | |
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/Documentation/mm/
Dslub.rst18 slabs that have data in them. See "slabinfo -h" for more options when
22 gcc -o slabinfo tools/mm/slabinfo.c
30 -------------------------------------------
35 slab_debug=<Debug-Options>
38 slab_debug=<Debug-Options>,<slab name1>,<slab name2>,...
55 A Enable failslab filter mark for the cache
58 - Switch all debugging off (useful if the kernel is
65 Trying to find an issue in the dentry cache? Try::
69 to only enable debugging on the dentry cache. You may use an asterisk at the
71 example, here's how you can poison the dentry cache as well as all kmalloc
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/Documentation/driver-api/usb/
Ddma.rst12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
21 - URBs have an additional "transfer_dma" field, as well as a transfer_flags
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
29 - There's a new "generic DMA API", parts of which are usable by USB device
37 and effects like cache-trashing can impose subtle penalties.
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/Documentation/
Dmemory-barriers.txt19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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/Documentation/filesystems/
Ddax.rst6 ----------
8 The page cache is usually used to buffer reads and writes to files.
12 For block devices that are memory-like, the page cache pages would be
19 -----
23 size equal to your kernel's `PAGE_SIZE`, so you may need to specify a block
24 size when creating the filesystem.
30 ------------------------------
32 When mounting the filesystem, use the ``-o dax`` option on the command line or
34 within the filesystem. It is equivalent to the ``-o dax=always`` behavior below.
38 ----------------------------
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Dramfs-rootfs-initramfs.rst1 .. SPDX-License-Identifier: GPL-2.0
12 --------------
15 mechanisms (the page cache and dentry cache) as a dynamically resizable
16 RAM-based filesystem.
24 memory. A similar mechanism (the dentry cache) greatly speeds up access to
28 dentries and page cache as usual, but there's nowhere to write them to.
34 you're mounting the disk cache as a filesystem. Because of this, ramfs is not
39 ------------------
43 device was of fixed size, so the filesystem mounted on it was of fixed
44 size. Using a ram disk also required unnecessarily copying memory from the
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Dceph.rst1 .. SPDX-License-Identifier: GPL-2.0
15 * N-way replication of data across storage nodes
32 re-replicated in a distributed fashion by the storage nodes themselves
37 in-memory cache above the file namespace that is extremely scalable,
39 and can tolerate arbitrary (well, non-Byzantine) node failures. The
44 loaded into its cache with a single I/O operation. The contents of
64 * They can not exceed 240 characters in size. This is because the MDS makes
66 `_<SNAPSHOT-NAME>_<INODE-NUMBER>`. Since filenames in general can't have
67 more than 255 characters, and `<node-id>` takes 13 characters, the long
68 snapshot names can take as much as 255 - 1 - 1 - 13 = 240.
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Daffs.rst1 .. SPDX-License-Identifier: GPL-2.0
19 in file names are case-insensitive, as they ought to be.
24 DOS\4 The original filesystem with directory cache. The directory
25 cache speeds up directory accesses on floppies considerably,
29 DOS\5 The Fast File System with directory cache. Supported read only.
84 The volume name, file system type and block size will
107 Amiga -> Linux:
111 - R maps to r for user, group and others. On directories, R implies x.
113 - W maps to w.
115 - E maps to x.
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Df2fs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WHAT IS Flash-Friendly File System (F2FS)?
7 NAND flash memory-based storage devices, such as SSD, eMMC, and SD cards, have
13 F2FS is a file system exploiting NAND flash memory-based storage devices, which
14 is based on Log-structured File System (LFS). The design has been focused on
18 Since a NAND flash memory-based storage device shows different characteristic
20 F2FS and its tools support various parameters not only for configuring on-disk
26 - git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git
30 - linux-f2fs-devel@lists.sourceforge.net
34 - https://bugzilla.kernel.org/enter_bug.cgi?product=File%20System&component=f2fs
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/Documentation/fault-injection/
Dfault-injection.rst5 See also drivers/md/md-faulty.c and "every_nth" module option for scsi_debug.
9 --------------------------------------
11 - failslab
15 - fail_page_alloc
19 - fail_usercopy
23 - fail_futex
27 - fail_sunrpc
31 - fail_make_request
34 /sys/block/<device>/make-it-fail or
35 /sys/block/<device>/<partition>/make-it-fail. (submit_bio_noacct())
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/Documentation/arch/loongarch/
Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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/Documentation/admin-guide/blockdev/
Dramdisk.rst14 -----------
18 in order to access the root filesystem (see Documentation/admin-guide/initrd.rst). It can
23 RAM from the buffer cache. The driver marks the buffers it is using as dirty
41 ---------------------------------
46 Size of the ramdisk.
48 This parameter tells the RAM disk driver to set up RAM disks of N k size. The
63 ---------------
85 -----------------------------------------------
96 a) Decide on the RAM disk size that you want. Say 2 MB for this example.
106 mke2fs -vm0 /dev/ram0 2048
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/Documentation/admin-guide/device-mapper/
Dvdo-design.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Design of dm-vdo
7 The dm-vdo (virtual data optimizer) target provides inline deduplication,
8 compression, zero-block elimination, and thin provisioning. A dm-vdo target
9 can be backed by up to 256TB of storage, and can present a logical size of
12 production environments ever since. It was made open-source in 2017 after
14 dm-vdo. For usage, see vdo.rst in the same directory as this file.
16 Because deduplication rates fall drastically as the block size increases, a
17 vdo target has a maximum block size of 4K. However, it can achieve
25 The design of dm-vdo is based on the idea that deduplication is a two-part
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Dpersistent-data.rst8 The more-sophisticated device-mapper targets require complex metadata
12 - Mikulas Patocka's multisnap implementation
13 - Heinz Mauelshagen's thin provisioning target
14 - Another btree-based caching target posted to dm-devel
15 - Another multi-snapshot target based on a design of Daniel Phillips
18 we'd like to reduce the number.
20 The persistent-data library is an attempt to provide a re-usable
21 framework for people who want to store metadata in device-mapper
22 targets. It's currently used by the thin-provisioning target and an
29 under drivers/md/persistent-data.
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/Documentation/networking/
Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
39 than the CPU's L1/L2 cache, 2) because it allows more queueing in the
44 ring-buffers for various performance reasons, and packets stalling
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
54 # ethtool -C ethX rx-usecs 30
72 * add_device DEVICE@NAME -- adds a single device
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/Documentation/virt/kvm/x86/
Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
17 a particular implementation such as tlb size)
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
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/Documentation/arch/arm/
Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
15 The size of DTCM or ITCM is minimum 4KiB so the typical
19 location and size of TCM memories. arch/arm/include/asm/cputype.h
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
29 size of TCM memories at runtime. This is used to read out and modify
30 TCM location and size. Notice that this is not a MMU table: you
52 - FIQ and other interrupt handlers that need deterministic
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