Searched +full:data +full:- +full:addr (Results 1 – 25 of 129) sorted by relevance
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| /Documentation/i2c/ |
| D | smbus-protocol.rst | 24 single data byte, the functions using SMBus protocol operation names execute 44 Addr (7 bits) I2C 7 bit address. Note that this can be expanded to 46 Comm (8 bits) Command byte, a data byte which often selects a register on 48 Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and 50 Count (8 bits) A data byte containing the length of a block operation. 52 [..] Data sent by I2C device, as opposed to data sent by the host 62 S Addr Rd/Wr [A] P 77 S Addr Rd [A] [Data] NA P 92 S Addr Wr [A] Data [A] P 105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P [all …]
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| D | i2c-protocol.rst | 16 Addr (7 bits) I2C 7 bit address. Note that this can be expanded to 18 Data (8 bits) A plain data byte. 20 [..] Data sent by I2C device, as opposed to data sent by the 30 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P 38 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P 50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P 64 These messages may still fail to SCL lo->hi timeout. 70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some 74 S Addr Rd [A] [Data] NA Data [A] P 77 we do not generate Addr, but we do generate the start condition S. [all …]
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 11 - compatible: Compatible property value should be "altr,nios2-1.0". 12 - reg: Contains CPU index. 13 - interrupt-controller: Specifies that the node is an interrupt controller 14 - #interrupt-cells: Specifies the number of cells needed to encode an 16 - clock-frequency: Contains the clock frequency for CPU, in Hz. 17 - dcache-line-size: Contains data cache line size. 18 - icache-line-size: Contains instruction line size. 19 - dcache-size: Contains data cache size. 20 - icache-size: Contains instruction cache size. 21 - altr,pid-num-bits: Specifies the number of bits to use to represent the process [all …]
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| /Documentation/devicetree/bindings/gpio/ |
| D | netxbig-gpio-ext.txt | 5 - compatible: "lacie,netxbig-gpio-ext". 6 - addr-gpios: GPIOs representing the address register (LSB -> MSB). 7 - data-gpios: GPIOs representing the data register (LSB -> MSB). 8 - enable-gpio: latches the new configuration (address, data) on raising edge. 12 netxbig_gpio_ext: netxbig-gpio-ext { 13 compatible = "lacie,netxbig-gpio-ext"; 15 addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH 18 data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH 21 enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 4 - compatible : "fsl,upm-nand". 5 - reg : should specify localbus chip select and size used for the chip. 6 - fsl,upm-addr-offset : UPM pattern offset for the address latch. 7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch. 10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins 13 (R/B#). For multi-chip devices, "n" GPIO definitions are required 17 - fsl,upm-wait-flags : add chip-dependent short delays after running the 18 UPM pattern (0x1), after writing a data byte (0x2) or after 20 - chip-delay : chip dependent delay for transferring data from array to [all …]
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| /Documentation/admin-guide/mm/damon/ |
| D | start.rst | 1 .. SPDX-License-Identifier: GPL-2.0 18 ------ 25 --------------- 37 Snapshot Data Access Patterns 44 $ sudo damo start "./masim ./configs/stairs.cfg --quiet" 46 0 addr [85.541 TiB , 85.541 TiB ) (57.707 MiB ) access 0 % age 10.400 s 47 1 addr [85.541 TiB , 85.542 TiB ) (413.285 MiB) access 0 % age 11.400 s 48 2 addr [127.649 TiB , 127.649 TiB) (57.500 MiB ) access 0 % age 1.600 s 49 3 addr [127.649 TiB , 127.649 TiB) (32.500 MiB ) access 0 % age 500 ms 50 4 addr [127.649 TiB , 127.649 TiB) (9.535 MiB ) access 100 % age 300 ms [all …]
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| /Documentation/devicetree/bindings/misc/ |
| D | ifm-csi.txt | 4 - compatible: "ifm,o2d-csi" 5 - reg: specifies sensor chip select number and associated address range 6 - interrupts: external interrupt line number and interrupt sense mode 8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable" 10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor 12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25) 13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16) 14 - ifm,csi-wait-cycles: sensor bus wait cycles 17 - ifm,csi-byte-swap: if this property is present, the byte swapping on 23 compatible = "ifm,o2d-csi"; [all …]
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| /Documentation/core-api/ |
| D | cachetlb.rst | 25 virtual-->physical address translations obtained from the software 59 modifications for the address space 'vma->vm_mm' in the range 60 'start' to 'end-1' will be visible to the cpu. That is, after 62 virtual addresses in the range 'start' to 'end-1'. 73 4) ``void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)`` 78 address space is available via vma->vm_mm. Also, one may 79 test (vma->vm_flags & VM_EXEC) to see if this region is 81 split-tlb type setups). 84 page table modification for address space 'vma->vm_mm' for 85 user virtual address 'addr' will be visible to the cpu. That [all …]
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| /Documentation/networking/ |
| D | j1939.rst | 1 .. SPDX-License-Identifier: (GPL-2.0 OR MIT) 14 ISO-11783 (ISOBUS). This last one specifies the so-called ETP (Extended 16 results in a maximum packet size of ((2 ^ 24) - 1) * 7 bytes == 111 MiB. 19 ------------------- 21 * SAE J1939-21 : data link layer 22 * SAE J1939-81 : network management 23 * ISO 11783-6 : Virtual Terminal (Extended Transport Protocol) 25 .. _j1939-motivation: 43 Furthermore, data transport should be handled properly during the address 56 ...). In-kernel code for these would not contribute to protocol stability. [all …]
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| D | mctp.rst | 1 .. SPDX-License-Identifier: GPL-2.0 11 The core code provides a socket-based interface to send and receive MCTP 24 A network defines a unique address space for MCTP endpoints by endpoint-ID 25 (described by DSP0236, section 3.2.31). A network has a user-visible identifier 39 -------------------- 41 MCTP uses ``AF_MCTP`` / ``PF_MCTP`` for the address- and protocol- families. 42 Since MCTP is message-based, only ``SOCK_DGRAM`` sockets are supported. 44 .. code-block:: C 51 specified with a ``sockaddr`` type, with a single-byte endpoint address: 53 .. code-block:: C [all …]
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| D | iso15765-2.rst | 1 .. SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 4 ISO 15765-2 (ISO-TP) 10 ISO 15765-2, also known as ISO-TP, is a transport protocol specifically defined 12 industry, for example as the transport protocol for UDSonCAN (ISO 14229-3) or 13 emission-related diagnostic services (ISO 15031-5). 15 ISO-TP can be used both on CAN CC (aka Classical CAN) and CAN FD (CAN with 17 CAN network using SAE J1939 as data link layer (however, this is not a 21 ------------------- 23 * ISO 15765-2:2024 : Road vehicles - Diagnostic communication over Controller 27 ---------- [all …]
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| D | af_xdp.rst | 1 .. SPDX-License-Identifier: GPL-2.0 20 XDP programs to redirect frames to a memory buffer in a user-space 29 descriptor ring points to a data buffer in a memory area called a 34 away. This again avoids copying data. 37 one of the rings references a frame by referencing its addr. The addr 43 FILL ring is used by the application to send down addr for the kernel 44 to fill in with RX packet data. References to these frames will then 46 COMPLETION ring, on the other hand, contains frame addr that the 62 then receive frame addr references in its own RX ring that point to 64 single-consumer / single-producer (for performance reasons), the new [all …]
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| D | phonet.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 ------------ 19 - USB with the CDC Phonet interface, 20 - infrared, 21 - Bluetooth, 22 - an RS232 serial port (with a dedicated "FBUS" line discipline), 23 - the SSI bus with some TI OMAP processors. 27 -------------- 32 uint8_t pn_media; /* Media type (link-layer identifier) */ 36 uint16_t pn_length; /* Big-endian message byte length (minus 6) */ [all …]
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| D | can.rst | 2 SocketCAN - Controller Area Network 20 .. _socketcan-motivation: 29 functionality. Usually, there is only a hardware-specific device 32 Queueing of frames and higher-level transport protocols like ISO-TP 34 character-device implementations support only one single process to 47 protocol family module and also vice-versa. Also, the protocol family 57 communicate using a specific transport protocol, e.g. ISO-TP, just 59 write application data byte streams, without having to deal with 60 CAN-IDs, frames, etc. 62 Similar functionality visible from user-space could be provided by a [all …]
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| /Documentation/userspace-api/ |
| D | mseal.rst | 1 .. SPDX-License-Identifier: GPL-2.0 17 such an attacker primitive can break control-flow integrity guarantees 18 since read-only memory that is supposed to be trusted can become writable 21 applications can additionally seal security critical data at runtime. 29 ----------------------- 30 ``int mseal(void \* addr, size_t len, unsigned long flags)`` 32 **addr**/**len**: virtual memory address range. 33 The address range set by **addr**/**len** must meet: 34 - The start address must be in an allocated VMA. 35 - The start address must be page aligned. [all …]
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| D | vduse.rst | 2 VDUSE - "vDPA Device in Userspace" 5 vDPA (virtio data path acceleration) device is a device that uses a 9 possible to implement software-emulated vDPA devices in userspace. And 11 control path is handled in the kernel and only the data path is 16 the data path is run by an unprivileged user. The support for other device 21 ---------------------------- 49 .. code-block:: c 59 return -ENOMEM; 92 return -1; 96 --------------- [all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | microchip,mcp3911.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Marcus Folkesson <marcus.folkesson@gmail.com> 12 - Kent Gustavsson <nedo80@gmail.com> 21 - microchip,mcp3910 22 - microchip,mcp3911 23 - microchip,mcp3912 24 - microchip,mcp3913 25 - microchip,mcp3914 [all …]
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| /Documentation/virt/kvm/devices/ |
| D | s390_flic.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 FLIC handles floating (non per-cpu) interrupts, i.e. I/O, service and some 8 machine check interruptions. All interrupts are stored in a per-vm list of 14 - add interrupts (KVM_DEV_FLIC_ENQUEUE) 15 - inspect currently pending interrupts (KVM_FLIC_GET_ALL_IRQS) 16 - purge all pending floating interrupts (KVM_DEV_FLIC_CLEAR_IRQS) 17 - purge one pending floating I/O interrupt (KVM_DEV_FLIC_CLEAR_IO_IRQ) 18 - enable/disable for the guest transparent async page faults 19 - register and modify adapter interrupt sources (KVM_DEV_FLIC_ADAPTER_*) 20 - modify AIS (adapter-interruption-suppression) mode state (KVM_DEV_FLIC_AISM) [all …]
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| D | arm-vgic-its.rst | 1 .. SPDX-License-Identifier: GPL-2.0 10 The ITS allows MSI(-X) interrupts to be injected into guests. This extension is 12 arm-vgic-v3.txt), but does not depend on having physical ITS controllers. 15 a separate, non-overlapping MMIO region. 22 ------------------------- 25 KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit) 33 -E2BIG Address outside of addressable IPA range 34 -EINVAL Incorrectly aligned address 35 -EEXIST Address already configured 36 -EFAULT Invalid user pointer for attr->addr. [all …]
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| /Documentation/trace/ |
| D | hisi-ptt.rst | 1 .. SPDX-License-Identifier: GPL-2.0 23 +--------------Core 0-------+ 25 | | [Root Port]---[Endpoint] 26 | | [Root Port]---[Endpoint] 27 | | [Root Port]---[Endpoint] 28 Root Complex |------Core 1-------+ 30 | | [Root Port]---[ Switch ]---[Endpoint] 31 | | [Root Port]---[Endpoint] `-[Endpoint] 32 | | [Root Port]---[Endpoint] 33 +---------------------------+ [all …]
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The STM32 MDMA is a general-purpose direct memory access controller capable of 13 described in the dma.txt file, using a five-cell specifier for each channel: 22 -bit 0-1: Source increment mode 24 0x2: Source address pointer is incremented after each data transfer 25 0x3: Source address pointer is decremented after each data transfer 26 -bit 2-3: Destination increment mode [all …]
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| /Documentation/filesystems/iomap/ |
| D | design.rst | 1 .. SPDX-License-Identifier: GPL-2.0 71 data. 78 1. Obtain a space mapping via ``->iomap_begin`` 80 2. For each sub-unit of work... 89 4. Release the mapping via ``->iomap_end``, if necessary 105 ----------- 127 device pre-shutdown hook from returning before other threads have 131 internal to the filesystem and must protect the file mapping data 152 ---------------- 158 .. code-block:: c [all …]
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| /Documentation/driver-api/ |
| D | ntb.rst | 5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects 6 the separate memory systems of two or more computers to the same PCI-Express 9 scratchpad and message registers. Scratchpad registers are read-and-writable 36 ---------------------------------------- 50 | dma-mapped |-ntb_mw_set_trans(addr) | 52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO 53 |------------| |--------------| | |--------------| 68 | dma-mapped | | | MW base addr |<== memory-mapped IO 69 | memory | | |--------------| 70 | (addr) |<===================| MW xlat addr |<-ntb_peer_mw_set_trans(addr) [all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | samsung-i2s.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 14 - $ref: dai-common.yaml# 19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. 21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with 25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for [all …]
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| /Documentation/trace/coresight/ |
| D | coresight-perf.rst | 1 .. SPDX-License-Identifier: GPL-2.0 4 CoreSight - Perf 10 Perf is able to locally access CoreSight trace data and store it to the 11 output perf data files. This data can then be later decoded to give the 13 can log such data with a perf record command like:: 15 perf record -e cs_etm//u testbinary 18 a perf.data trace file. That file would have AUX sections if CoreSight 22 perf report --stdio --dump -i perf.data 24 You should find some sections of this file have AUX data blocks like:: 26 …ERF_RECORD_AUXTRACE size: 0x11dd0 offset: 0 ref: 0x1b614fc1061b0ad1 idx: 0 tid: 531230 cpu: -1 [all …]
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