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/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx7ulp-pinctrl.txt4 ports and IOMUXC DDR for DDR interface.
8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
20 The last integer CONFIG is the pad setting value like
21 pull-up on this pin.
24 CONFIG settings.
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/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
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/Documentation/admin-guide/perf/
Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
10 Selection of the value for each counter is done via the config registers. There
16 The "format" directory describes format of the config (event ID) and config1/2
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
33 un-supported, and value 1 for supported.
37 --AXI_ID defines AxID matching value.
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Dhisi-pmu.rst13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
27 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
28 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
44 ------------------------------------------
46 ------------------------------------------
48 ------------------------------------------
50 ------------------------------------------
52 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
53 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
60 case, the linked-list loops on to create a circular MDMA transfer.
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/Documentation/ABI/testing/
Ddebugfs-driver-habanalabs46 the generic Linux user-space PCI mapping) because the DDR bar
47 is very small compared to the DDR memory and only the driver can
61 the generic Linux user-space PCI mapping) because the DDR bar
62 is very small compared to the DDR memory and only the driver can
77 Linux user-space PCI mapping) because the amount of internal
237 protected config space.
241 Linux user-space PCI mapping) because this space is protected
286 next read would return X+1-st newest state dump.
292 Description: Sets the stop-on_error option for the device engines. Value of
/Documentation/misc-devices/
Dspear-pcie-gadget.rst1 .. SPDX-License-Identifier: GPL-2.0
37 -----------------------
53 ------------------------
61 inta write 1 to assert INTA and 0 to de-assert.
83 #mount -t configfs none /Config
87 # cd /config/pcie_gadget.n/
106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
138 To de-assert INTA::
170 # cd -
/Documentation/admin-guide/media/
Dipu3.rst1 .. SPDX-License-Identifier: GPL-2.0
24 ImgU). The CIO2 driver is available as drivers/media/pci/intel/ipu3/ipu3-cio2*
25 and is enabled through the CONFIG_VIDEO_IPU3_CIO2 config option.
30 CONFIG_VIDEO_IPU3_IMGU config option.
36 Both of the drivers implement V4L2, Media Controller and V4L2 sub-device
38 MIPI CSI-2 interfaces through V4L2 sub-device sensor drivers.
44 interface to the user space. There is a video node for each CSI-2 receiver,
47 The CIO2 contains four independent capture channel, each with its own MIPI CSI-2
48 receiver and DMA engine. Each channel is modelled as a V4L2 sub-device exposed
49 to userspace as a V4L2 sub-device node and has two pads:
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/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
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