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/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml109 ti,otap-del-sel-ddr52:
110 description: Output tap delay for eMMC DDR52 timing
167 ti,itap-del-sel-ddr52:
168 description: Input tap delay for MMC DDR52 timing
234 ti,otap-del-sel-ddr52 = <0x5>;
239 ti,itap-del-sel-ddr52 = <0x3>;
Dsprd,sdhci-r11.yaml53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
Dmmc-controller.yaml348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":