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/Documentation/devicetree/bindings/dma/
Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
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/Documentation/misc-devices/
Dmrvl_cn10k_dpi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
25 queues and provisions the hardware resources, it cannot initiate any
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
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/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
7 Packet DMA.
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
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Dkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
6 the actual data movements across clients using destination queues. Every
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
13 ------------------
15 ------------------
17 |-> DMA instance #0
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Dk3-ringacc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Santosh Shilimkar <ssantosh@kernel.org>
12 - Grygorii Strashko <grygorii.strashko@ti.com>
17 circular data structure in memory. The RA eliminates the need for each DMA
19 state of the ring (base address, current offset). The DMA controller
26 management of the packet queues. The K3 SoCs can have more than one RA instances
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/Documentation/devicetree/bindings/net/
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/Documentation/driver-api/media/drivers/
Dipu6.rst1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
86 DMA and MMU
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
97 The IPU6 driver exports its own DMA operations. The IPU6 driver will update the
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/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
10 Region 1 has registers for functionality common to all queues.
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
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/Documentation/arch/arm/keystone/
Dknav-qmss.rst11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
13 Packet DMA.
15 management of the packet queues. Packets are queued/de-queued by writing or
24 knav qmss driver provides a set of APIs to drivers to open/close qmss queues,
25 allocate descriptor pools, map the descriptors, push/pop to queues etc. For
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
31 Accumulator QMSS queues using PDSP firmware
34 queue or multiple contiguous queues. drivers/soc/ti/knav_qmss_acc.c is the
37 1 or 32 queues per channel. More description on the firmware is available in
40 git://git.ti.com/keystone-rtos/qmss-lld.git
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/Documentation/networking/device_drivers/ethernet/google/
Dgve.rst1 .. SPDX-License-Identifier: GPL-2.0+
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
26 +--------------+----------+---------+
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/Documentation/networking/device_drivers/ethernet/huawei/
Dhinic.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The driver supports a range of link-speed devices (10GbE, 25GbE, 40GbE, etc.).
14 Some HiNIC devices support SR-IOV. This driver is used for Physical Function
17 HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
21 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
28 19e5:1822 - HiNIC PF
34 hinic_dev - Implement a Logical Network device that is independent from
37 hinic_hwdev - Implement the HW details of the device and include the components
46 The interface for accessing the pci device (DMA memory and PCI BARs).
55 Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
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/Documentation/block/
Dblk-mq.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Queue Block IO Queueing Mechanism (blk-mq)
7 The Multi-Queue Block IO Queueing Mechanism is an API to enable fast storage
16 ----------
26 However, with the development of Solid State Drives and Non-Volatile Memories
30 in those devices' design, the multi-queue mechanism was introduced.
36 to different CPUs) wanted to perform block IO. Instead of this, the blk-mq API
37 spawns multiple queues with individual entry points local to the CPU, removing
42 ---------
45 for instance), blk-mq takes action: it will store and manage IO requests to
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/Documentation/gpu/amdgpu/
Ddriver-core.rst11 E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.
32 This was a dedicated IP on older pre-vega chips, but has since
58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`.
60 SDMA (System DMA)
61 This is a multi-purpose DMA engine. The kernel driver uses it for
69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In
75 This is the multi-media engine. It handles video and image encode and
76 decode. It's exposed to userspace for user mode drivers (VA-API,
80 -------------------------------------
89 This is the microcontroller that controls the compute queues on the
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/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
16 and event queues and adding support for the ATS and PRI components of
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
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/Documentation/accel/
Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
8 accelerators in a common way to user-space and provide a common set of
11 These devices can be either stand-alone ASICs or IP blocks inside an SoC/GPU.
13 Machine-Learning (ML) and/or Deep-Learning (DL) computations, the accel layer
19 - Edge AI - doing inference at an edge device. It can be an embedded ASIC/FPGA,
21 are typically configured using registers and can work with or without DMA.
23 - Inference data-center - single/multi user devices in a large server. This
24 type of device can be stand-alone or an IP inside a SoC or a GPU. It will
25 have on-board DRAM (to hold the DL topology), DMA engines and
26 command submission queues (either kernel or user-space queues).
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/Documentation/devicetree/bindings/scsi/
Dhisilicon-sas.txt6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
18 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
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/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt7622-wed.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
15 intercept and handle access to the WLAN DMA queues and PCIe interrupts
21 - enum:
22 - mediatek,mt7622-wed
23 - mediatek,mt7981-wed
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/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
10 is queued even on a running DMA channel.
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
28 a check of the DMA channel reports a "stopped channel", the transfer should
36 A driver should be able to request a priority, especially the real-time
43 channel" linked to the requestor line, and the physical DMA channel is
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
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/Documentation/userspace-api/media/v4l/
Ddmabuf.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
7 Streaming I/O (DMA buffer importing)
12 a DMA buffer to userspace as a file descriptor (known as the exporter
13 role), import a DMA buffer from userspace using a file descriptor
25 importing DMA buffers through DMABUF file descriptors is supported is
29 This I/O method is dedicated to sharing DMA buffers between different
30 devices, which may be V4L devices or other video-related devices (e.g.
34 such file descriptor are exchanged. The descriptors and meta-information
36 :c:type:`v4l2_plane` in the multi-planar API case). The
43 .. code-block:: c
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Dvidioc-streamon.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_STREAMON - VIDIOC_STREAMOFF - Start or stop streaming I/O
48 Memory-to-memory devices will not start until ``VIDIOC_STREAMON`` has
54 The ``VIDIOC_STREAMOFF`` ioctl, apart of aborting or finishing any DMA
56 and it removes all buffers from the incoming and outgoing queues. That
90 On success 0 is returned, on error -1 and the ``errno`` variable is set
92 :ref:`Generic Error Codes <gen-errors>` chapter.
100 :ref:`pad-level format configuration <pad-level-formats>` and the
Duserp.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
21 data are exchanged, these pointers and meta-information are passed in
23 :c:type:`v4l2_plane` in the multi-planar API case). The
33 .. code-block:: c
41 if (ioctl (fd, VIDIOC_REQBUFS, &reqbuf) == -1) {
58 memory for DMA. [#f1]_
62 memory pages at any time between the completion of the DMA and this
70 possibly completing the requested DMA and overwriting valuable data.
74 application waits until a filled buffer can be dequeued, and re-enqueues
85 <func-select>` or :c:func:`poll()` function are always
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/Documentation/sound/designs/
Dcompress-accel.rst2 ALSA Co-processor Acceleration API
16 is able to handle "tasks" that are not bound to real-time operations
24 - serialization of multiple tasks for user space to allow multiple
27 - separate buffers (input + output) for each operation
29 - expose buffers using mmap to user space
31 - signal user space when the task is finished (standard poll mechanism)
47 Data I/O mechanism is using standard dma-buf interface with all advantages
62 +----------+
66 +----------+
72 all passthrough task ops +----------+
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