Searched +full:ethernet +full:- (Results 1 – 25 of 436) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | realtek,rtl82xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id001c.c800
21 - ethernet-phy-id001c.c816
22 - ethernet-phy-id001c.c838
23 - ethernet-phy-id001c.c840
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| D | microchip,lan95xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SMSC9500/LAN9530/LAN9730 USB Ethernet Controllers
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Device tree properties for hard wired SMSC95xx compatible USB Ethernet
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - usb424,9500 # SMSC9500 USB Ethernet Device
24 - usb424,9505 # SMSC9505 USB Ethernet Device
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| D | nxp,tja11xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
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| D | ethernet-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Ethernet Switch
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 Ethernet switches are multi-port Ethernet controllers. Each port has
16 its own number and is represented as its own Ethernet controller.
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| D | marvell,aquantia.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Aquantia Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Marvell Aquantia Ethernet PHY require a firmware to be loaded to actually
17 - Attached SPI flash directly to the PHY with the firmware. The PHY
19 - Read from a dedicated partition on system NAND declared in an
21 - Manually provided firmware loaded from a file in the filesystem.
24 - $ref: ethernet-phy.yaml#
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| D | cortina,gemini-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
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| D | intel,ixp4xx-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx ethernet
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
17 The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
19 the ethernet frames. It can optionally contain an MDIO bus to
24 const: intel,ixp4xx-ethernet
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| D | hisilicon-hip04-net.txt | 1 Hisilicon hip04 Ethernet Controller
3 * Ethernet controller node
6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
19 [1] Documentation/devicetree/bindings/net/ethernet.txt
26 - compatible: should be "hisilicon,mdio".
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| D | marvell-orion-net.txt | 1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
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| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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| D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
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| D | ethernet-phy-package.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Package Common Properties
10 - Christian Marangi <ansuelsmth@gmail.com>
13 PHY packages are multi-port Ethernet PHY of the same family
14 and each Ethernet PHY is affected by the global configuration
18 absolute and describe the real address of the Ethernet PHY on
23 pattern: "^ethernet-phy-package@[a-f0-9]+$"
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| D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
14 PHY designed for industrial Ethernet applications. It integrates
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
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| D | nixge.txt | 1 * NI XGE Ethernet controller
4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
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| D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
6 This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
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| D | marvell-pxa168.txt | 1 * Marvell PXA168 Ethernet Controller
4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device.
10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the same directory.
16 defined in ethernet.txt.
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | marvell,mv88e6xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
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| D | vitesse,vsc73xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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| D | dsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Switch
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Vladimir Oltean <olteanv@gmail.com>
15 This binding represents Ethernet Switches which have a dedicated CPU
16 port. That port is usually connected to an Ethernet Controller of the
21 $ref: /schemas/net/ethernet-switch.yaml#
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| D | marvell,mv88e6060.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
31 reset-gpios:
37 - $ref: dsa.yaml#/$defs/ethernet-ports
40 - compatible
41 - reg
46 - |
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| D | microchip,lan937x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
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| D | arrow,xrs700x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: dsa.yaml#/$defs/ethernet-ports
13 - George McCollister <george.mccollister@gmail.com>
16 The Arrow SpeedChips XRS7000 Series of single chip gigabit Ethernet switches
23 - enum:
24 - arrow,xrs7003e
25 - arrow,xrs7003f
26 - arrow,xrs7004e
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| /Documentation/infiniband/ |
| D | opa_vnic.rst | 2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
7 the Ethernet packets between HFI nodes.
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
14 permitted to exchange encapsulated Ethernet packets across a particular
15 virtual Ethernet switch. The virtual Ethernet switches are logical
18 nodes across the fabric exchange encapsulated Ethernet packets over a
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 14 -----------------------------------
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
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| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The QorIQ DPAA Ethernet Driver
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
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