Searched +full:fifo +full:- +full:width (Results 1 – 25 of 26) sorted by relevance
12
| /Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
|
| D | rockchip-sfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com>
14 - $ref: spi-controller.yaml#
32 - description: Bus Clock
33 - description: Module Clock
35 clock-names:
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
26 0x0: offset size is linked to the peripheral bus width
[all …]
|
| /Documentation/devicetree/bindings/mmc/ |
| D | bluefield-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
22 compatible = "mellanox,bluefield-dw-mshc";
25 fifo-depth = <0x100>;
26 clock-frequency = <24000000>;
27 bus-width = <8>;
28 cap-mmc-highspeed;
|
| D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
[all …]
|
| D | k3-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
30 compatible = "hisilicon,hi4511-dw-mshc";
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
|
| D | hisilicon,hi3798cv200-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
[all …]
|
| D | samsung,exynos-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
[all …]
|
| D | arm,pl18x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
[all …]
|
| D | mtk-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
[all …]
|
| /Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
|
| D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
23 - axis,artpec8-uart
24 - google,gs101-uart
[all …]
|
| /Documentation/networking/device_drivers/can/ctu/ |
| D | ctucanfd-driver.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
[all …]
|
| /Documentation/admin-guide/media/ |
| D | imx7.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
14 - CMOS Sensor Interface (CSI)
15 - Video Multiplexer
16 - MIPI CSI-2 Receiver
18 .. code-block:: none
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
24 | U | ------> CSI ---> Capture
27 Parallel Camera Input ----------------> | /
34 --------
[all …]
|
| D | imx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
27 packed <--> planar conversion. The IDMAC can also perform a simple
[all …]
|
| /Documentation/driver-api/dmaengine/ |
| D | provider.rst | 20 DMA-eligible devices to the controller itself. Whenever the device
33 memory copy operation, but our audio device could have a narrower FIFO
36 parameter called the transfer width.
44 transfer into smaller sub-transfers.
49 non-contiguous buffers to a contiguous buffer, which is called
50 scatter-gather.
53 scatter-gather. So we're left with two cases here: either we have a
56 that implements in hardware scatter-gather.
73 transfer width and the transfer size.
79 These were just the general memory-to-memory (also called mem2mem) or
[all …]
|
| /Documentation/sound/designs/ |
| D | tracepoints.rst | 19 ------------------------------------
25 -----------------------------------------------------
53 - SNDRV_PCM_HW_PARAM_ACCESS
54 - SNDRV_PCM_HW_PARAM_FORMAT
55 - SNDRV_PCM_HW_PARAM_SUBFORMAT
61 - SNDRV_PCM_HW_PARAM_SAMPLE_BITS
62 - SNDRV_PCM_HW_PARAM_FRAME_BITS
63 - SNDRV_PCM_HW_PARAM_CHANNELS
64 - SNDRV_PCM_HW_PARAM_RATE
65 - SNDRV_PCM_HW_PARAM_PERIOD_TIME
[all …]
|
| /Documentation/networking/device_drivers/ethernet/neterion/ |
| D | s2io.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver
7 Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
10 - 1. Introduction
11 - 2. Identifying the adapter/interface
12 - 3. Features supported
13 - 4. Command line parameters
14 - 5. Performance suggestions
15 - 6. Available Downloads
20 This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
[all …]
|
| /Documentation/arch/arm/omap/ |
| D | dss.rst | 7 TV-out and multiple display support, but there are lots of small improvements
10 The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
15 --------
19 - MIPI DPI (parallel) output
20 - MIPI DSI output in command mode
21 - MIPI DBI (RFBI) output
22 - SDI output
23 - TV output
24 - All pieces can be compiled as a module or inside kernel
25 - Use DISPC to update any of the outputs
[all …]
|
| /Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /Documentation/admin-guide/ |
| D | bcache.rst | 11 This is the git repository of bcache-tools:
12 https://git.kernel.org/pub/scm/linux/kernel/git/colyli/bcache-tools.git/
17 It's designed around the performance characteristics of SSDs - it only allocates
25 great lengths to protect your data - it reliably handles unclean shutdown. (It
29 Writeback caching can use most of the cache for buffering writes - writing
36 average is above the cutoff it will skip all IO from that task - instead of
47 You'll need bcache util from the bcache-tools repository. Both the cache device
50 bcache make -B /dev/sdb
51 bcache make -C /dev/sdc
53 `bcache make` has the ability to format multiple devices at the same time - if
[all …]
|
| /Documentation/scsi/ |
| D | sym53c8xx_2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SYM-2 driver
11 95170 DEUIL LA BARRE - FRANCE
15 2004-10-09
67 This driver supports the whole SYM53C8XX family of PCI-SCSI controllers.
68 It also support the subset of LSI53C10XX PCI-SCSI controllers that are based
72 with the FreeBSD SYM-2 driver. The 'glue' that allows this driver to work
81 - Wolfgang Stanglmeier <wolf@cologne.de>
82 - Stefan Esser <se@mi.Uni-Koeln.de>
84 1996: port of the ncr driver to Linux-1.2.13 and rename it ncr53c8xx.
[all …]
|
| D | ncr53c8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
64 10.4 PCI configuration fix-up boot option
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
97 - Gerard Roudier <groudier@free.fr>
101 - Wolfgang Stanglmeier <wolf@cologne.de>
102 - Stefan Esser <se@mi.Uni-Koeln.de>
106 - ncr53c8xx generic driver that supports all the SYM53C8XX family including
109 - sym53c8xx enhanced driver (a.k.a. 896 drivers) that drops support of oldest
[all …]
|
| /Documentation/translations/ko_KR/ |
| D | memory-barriers.txt | 2 This is a version of Documentation/memory-barriers.txt translated into Korean.
15 Documentation/memory-barriers.txt
39 일부 이상한 점들은 공식적인 메모리 일관성 모델과 tools/memory-model/ 에 있는
60 해당 배리어의 명시적 사용이 불필요해서 no-op 이 될수도 있음을 알아두시기
76 - 디바이스 오퍼레이션.
77 - 보장사항.
81 - 메모리 배리어의 종류.
82 - 메모리 배리어에 대해 가정해선 안될 것.
83 - 주소 데이터 의존성 배리어 (역사적).
84 - 컨트롤 의존성.
[all …]
|
12