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/Documentation/devicetree/bindings/phy/
Dhisilicon,hi3798cv200-combphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
14 const: hisilicon,hi3798cv200-combphy
19 '#phy-cells':
20 description: The cell contains the PHY mode
29 hisilicon,fixed-mode:
30 description: If the phy device doesn't support mode select but a fixed mode
[all …]
/Documentation/devicetree/bindings/net/
Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
7 These interrupts are ordered by fixed and follows variable
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
18 This is an integer and represents allowable DMA bursts when fixed burst.
[all …]
Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
[all …]
Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
[all …]
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
[all …]
/Documentation/filesystems/
Dhpfs.rst1 .. SPDX-License-Identifier: GPL-2.0
7 1998-2004, Mikulas Patocka
10 :homepage: https://artax.karlin.mff.cuni.cz/~mikulas/vyplody/hpfs/index-e.cgi
14 Chris Smith, 1993, original read-only HPFS, some code and hpfs structures file
24 Set owner/group/mode for files that do not have it specified in extended
25 attributes. Mode is inverted umask - for example umask 027 gives owner
27 that for files mode is anded with 0666. If you want files to have 'x'
32 CR/LF -> LF conversion, if auto, decision is made according to extension
33 - there is a list of text extensions (I thing it's better to not convert
43 corrupted filesystems. check=strict means many superfluous checks -
[all …]
/Documentation/devicetree/bindings/regulator/
Drichtek,rtq2208.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alina Yu <alina_yu@richtek.com>
14 multi-configurable synchronous buck converters and two LDOs.
16 Bucks support "regulator-allowed-modes" and "regulator-mode". The former defines the permitted
17 switching operation in normal mode; the latter defines the operation in suspend to RAM mode.
19 No matter the RTQ2208 is configured to normal or suspend to RAM mode, there are two switching
20 operation modes for all buck rails, automatic power saving mode (Auto mode) and forced continuous
21 conduction mode (FCCM).
[all …]
/Documentation/devicetree/bindings/net/dsa/
Dlan9303.txt2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
27 I2C managed mode:
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
[all …]
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
[all …]
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/Documentation/networking/devlink/
Dbnxt.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``enable_sriov``
18 - Permanent
19 * - ``ignore_ari``
20 - Permanent
21 * - ``msix_vec_per_pf_max``
22 - Permanent
[all …]
Dnfp.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``fw_load_policy``
18 - permanent
19 * - ``reset_dev_on_drv_probe``
20 - permanent
27 .. list-table:: devlink info versions implemented
30 * - Name
[all …]
Dmlxsw.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``fw_load_policy``
18 - driverinit
20 The ``mlxsw`` driver also implements the following driver-specific
23 .. list-table:: Driver-specific parameters implemented
26 * - Name
27 - Type
[all …]
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Justified Mode, Right Justified Mode, and DSP mode formats.
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
[all …]
Dcs35l32.txt5 - compatible : "cirrus,cs35l32"
7 - reg : the I2C address of the device for I2C. Address is determined by the level
10 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
18 - cirrus,boost-manager : Boost voltage control.
19 0 = Automatically managed. Boost-converter output voltage is the higher
21 1 = Automatically managed irrespective of audio, adapting for low-power
22 dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
24 2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP).
25 3 = Boost voltage fixed at 5 V.
[all …]
Dbrcm,bcm63xx-audio.txt4 - compatible: Should be "brcm,bcm63xx-i2s".
5 - #address-cells: 32bit valued, 1 cell.
6 - #size-cells: 32bit valued, 0 cell.
7 - reg: Should contain audio registers location and length
8 - interrupts: Should contain the interrupt for the controller.
9 - clocks: Must contain an entry for each entry in clock-names.
10 Please refer to clock-bindings.txt.
11 - clock-names: One of each entry matching the clocks phandles list:
12 - "i2sclk" (generated clock) Required.
13 - "i2sosc" (fixed 200MHz clock) Required.
[all …]
/Documentation/devicetree/bindings/mmc/
Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
[all …]
/Documentation/admin-guide/
Dsvga.rst4 Video Mode Selection Support 2.13
7 :Copyright: |copy| 1995--1999 Martin Mares, <mj@ucw.cz>
12 This small document describes the "Video Mode Selection" feature which
21 enter ``scan`` on the video mode prompt, pick the mode you want to use,
22 remember its mode ID (the four-digit hexadecimal number) and then
25 The video mode to be used is selected by a kernel parameter which can be
31 NORMAL_VGA - Standard 80x25 mode available on all display adapters.
33 EXTENDED_VGA - Standard 8-pixel font mode: 80x43 on EGA, 80x50 on VGA.
35 ASK_VGA - Display a video mode menu upon startup (see below).
37 0..35 - Menu item number (when you have used the menu to view the list of
[all …]
/Documentation/firmware-guide/acpi/dsd/
Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
30 .. code-block:: none
48 phy-mode
49 --------
[all …]
/Documentation/devicetree/bindings/iio/resolver/
Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
22 The mode of operation of the communication channel (parallel or serial) is
23 selected by the A0 and A1 input pins. In normal mode, data is latched by
24 toggling the SAMPLE line and can then be read directly. In configuration mode,
[all …]
/Documentation/networking/
Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
30 2. Fixed mode
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
[all …]
/Documentation/hwmon/
Dnzxt-kraken3.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver nzxt-kraken3
20 -----------
23 Z53/Z63/Z73 and Kraken 2023 (standard and Elite) all-in-one CPU liquid coolers.
25 control (either as a fixed value or through a temp-PWM curve). The Z-series and
29 Pump and fan duty control mode can be set through pwm[1-2]_enable, where 1 is
30 for the manual control mode and 2 is for the liquid temp to PWM curve mode.
34 The temperature of the curves relates to the fixed [20-59] range, correlating to
35 the detected liquid temperature. Only PWM values (ranging from 0-255) can be set.
36 If in curve mode, setting point values should be done in moderation - the devices
[all …]
/Documentation/fb/
Dtgafb.rst9 - ZLxP-E1 (8bpp, 2 MB VRAM)
10 - ZLxP-E2 (32bpp, 8 MB VRAM)
11 - ZLxP-E3 (32bpp, 16 MB VRAM, Zbuffer)
20 * Support for fixed-frequency and other oddball monitors
21 (by allowing the video mode to be set at boot time)
23 User-visible changes since Linux 2.2.x:
25 * Sync-on-green is now handled properly
47 mode:X default video mode. The following video modes are supported:
48 640x480-60, 800x600-56, 640x480-72, 800x600-60, 800x600-72,
49 1024x768-60, 1152x864-60, 1024x768-70, 1024x768-76,
[all …]

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