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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
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| /Documentation/filesystems/ext4/ |
| D | checksums.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
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| /Documentation/arch/x86/x86_64/ |
| D | 5level-paging.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 5-level paging
9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
31 In this case additional page table level -- p4d -- will be folded at
34 User-space and large virtual address space
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| D | fred.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 establishes the full supervisor context and that event return
21 establishes the full user context.
33 The LKGS instruction can be used by 64-bit operating systems that do
46 framework must be implemented to facilitate the event-to-handler
48 once an event is delivered, and employs a two-level dispatch.
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
65 FRED always restores the full value of %rsp, thus ESPFIX is no longer
|
| /Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 2 APM X-Gene SoC Performance Monitoring Unit (PMU)
5 X-Gene SoC PMU consists of various independent system device PMUs such as
12 -----------------
14 The xgene-pmu driver registers several perf PMU drivers. Each of the perf
21 can be used with perf tool. For example, "l3c0/bank-fifo-full/" is an
27 masking the agents from which the request come from. If the bit with
28 the bit number corresponding to the agent is set, the event is counted only if
29 it is caused by a request from that agent. Each agent ID bit is inversely mapped
30 to a corresponding bit in "config1" field. By default, the event will be
32 each PMU, please refer to APM X-Gene User Manual.
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| /Documentation/w1/slaves/ |
| D | w1_ds2438.rst | 16 -----------
28 -----
29 This file controls the 'Current A/D Control Bit' (IAD) in the
31 Writing a zero value will clear the IAD bit and disables the current
33 Writing value "1" is setting the IAD bit (enables the measurements).
34 The IAD bit is enabled by default in the DS2438.
36 When writing to sysfs file bits 2-7 are ignored, so it's safe to write ASCII.
40 -------
41 This file provides full 8 bytes of the chip Page 0 (00h).
48 -------
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| /Documentation/networking/device_drivers/can/ |
| D | can327.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
29 into full fledged (as far as possible) CAN interfaces.
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
50 -----------
59 ----------------------------------
68 --debug \
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| /Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
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| /Documentation/hwmon/ |
| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
33 setting a bit to 0 enables the voltage input.
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
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| D | gsc-hwmon.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Kernel driver gsc-hwmon
11 ------------
19 ------------------
30 ----------------------
32 Temperatures are measured with 12-bit or 10-bit resolution and are scaled
41 ------------------
45 The tempeature boundaries are read-write and in millidegree Celsius and the
46 read-only PWM values range from 0 (off) to 255 (full speed).
51 pwm1_auto_point[1-6]_pwm PWM value.
[all …]
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …g a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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| /Documentation/devicetree/bindings/serial/ |
| D | fsl,s32-linflexuart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 as support for full-duplex UART communication through 8-bit and 9-bit
16 - Chester Lin <chester62515@gmail.com>
19 - $ref: serial.yaml#
24 - const: fsl,s32v234-linflexuart
25 - items:
26 - enum:
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-dv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _dv-controls:
15 only exposed on the ``/dev/v4l-subdev*`` device node.
23 Identification Data, :ref:`vesaedid`) and HDCP (High-bandwidth Digital
29 bitmasks, one bit for each pad. Bit 0 corresponds to pad 0, bit 1 to pad
33 .. _dv-control-id:
44 hotplug pin as seen by the transmitter. Each bit corresponds to an
46 associated hotplug pin, then the bit for that pad will be 0. This
47 read-only control is applicable to DVI-D, HDMI and DisplayPort
51 Rx Sense is the detection of pull-ups on the TMDS clock lines. This
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
19 LAN8814: register EP5.0, bit 6
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-light-isl29018 | 4 Contact: linux-iio@vger.kernel.org
9 Scheme 0, makes full n (4, 8, 12, 16) bits (unsigned) proximity
11 2^n. Logic 1 of this bit, Scheme 1, makes n-1 (3, 7, 11, 15)
13 range of Scheme 1 proximity count is from -2^(n-1) to 2^(n-1).
14 The sign bit is extended for resolutions less than 16. While
|
| /Documentation/userspace-api/netlink/ |
| D | specs.rst | 1 .. SPDX-License-Identifier: BSD-3-Clause
17 - the C uAPI header
18 …- documentation of the protocol as a ReST file - see :ref:`Documentation/networking/netlink_spec/i…
19 - policy tables for input attribute validation
20 - operation tables
25 See :doc:`intro-specs` for a practical starting guide.
28 ``((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)``
40 - ``genetlink`` - most streamlined, should be used by all new families
41 - ``genetlink-c`` - superset of ``genetlink`` with extra attributes allowing
45 - ``genetlink-legacy`` - Generic Netlink catch all schema supporting quirks of
[all …]
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| /Documentation/ABI/stable/ |
| D | sysfs-bus-vmbus | 42 Description: The 16 bit device ID of the device
49 Description: The 16 bit vendor ID of the device
57 attached, or -1 if the node is unknown.
63 Description: Directory for per-channel information
144 Description: Monitor bit associated with channel. This file is available only
161 buffer transitioning from full to not full while a packet is
178 outbound ring buffer full condition
186 ring buffer full condition
|
| /Documentation/devicetree/bindings/spi/ |
| D | icpdas-lp8841-spi-rtc.txt | 1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
23 - There can be only one slave device.
25 - The spi slave node should claim the following flags which are
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
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| /Documentation/spi/ |
| D | spidev.rst | 5 SPI devices have a limited userspace API, supporting basic half-duplex
7 full duplex transfers and device I/O configuration are also available.
19 * Prototyping in an environment that's not crash-prone; stray pointers
38 - struct spi_device_id spidev_spi_ids[]: list of devices that can be
42 - struct of_device_id spidev_dt_ids[]: list of devices that can be
46 - struct acpi_device_id spidev_acpi_ids[]: list of devices that can
52 post a patch for spidev to the linux-spi@vger.kernel.org mailing list.
101 Since this is a standard Linux device driver -- even though it just happens
102 to expose a low level API to userspace -- it can be associated with any number
112 Standard read() and write() operations are obviously only half-duplex, and
[all …]
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| /Documentation/security/tpm/ |
| D | tpm_tis.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 buffer containing the full command or response.
11 FIFO (First-In-First-Out) interface is used by the tpm_tis_core dependent
23 further split into five equal-size 4 KiB buffers, which provide equivalent
28 locality 0 by setting the requestUse bit in the TPM_ACCESS register. The bit is
30 communication, the kernel writes the TPM_ACCESS.activeLocality bit. This
36 - Locality 0 has the lowest priority.
37 - Locality 5 has the highest priority.
46 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
|
| /Documentation/admin-guide/ |
| D | vga-softcursor.rst | 9 tricks: you can make your cursor look like a non-blinking red block,
26 8=full block
40 on highlight (or sometimes blinking -- it depends on the configuration
46 Bit setting takes place before bit toggling, so you can simply clear a
47 bit by including it in both the set mask and the toggle mask.
50 --------
54 echo -e '\033[?2c'
58 echo -e '\033[?6c'
60 To get red non-blinking block, use::
62 echo -e '\033[?17;0;64c'
|
| /Documentation/devicetree/bindings/w1/ |
| D | w1-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
[all …]
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| /Documentation/userspace-api/media/cec/ |
| D | cec-pin-error-inj.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
15 What makes doing this so interesting is that since we have full control
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
32 With ``cat error-inj`` you can see both the possible commands and the current
35 $ cat /sys/kernel/debug/cec/cec0/error-inj
38 # rx-clear clear all rx error injections
[all …]
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad9739a.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dragos Bogdan <dragos.bogdan@analog.com>
11 - Nuno Sa <nuno.sa@analog.com>
14 The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ad9737a_9739a.pdf
22 - adi,ad9739a
30 reset-gpios:
36 vdd-3p3-supply:
[all …]
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
38 KVM clock are special enough to warrant a full exposition and are described in
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
57 controlled by port 61h, bit 0, as illustrated in the following diagram::
59 -------------- ----------------
[all …]
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