Searched +full:generic +full:- +full:names (Results 1 – 25 of 266) sorted by relevance
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| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-ath79.txt | 4 - compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
5 - reg: Base address and size of the controllers memory area
6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
8 - #address-cells: <1>, as required by generic SPI binding.
9 - #size-cells: <0>, also as required by generic SPI binding.
11 Child nodes as per the generic SPI binding.
16 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
20 clock-names = "ahb";
22 #address-cells = <1>;
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| /Documentation/devicetree/bindings/clock/ |
| D | microchip,lan966x-gck.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN966X Generic Clock Controller
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
19 const: microchip,lan966x-gck
24 - description: Generic clock registers
25 - description: Optional gate clock registers
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| /Documentation/devicetree/bindings/net/ |
| D | nixge.txt | 4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
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| D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
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| /Documentation/devicetree/bindings/thermal/ |
| D | generic-adc-thermal.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/thermal/generic-adc-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
16 temperature using voltage-temperature lookup table.
18 $ref: thermal-sensor.yaml#
22 const: generic-adc-thermal
24 '#thermal-sensor-cells':
27 io-channels:
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| /Documentation/devicetree/bindings/serial/ |
| D | renesas,scif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,scif-r7s72100 # RZ/A1H
18 - const: renesas,scif # generic SCIF compatible UART
20 - items:
21 - enum:
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| D | renesas,em-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Magnus Damm <magnus.damm@gmail.com>
15 - items:
16 - enum:
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
20 - items:
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| D | renesas,hscif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,hscif-r8a7778 # R-Car M1
21 - renesas,hscif-r8a7779 # R-Car H1
22 - const: renesas,rcar-gen1-hscif # R-Car Gen1
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| D | renesas,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-sci # RZ/G2{L,LC}
22 - renesas,r9a07g054-sci # RZ/V2L
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| D | renesas,scifa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,scifa-r8a73a4 # R-Mobile APE6
21 - renesas,scifa-r8a7740 # R-Mobile A1
22 - renesas,scifa-sh73a0 # SH-Mobile AG5
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| D | renesas,scifb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,scifb-r8a73a4 # R-Mobile APE6
21 - renesas,scifb-r8a7740 # R-Mobile A1
22 - renesas,scifb-sh73a0 # SH-Mobile AG5
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| /Documentation/devicetree/bindings/usb/ |
| D | generic-xhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-xhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathias Nyman <mathias.nyman@intel.com>
15 - description: Generic xHCI device
16 const: generic-xhci
17 - description: Armada 37xx/375/38x/8k SoCs
19 - enum:
20 - marvell,armada3700-xhci
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| D | aspeed,ast2600-udc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/aspeed,ast2600-udc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neal Liu <neal_liu@aspeedtech.com>
15 4 generic endpoints for AST260x.
17 Supports independent DMA channel for each generic endpoint.
18 Supports 32/256 stages descriptor mode for all generic endpoints.
23 - aspeed,ast2600-udc
35 - compatible
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| D | generic-ohci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 - items:
16 - enum:
17 - allwinner,sun4i-a10-ohci
18 - allwinner,sun50i-a64-ohci
19 - allwinner,sun50i-h6-ohci
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-omap.txt | 8 - compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
9 Should be "ti,omap3-sdhci" for omap3 controllers
10 Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
11 Should be "ti,omap5-sdhci" for omap5 controllers
12 Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
13 Should be "ti,k2g-sdhci" for K2G
14 Should be "ti,am335-sdhci" for am335x controllers
15 Should be "ti,am437-sdhci" for am437x controllers
16 - ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
18 - pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
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| D | amlogic,meson-mx-sdio.txt | 13 - compatible : must be one of
14 - "amlogic,meson8-sdio"
15 - "amlogic,meson8b-sdio"
16 along with the generic "amlogic,meson-mx-sdio"
17 - reg : mmc controller base registers
18 - interrupts : mmc controller interrupt
19 - #address-cells : must be 1
20 - size-cells : must be 0
21 - clocks : phandle to clock providers
22 - clock-names : must contain "core" and "clkin"
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
35 mbox-names = "pwr-ctrl", "rpc";
42 compatible = "mmio-sram";
45 #address-cells = <1>;
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| /Documentation/devicetree/bindings/hwlock/ |
| D | hwlock.txt | 1 Generic hwlock bindings
4 Generic bindings that are common to all the hwlock platform specific driver
15 - #hwlock-cells: Specifies the number of cells needed to represent a
22 property "hwlocks", and an optional "hwlock-names" property.
25 - hwlocks: List of phandle to a hwlock provider node and an
27 #hwlock-cells. The list can have just a single hwlock
32 - hwlock-names: List of hwlock name strings defined in the same order
34 use the hwlock-names to match and get a specific hwlock.
52 the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
53 hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | resistive-adc-touch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/resistive-adc-touch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic resistive touchscreen ADC
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Generic ADC based resistive touchscreen controller
18 - $ref: touchscreen.yaml#
22 const: resistive-adc-touch
24 io-channels:
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| /Documentation/devicetree/bindings/ata/ |
| D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
29 Generic AHCI registers space conforming to the Serial ATA AHCI
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-mvebu-comphy.txt | 2 --------------------
12 - compatible: should be one of:
13 * "marvell,comphy-cp110" for Armada 7k/8k
14 * "marvell,comphy-a3700" for Armada 3700
15 - reg: should contain the COMPHY register(s) location(s) and length(s).
17 * 4 entries for Armada 3700 along with the corresponding reg-names
19 * Generic COMPHY registers
23 - marvell,system-controller: should contain a phandle to the system
25 - #address-cells: should be 1.
26 - #size-cells: should be 0.
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| D | dm816x-phy.txt | 5 - compatible : should be "ti,dm816x-usb-phy"
6 - reg : offset and length of the PHY register set.
7 - reg-names : name for the phy registers
8 - clocks : phandle to the clock
9 - clock-names : name of the clock
10 - syscon: phandle for the syscon node to access misc registers
11 - #phy-cells : from the generic PHY bindings, must be 1
12 - syscon: phandle for the syscon node to access misc registers
16 usb_phy0: usb-phy@20 {
17 compatible = "ti,dm8168-usb-phy";
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| /Documentation/devicetree/bindings/sound/ |
| D | ac97-bus.txt | 1 Generic AC97 Device Properties
7 -compatible : Must be "ac97,vendor_id1,vendor_id2
10 -reg : Must be the ac97 codec number, between 0 and 3
14 compatible = "marvell,pxa270-ac97";
17 reset-gpios = <&gpio 95 GPIO_ACTIVE_HIGH>;
18 #sound-dai-cells = <1>;
19 pinctrl-names = "default";
20 pinctrl-0 = < &pinctrl_ac97_default >;
22 clock-names = "AC97CLK", "AC97CONFCLK";
24 #address-cells = <1>;
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