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/Documentation/driver-api/iio/
Dtriggered-buffers.rst26 pf->timestamp = iio_get_time_ns((struct indio_dev *)p);
36 for_each_set_bit(bit, active_scan_mask, masklength)
37 buf[i++] = sensor_get_data(bit)
56 * **sensor_iio_pollfunc**, the function that will be used as top half of poll
61 * **sensor_trigger_handler**, the function that will be used as bottom half of
65 top half.
69 .. kernel-doc:: drivers/iio/buffer/industrialio-triggered-buffer.c
/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
[all …]
/Documentation/filesystems/
Dqnx6.rst1 .. SPDX-License-Identifier: GPL-2.0
29 ------
35 Blockpointers are 32bit, so the maximum space that can be addressed is
39 ---------------
42 Each qnx6fs got two superblocks, each one having a 64bit serial number.
65 Unused block pointers are always set to ~0 - regardless of root node,
79 0x1000 is the size reserved for each superblock - regardless of the
83 ------
100 The filesize is stored 64bit. Inode counting starts with 1. (while long
104 -----------
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/Documentation/devicetree/bindings/timer/
Dti,keystone-timer.txt3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
Dti,da830-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
18 The timer is a free running up-counter and can generate interrupts when the
23 const: ti,da830-timer
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/Documentation/devicetree/bindings/memory-controllers/
Dxlnx,zynq-ddrc-a05.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
15 (16-bit) configuration. It is capable of correcting single bit ECC errors
16 and detecting double bit ECC errors.
20 const: xlnx,zynq-ddrc-a05
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Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/Documentation/userspace-api/media/dvb/
Dlegacy_dvb_osd.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later OR GPL-2.0
14 The DVB OSD device controls the OnScreen-Display of the AV7110 based
15 DVB-cards with hardware MPEG2 decoder. It can be accessed through
20 The OSD is not a frame-buffer like on many other cards.
22 The color-depth is limited depending on the memory size installed.
31 -----------
36 .. code-block:: c
39 /* All functions return -2 on "not open" */
67 .. note:: All functions return -2 on "not open"
69 .. flat-table::
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/Documentation/userspace-api/media/v4l/
Dpixfmt-sdr-pcu16be.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU16BE:
9 Planar complex unsigned 16-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 16 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
20 the 16 bits, bit 15:2 (14 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
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Dpixfmt-sdr-pcu18be.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU18BE:
9 Planar complex unsigned 18-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 18 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
20 the 18 bits, bit 17:2 (16 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
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Dpixfmt-sdr-pcu20be.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU20BE:
9 Planar complex unsigned 20-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 20 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
19 equalling half of the buffer size (i.e.) offset = buffersize/2. Out of
20 the 20 bits, bit 19:2 (18 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
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Dvidioc-g-dv-timings.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - VIDIOC_SUBDEV_G_DV_TIMINGS - VIDIOC_SUBDEV_S_DV_TIMINGS…
56 registered in read-only mode is not allowed. An error is returned and the errno
57 variable is set to ``-EPERM``.
59 The ``linux/v4l2-dv-timings.h`` header can be used to get the timings of
68 On success 0 is returned, on error -1 and the ``errno`` variable is set
70 :ref:`Generic Error Codes <gen-errors>` chapter.
83 ``VIDIOC_SUBDEV_S_DV_TIMINGS`` has been called on a read-only subdevice.
91 .. flat-table:: struct v4l2_bt_timings
92 :header-rows: 0
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/Documentation/devicetree/bindings/dma/
Datmel-dma.txt4 - compatible: Should be "atmel,<chip>-dma".
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
7 - #dma-cells: Must be <2>, used to represent the number of integer cells in
13 compatible = "atmel,at91sam9g45-dma";
16 #dma-cells = <2>;
20 described in the dma.txt file, using a three-cell specifier for each channel:
29 - bit 7-0: peripheral identifier for the hardware handshaking interface. The
31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
36 compatible = "atmel,at91sam9x5-i2c";
[all …]
/Documentation/devicetree/bindings/net/
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
19 LAN8814: register EP5.0, bit 6
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
/Documentation/devicetree/bindings/spi/
Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
23 - There can be only one slave device.
25 - The spi slave node should claim the following flags which are
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
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/Documentation/devicetree/bindings/i3c/
Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
20 pattern: "^i3c@[0-9a-f]+$"
22 "#address-cells":
39 "#size-cells":
42 i3c-scl-hz:
49 i2c-scl-hz:
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/Documentation/crypto/
Ddescore-readme.rst1 .. SPDX-License-Identifier: GPL-2.0
13 ------------------------------------------------------------------------------
15 des - fast & portable DES encryption & decryption.
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
43 3. Plug-compatible replacement for KERBEROS's low-level routines.
46 register-starved machines. My discussions with Richard Outerbridge,
51 up in a parameterized fashion so it can easily be modified by speed-daemon
58 compile on a SPARCStation 1 (cc -O4, gcc -O2):
60 this code (byte-order independent):
62 - 30us per encryption (options: 64k tables, no IP/FP)
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/Documentation/i2c/busses/
Di2c-mlxcpld.rst2 Driver i2c-mlxcpld
11 - Master mode.
12 - One physical bus.
13 - Polling mode.
20 - Receive Byte/Block.
21 - Send Byte/Block.
22 - Read Byte/Block.
23 - Write Byte/Block.
28 CPBLTY 0x0 - capability reg.
29 Bits [6:5] - transaction length. b01 - 72B is supported,
[all …]
/Documentation/admin-guide/hw-vuln/
Dindirect-target-selection.rst1 .. SPDX-License-Identifier: GPL-2.0
8 of indirect branches and RETs located in the lower half of a cacheline.
10 ITS is assigned CVE-2024-28956 with a CVSS score of 4.7 (Medium).
13 ---------------
14 - **eIBRS Guest/Host Isolation**: Indirect branches in KVM/kernel may still be
17 - **Intra-Mode BTI**: In-kernel training such as through cBPF or other native
20 - **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
27 -------------
31 Common name Family_Model eIBRS Intra-mode BTI
47 - All affected CPUs enumerate Enhanced IBRS feature.
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/Documentation/networking/device_drivers/ethernet/dec/
Ddmfe.rst1 .. SPDX-License-Identifier: GPL-2.0
26 dmfe: Davicom DM9xxx net driver, version 1.36.4 (2002-01-17)
35 insmod dmfe mode=0 # Force 10M Half Duplex
36 insmod dmfe mode=1 # Force 100M Half Duplex
56 - Implement pci_driver::suspend() and pci_driver::resume() power management methods.
57 - Check on 64 bit boxes.
58 - Check and fix on big endian boxes.
59 - Test and make sure PCI latency is now correct for all cases.
68 - Marcelo Tosatti <marcelo@conectiva.com.br>
69 - Alan Cox <alan@lxorguk.ukuu.org.uk>
[all …]
/Documentation/devicetree/bindings/rtc/
Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
12 - compatible : Should be "maxim,ds1302"
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
/Documentation/networking/device_drivers/ethernet/ti/
Dtlan.rst1 .. SPDX-License-Identifier: GPL-2.0
9 (C) 1997-1998 Caldera, Inc.
13 (C) 1999-2001 Torben Mathiasen <tmm@image.dk, torben.mathiasen@compaq.com>
41 108d 0012 Olicom OC-2325
42 108d 0013 Olicom OC-2183
43 108d 0014 Olicom OC-2326
64 debug messages, where x is a bit field where the bits mean
81 3. You can set duplex=1 to force half duplex, and duplex=2 to
90 do "insmod tlan.o speed=100" the driver will do Auto-Neg.
91 To force a 10Mbps Half-Duplex link do "insmod tlan.o speed=10
[all …]
/Documentation/networking/device_drivers/ethernet/intel/
De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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