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/Documentation/devicetree/bindings/clock/
Damlogic,c3-peripherals-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic C3 series Peripheral Clock Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Xianwei Zhao <xianwei.zhao@amlogic.com>
14 - Chuan Liu <chuan.liu@amlogic.com>
[all …]
Damlogic,s4-peripherals-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic S4 Peripherals Clock Controller
11 - Yu Tu <yu.tu@amlogic.com>
15 const: amlogic,s4-peripherals-clkc
23 - description: input fixed pll div2
24 - description: input fixed pll div2p5
[all …]
Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
21 This binding document describes the binding for the clock portion of the
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
36 - cirrus,lochnagar1-clk
[all …]
Dmarvell,berlin.txt1 Device Tree Clock bindings for Marvell Berlin
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 Clock related registers are spread among the chip control registers. Berlin
8 clock node should be a sub-node of the chip controller node. Marvell Berlin2
13 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
14 - #clock-cells: must be 1
15 - clocks: must be the input parent clock phandle
16 - clock-names: name of the input parent clock
17 Allowed clock-names for the reference clocks are
[all …]
Dimx8m-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Family Clock Control Module
10 - Abel Vesa <abelvesa@kernel.org>
11 - Peng Fan <peng.fan@nxp.com>
14 NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
20 - fsl,imx8mm-ccm
21 - fsl,imx8mn-ccm
[all …]
Damlogic,a1-peripherals-clkc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic A1 Peripherals Clock Control Unit
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
12 - Jian Hu <jian.hu@jian.hu.com>
13 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
17 const: amlogic,a1-peripherals-clkc
[all …]
Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input-clk: input-clk {
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Dvf610-clock.txt1 * Clock bindings for Freescale Vybrid VF610 SOC
4 - compatible: Should be "fsl,vf610-ccm"
5 - reg: Address and length of the register set
6 - #clock-cells: Should be <1>
9 - clocks: list of clock identifiers which are external input clocks to the
10 given clock controller. Please refer the next section to find
11 the input clocks for a given controller.
12 - clock-names: list of names of clocks which are external input clocks to the
13 given clock controller.
15 Input clocks for top clock controller:
[all …]
Damlogic,axg-audio-clkc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG Audio Clock Controller
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
14 The Amlogic AXG audio clock controller generates and supplies clock to the
21 - amlogic,axg-audio-clkc
22 - amlogic,g12a-audio-clkc
[all …]
Dmaxim,max9485.txt1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provide 27.000 MHz
16 - clock-names: Must be set to "xclk"
17 - #clock-cells: From common clock binding; shall be set to 1
20 - reset-gpios: GPIO descriptor connected to the #RESET input pin
21 - vdd-supply: A regulator node for Vdd
[all …]
Dimx6sx-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 SoloX Clock Controller
10 - Abel Vesa <abelvesa@kernel.org>
11 - Peng Fan <peng.fan@nxp.com>
15 const: fsl,imx6sx-ccm
25 - description: CCM interrupt request 1
26 - description: CCM interrupt request 2
[all …]
Dcirrus,cs2000-cp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
21 - cirrus,cs2000-cp
25 Common clock binding for CLK_IN, XTI/REF_CLK
28 clock-names:
[all …]
Damlogic,a1-pll-clkc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic A1 PLL Clock Control Unit
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Jerome Brunet <jbrunet@baylibre.com>
12 - Jian Hu <jian.hu@jian.hu.com>
13 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
17 const: amlogic,a1-pll-clkc
[all …]
Damlogic,c3-pll-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic C3 series PLL Clock Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Chuan Liu <chuan.liu@amlogic.com>
14 - Xianwei Zhao <xianwei.zhao@amlogic.com>
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dadi,adv7511.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 space conversion, S/PDIF, CEC and HDCP. The transmitter input is
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
[all …]
/Documentation/devicetree/bindings/display/
Drenesas,du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
[all …]
/Documentation/devicetree/bindings/media/
Dsamsung,exynos4210-fimc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
20 - samsung,exynos4210-fimc
21 - samsung,exynos4212-fimc
22 - samsung,s5pv210-fimc
30 clock-names:
[all …]
Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
5 4 CSI lanes in output, and up to 4 different pixel streams in input.
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
13 * esc_clk: escape mode clock
14 * p_clk: register bank clock
[all …]
Dmicrochip,xisc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eugen Hristev <eugen.hristev@microchip.com>
14 The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
17 The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
21 The XISC provides one clock output that is used to clock the demuxer/bridge.
25 const: microchip,sama7g5-isc
36 clock-names:
38 - const: hclock
[all …]
Dmicrochip,csi2dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
19 clock domain towards a parallel interface that can be read by a sensor
30 32-bit IDI interface or a parallel interface.
44 const: microchip,sama7g5-csi2dc
53 clock-names:
55 CSI2DC must have two clocks to function correctly. One clock is the
[all …]
/Documentation/devicetree/bindings/net/pcs/
Drenesas,rzn1-miic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 '#address-cells':
20 '#size-cells':
25 - enum:
26 - renesas,r9a06g032-miic
27 - const: renesas,rzn1-miic
[all …]
/Documentation/devicetree/bindings/pwm/
Dpwm-amlogic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiner Kallweit <hkallweit1@gmail.com>
15 - enum:
16 - amlogic,meson8b-pwm
17 - amlogic,meson-gxbb-pwm
18 - amlogic,meson-gxbb-ao-pwm
19 - amlogic,meson-axg-ee-pwm
[all …]
/Documentation/devicetree/bindings/net/
Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
38 input clock. Used to determine the XI input clock.
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
/Documentation/devicetree/bindings/sound/
Dxlnx,spdif.txt1 Device-Tree bindings for Xilinx SPDIF IP
6 - compatible: "xlnx,spdif-2.0"
7 - clock-names: List of input clocks.
9 - clocks: Input clock specifier. Refer to common clock bindings.
10 - reg: Base address and address length of the IP core instance.
11 - interrupts-parent: Phandle for interrupt controller.
12 - interrupts: List of Interrupt numbers.
13 - xlnx,spdif-mode: 0 :- receiver mode
14 1 :- transmitter mode
15 - xlnx,aud_clk_i: input audio clock value.
[all …]
/Documentation/devicetree/bindings/mfd/
Drockchip,rk808.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Zhong <zyw@rock-chips.com>
11 - Zhang Qing <zhangqing@rock-chips.com>
20 - rockchip,rk808
28 '#clock-cells':
30 See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
33 clock-output-names:
35 From common clock binding to override the default output clock name.
[all …]

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