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/Documentation/devicetree/bindings/pinctrl/
Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
23 description: disable any pin bias
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
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Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
38 gpio-controller: true
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Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
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Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
44 gpio-controller: true
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Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
25 | |--- PAD_GPIO[63]
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Dsprd,pinctrl.txt16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
46 and set the pin sleep related configuration as "input-enable", which
48 input enable automatically.
54 "sprd,sleep-mode" property to set pin sleep mode.
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Dste,nomadik.txt4 - compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl"
6 - nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 parameters, such as input, output, pull up, pull down...
23 (see pinctrl-bindings.txt):
26 - function: A string containing the name of the function to mux to the
28 - groups : An array of strings. Each string contains the name of a pin
30 set-up.
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Dsprd,sc9860-pinctrl.txt7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
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Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
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Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
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Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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Dawinic,aw9523-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
13 The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function
18 const: awinic,aw9523-pinctrl
23 '#gpio-cells':
26 include/dt-bindings/gpio/gpio.h
29 gpio-controller: true
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Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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Dnuvoton,ma35d1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shan-Chun Hung <schung@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
14 - $ref: pinctrl.yaml#
19 - nuvoton,ma35d1-pinctrl
24 '#address-cells':
27 '#size-cells':
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Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
26 reg-names: true
28 gpio-controller: true
[all …]
Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
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Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
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Dmediatek,mt8183-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
17 const: mediatek,mt8183-pinctrl
23 reg-names:
25 - const: iocfg0
26 - const: iocfg1
27 - const: iocfg2
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Dbrcm,bcm11351-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 - $ref: pinctrl.yaml#
19 const: brcm,bcm11351-pinctrl
25 '-pins$':
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/Documentation/ABI/testing/
Dsysfs-bus-iio-filter-admv88183 Contact: linux-iio@vger.kernel.org
8 - auto -> Adjust bandpass filter to track changes in input clock rate.
9 - manual -> disable/unregister the clock rate notifier / input clock tracking.
10 - bypass -> bypass low pass filter, high pass filter and disable/unregister
15 Contact: linux-iio@vger.kernel.org
Dsysfs-bus-iio-adc-mcp35643 Contact: linux-iio@vger.kernel.org
6 circuit of the Delta-Sigma modulator. The different BOOST
12 Contact: linux-iio@vger.kernel.org
15 the current biasing circuit of the Delta-Sigma modulator.
19 Contact: linux-iio@vger.kernel.org
21 This attribute is used to enable the analog input multiplexer
22 auto-zeroing algorithm (the input multiplexer and the ADC
26 input as VIN+/VIN-, one with VIN+/VIN- inverted. In this case the
30 ultra-low offset without any digital calibration. The resulting
35 Write '1' to enable it, write '0' to disable it.
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/Documentation/devicetree/bindings/net/
Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
29 allowable by a module in the slot, in milli-Watts. Presently, modules can
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/Documentation/devicetree/bindings/hwmon/
Dti,ina3221.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
20 ti,single-shot:
22 This chip has two power modes: single-shot (chip takes one measurement
25 hardware monitor type device, but the single-shot mode is more power-
26 friendly and useful for battery-powered device which cares power
29 If this property is present, the single-shot mode will be used, instead
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