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/Documentation/devicetree/bindings/mtd/
Dhisi504-nand.txt5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
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Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
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Dnxp-spifi.txt4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
19 - resets : phandle + reset specifier
22 compatible property as specified in bindings/mtd/jedec,spi-nor.txt
25 - spi-cpol : Controller only supports mode 0 and 3 so either
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Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
19 - marvell,ac5-nand-controller
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/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/Documentation/admin-guide/
Dpstore-blk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
10 block device and non-block device before the system crashes. You can get
13 mount -t pstore pstore /sys/fs/pstore
17 ---------------------
27 Configurations for driver are all about block device and non-block device,
31 -----------------------
45 The block device to use. Most of the time, it is a partition of block device.
51 #. /dev/<disk_name><decimal> represents the device number of partition - device
52 number of disk plus the partition number
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Dinit.rst6 This document provides some high-level reasons for failure
14 partition), required drivers such as storage hardware (such as SCSI or
16 modules, to be pre-loaded by an initrd).
19 --> initial console unavailable. E.g. some serial consoles are unreliable
20 due to serial IRQ issues (e.g. missing interrupt-based configuration).
24 dependencies of the init binary such as ``/lib/ld-linux.so.2`` missing or
25 broken. Use ``readelf -d <INIT>|grep NEEDED`` to find out which libraries
30 hardware. In case you tried loading a non-binary file here (shell script?),
34 simple non-script binary such as ``/bin/sh`` and confirm its successful
43 - Implement the various ``run_init_process()`` invocations via a struct array
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/Documentation/devicetree/bindings/spi/
Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-timer.txt4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
10 - fsl,available-ranges: use <start count> style section to define which
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
19 /* Note that this requires #interrupt-cells to be 4 */
21 compatible = "fsl,mpic-global-timer";
24 /* Another AMP partition is using timers 0 and 1 */
25 fsl,available-ranges = <2 2>;
32 compatible = "fsl,mpic-global-timer";
/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Felix Fietkau <nbd@nbd.name>
12 - Lorenzo Bianconi <lorenzo@kernel.org>
13 - Ryder Lee <ryder.lee@mediatek.com>
25 - mediatek,mt76
26 - mediatek,mt7628-wmac
27 - mediatek,mt7622-wmac
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/Documentation/devicetree/bindings/perf/
Dspe-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
14 performance sample data using an in-memory trace buffer.
18 const: arm,statistical-profiling-extension-v1
24 supported on a subset of the CPUs, please consult the arm,gic-v3 binding
25 for details on describing a PPI partition.
30 - compatible
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/Documentation/arch/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
75 +---+---+---+---------------+
79 +---+---+---+---------------+
81 +---+---+---+---------------+
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Dhvcs.rst24 3.1 Built-in:
40 ppc64 system. Physical hardware consoles per partition are not practical
55 major and minor numbers are associated with each vty-server. Directions
68 built into the kernel. If not, the default can be over-ridden by inserting
71 3.1 Built-in:
72 -------------
77 Device Drivers --->
78 Character devices --->
84 -----------
89 Device Drivers --->
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/Documentation/devicetree/bindings/arm/
Darm,trace-buffer-extension.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Anshuman Khandual <anshuman.khandual@arm.com>
26 - const: arm,trace-buffer-extension
32 the arm,gic-v3 binding for details on describing a PPI partition.
36 - compatible
37 - interrupts
43 - |
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/Documentation/scsi/
Daha152x.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
8 Copyright |copy| 1993-1999 Jürgen Fischer <fischer@norbit.de>
14 bottom-half handler complete()).
27 IRQ interrupt level (9-12; default 11)
28 SCSI_ID scsi id of controller (0-7; default 7)
42 - DAUTOCONF
43 use configuration the controller reports (AHA-152x only)
45 - DSKIP_BIOSTEST
46 Don't test for BIOS signature (AHA-1510 or disabled BIOS)
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/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
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/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
32 "#size-cells":
44 IFC may have one or two interrupts. If two interrupt specifiers are
45 present, the first is the "common" interrupt (CM_EVTER_STAT), and the
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/Documentation/power/
Dswsusp.rst15 ...bye bye root partition.
34 Swap partition:
47 - If you feel ACPI works pretty well on your system, you might try::
51 - If you would like to write hibernation image to swap and then suspend
56 - If you have SATA disks, you'll need recent kernels with SATA suspend
58 are built into kernel -- not modules. [There's way to make
68 - The resume process checks for the presence of the resume device,
72 - The resume process may be triggered in two ways:
81 read-only) otherwise data may be corrupted.
87 Last revised: 2003-10-20 by Pavel Machek
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/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
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/Documentation/virt/gunyah/
Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
10 message-queue
12 Gunyah is a Type-1 hypervisor which is independent of any OS kernel, and runs in
15 security and can support a much smaller trusted computing base than a Type-2
19 https://github.com/quic/gunyah-hypervisor.
23 - Scheduling:
25 A scheduler for virtual CPUs (vCPUs) on physical CPUs enables time-sharing
30 its own. The default is a real-time priority with round-robin scheduler.
31 2. "Proxy" scheduling in which an owner-VM can donate the remainder of its
32 own vCPU's time slice to an owned-VM's vCPU via a hypercall.
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/Documentation/ABI/stable/
Dsysfs-driver-ib_srp1 What: /sys/class/infiniband_srp/srp-<hca>-<port_number>/add_target
4 Contact: linux-rdma@vger.kernel.org
7 a comma-separated list of login parameters to this sysfs
10 * id_ext, a 16-digit hexadecimal number specifying the eight
11 byte identifier extension in the 16-byte SRP target port
14 * ioc_guid, a 16-digit hexadecimal number specifying the eight
15 byte I/O controller GUID portion of the 16-byte target port
17 * dgid, a 32-digit hexadecimal number specifying the
19 * pkey, a four-digit hexadecimal number specifying the
20 InfiniBand partition key.
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Dsysfs-bus-vmbus6 Users: Daemon that sets up swap partition/file for hibernation.
57 attached, or -1 if the node is unknown.
63 Description: Directory for per-channel information
77 Description: Host to guest channel interrupt mask
93 Description: Guest to host channel interrupt mask
100 Description: Channel interrupt pending state. This file is available only for
130 Description: Number of times we have taken an interrupt (incoming)
/Documentation/arch/m68k/
Dkernel-options.rst9 Author: Roman.Hodek@informatik.uni-erlangen.de (Roman Hodek)
11 Update: jds@kom.auc.dk (Jes Sorensen) and faq@linux-m68k.org (Chris Lawrence)
58 ----------
76 /dev/ram: -> 0x0100 (initial ramdisk)
77 /dev/hda: -> 0x0300 (first IDE disk)
78 /dev/hdb: -> 0x0340 (second IDE disk)
79 /dev/sda: -> 0x0800 (first SCSI disk)
80 /dev/sdb: -> 0x0810 (second SCSI disk)
81 /dev/sdc: -> 0x0820 (third SCSI disk)
82 /dev/sdd: -> 0x0830 (forth SCSI disk)
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/Documentation/devicetree/bindings/crypto/
Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
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