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/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
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/Documentation/userspace-api/
Dlandlock.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. Copyright © 2017-2020 Mickaël Salaün <mic@digikod.net>
3 .. Copyright © 2019-2020 ANSSI
4 .. Copyright © 2021-2022 Microsoft Corporation
16 new security layers in addition to the existing system-wide access-controls.
23 ``dmesg | grep landlock || journalctl -kb -g landlock`` .
48 ----------------------------------------
59 to be explicit about the denied-by-default access rights.
61 .. code-block:: c
90 on, it is safer to follow a best-effort security approach. Indeed, we
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/Documentation/process/
D4.Coding.rst6 While there is much to be said for a solid and community-oriented design
19 ---------
25 :ref:`Documentation/process/coding-style.rst <codingstyle>`. For much of
38 strangely-formatted code.
43 giving up a degree of control in a number of ways - including control over
49 as a way of getting their name into the kernel changelogs - or both. But
59 80-column limit, for example), just do it.
61 Note that you can also use the ``clang-format`` tool to help you with
62 these rules, to quickly re-format parts of your code automatically,
66 See the file :ref:`Documentation/dev-tools/clang-format.rst <clangformat>`
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/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
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/Documentation/mm/damon/
Ddesign.rst1 .. SPDX-License-Identifier: GPL-2.0
13 The monitoring-related information including the monitoring request
14 specification and DAMON-based operation schemes are stored in a data structure
19 To know how user-space can do the configurations and start/stop DAMON, refer to
26 DAMON subsystem is configured with three layers including
28 - :ref:`Operations Set <damon_operations_set>`: Implements fundamental
30 address-space and available set of software/hardware primitives,
31 - :ref:`Core <damon_core_logic>`: Implements core logics including monitoring
32 overhead/accuracy control and access-aware system operations on top of the
34 - :ref:`Modules <damon_modules>`: Implements kernel modules for various
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/Documentation/admin-guide/pm/
Dcpufreq.rst1 .. SPDX-License-Identifier: GPL-2.0
20 Operating Performance Points or P-states (in ACPI terminology). As a rule,
24 time (or the more power is drawn) by the CPU in the given P-state. Therefore
29 as possible and then there is no reason to use any P-states different from the
30 highest one (i.e. the highest-performance frequency/voltage configuration
38 put into different P-states.
41 capacity, so as to decide which P-states to put the CPUs into. Of course, since
52 (CPU Frequency scaling) subsystem that consists of three layers of code: the
64 information on the available P-states (or P-state ranges in some cases) and
65 access platform-specific hardware interfaces to change CPU P-states as requested
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/Documentation/networking/device_drivers/can/ctu/
Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
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/Documentation/userspace-api/media/v4l/
Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-controls:
24 .. _mpeg-control-id:
27 -----------------
35 .. _v4l2-mpeg-stream-type:
40 enum v4l2_mpeg_stream_type -
41 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
48 .. flat-table::
49 :header-rows: 0
50 :stub-columns: 0
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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