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/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
Dopen-pic.txt13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
Datmel,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
[all …]
Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
Damazon,al-fic.txt5 - compatible: should be "amazon,al-fic"
6 - reg: physical base address and size of the registers
7 - interrupt-controller: identifies the node as an interrupt controller
8 - #interrupt-cells : must be 2. Specifies the number of cells needed to encode
9 an interrupt source. Supported trigger types are low-to-high edge
10 triggered and active high level-sensitive.
11 - interrupts: describes which input line in the interrupt parent, this
20 amazon_fic: interrupt-controller@fd8a8500 {
21 compatible = "amazon,al-fic";
22 interrupt-controller;
[all …]
Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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/Documentation/devicetree/bindings/gpio/
Dsodaville.txt14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
[all …]
Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
Dcdns,gpio.txt4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
16 - ngpios: integer number of gpio lines supported by this controller, up to 32.
17 - interrupts: interrupt specifier for the controllers interrupt.
18 - interrupt-controller: marks the device as an interrupt controller. When
19 defined, interrupts, interrupt-parent and #interrupt-cells
[all …]
Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
53 controller, are both extremely non-linear. The header file
54 <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
65 module and the sets-of-ports as "controllers".
69 one of the interrupt signals generated by a set-of-ports. The intent is
[all …]
/Documentation/virt/kvm/devices/
Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
/Documentation/virt/
Dparavirt_ops.rst1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
34 because they include sensitive instructions or some code paths in
/Documentation/devicetree/bindings/pinctrl/
Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
/Documentation/admin-guide/pm/
Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
23 Users may have some latency sensitive workloads where they do not want any
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
50 This is a read-only attribute. If users adjust min_freq_khz,
63 -----------------------------------------------------------------
72 The current sysfs interface supports controls at package and die level.
74 fabric cluster level.
[all …]
/Documentation/userspace-api/media/v4l/
Dext-ctrls-image-source.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _image-source-controls:
9 The Image Source control class is intended for low-level control of
15 .. _image-source-control-id:
28 same sub-device.
58 The unit cell consists of the whole area of the pixel, sensitive and
59 non-sensitive.
64 .. flat-table:: struct v4l2_area
65 :header-rows: 0
66 :stub-columns: 0
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
[all …]
/Documentation/scheduler/
Dsched-nice-design.rst6 nice-levels implementation in the new Linux scheduler.
12 scheduler, (otherwise we'd have done it long ago) because nice level
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
34 -*----------------------------------*-----> [nice level]
35 -20 | +19
52 right minimal granularity - and this translates to 5% CPU utilization.
53 But the fundamental HZ-sensitive property for nice+19 still remained,
56 too _strong_ :-)
59 within the constraints of HZ and jiffies and their nasty design level
63 about Linux's nice level support was its asymmetry around the origin
[all …]
/Documentation/security/
Dself-protection.rst2 Kernel Self-Protection
5 Kernel self-protection is the design and implementation of systems and
13 In the worst-case scenario, we assume an unprivileged local attacker
15 cases, bugs being exploited will not provide this level of access,
23 The goals for successful self-protection systems would be that they
24 are effective, on by default, require no opt-in by developers, have no
36 from limiting the exposed APIs available to userspace, making in-kernel
41 --------------------------------
47 Executable code and read-only data must not be writable
61 writable, data is not executable, and read-only data is neither writable
[all …]
/Documentation/power/
Dswsusp.rst47 - If you feel ACPI works pretty well on your system, you might try::
51 - If you would like to write hibernation image to swap and then suspend
56 - If you have SATA disks, you'll need recent kernels with SATA suspend
58 are built into kernel -- not modules. [There's way to make
68 - The resume process checks for the presence of the resume device,
72 - The resume process may be triggered in two ways:
81 read-only) otherwise data may be corrupted.
87 Last revised: 2003-10-20 by Pavel Machek
90 -------------------------
163 between 0-640KB. That way, I'd have to make sure that 0-640KB is free
[all …]
/Documentation/ABI/testing/
Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
23 means different throttling level. When reading this file, it
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
[all …]

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