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Searched +full:lpc3220 +full:- +full:adc (Results 1 – 3 of 3) sorted by relevance

/Documentation/devicetree/bindings/iio/adc/
Dnxp,lpc3220-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,lpc3220-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC3220 SoC ADC controller
10 - Gregory Clement <gregory.clement@bootlin.com>
17 const: nxp,lpc3220-adc
25 vref-supply: true
27 "#io-channel-cells":
31 - compatible
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/Documentation/devicetree/bindings/interrupt-controller/
Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
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/Documentation/devicetree/bindings/input/touchscreen/
Dlpc32xx-tsc.txt4 - compatible: must be "nxp,lpc3220-tsc"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: The TSC/ADC interrupt
12 compatible = "nxp,lpc3220-tsc";
14 interrupt-parent = <&mic>;